arm: 96b_stm32_sensor_mez: spi: Enable SPI4

This patch enables SPI4 on the 96Boards STM32 Sensors Mezzanine.
SPI4 has been broken out to a Grove Connector on the board.

Changes:

- Updated board dts to enable spi4
- Updated board Kconfig
- Updated board documentation
- Update board pinmux
- Updated stm32f4 pinmux header file
- Updated stm32f401 dtsi
- Updated stm32f4 defconfig to enable PORTE GPIO
- Added board to spi_loopback test

Test: spi_loopback test passed

Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
This commit is contained in:
Sahaj Sarup 2019-12-14 14:22:45 +05:30 committed by Maureen Helm
commit d072ab83ac
8 changed files with 53 additions and 4 deletions

View file

@ -100,6 +100,10 @@
status = "okay"; status = "okay";
}; };
&spi4 {
status = "okay";
};
&timers3 { &timers3 {
status = "okay"; status = "okay";

View file

@ -59,6 +59,9 @@ config SPI_1
config SPI_2 config SPI_2
default y default y
config SPI_4
default y
config SPI_STM32_INTERRUPT config SPI_STM32_INTERRUPT
default y default y

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@ -42,7 +42,7 @@ Hardware
- GPIO with external interrupt capability - GPIO with external interrupt capability
- UART - UART
- I2C (2) - I2C (2)
- SPI (2) - SPI (3)
- I2S (1) - I2S (1)
Supported Features Supported Features
@ -125,9 +125,10 @@ I2C2 goes to the Groove connectors and can be used to attach external sensors.
SPI SPI
--- ---
96Boards STM32 Sensor Mezzanine board has 2 SPIs. SPI1 is used in slave mode 96Boards STM32 Sensor Mezzanine board has 3 SPIs. SPI1 is used in slave mode
as the communication bus with the AP. SPI2 is used in master mode to control as the communication bus with the AP. SPI2 is used in master mode to control
the LSM6DS3H sensor. The default SPI mapping is: the LSM6DS3H sensor. SPI4 is broken out to Grove Connector J5.
The default SPI mapping is:
- SPI1_NSS : PA4 - SPI1_NSS : PA4
- SPI1_SCK : PA5 - SPI1_SCK : PA5
@ -137,6 +138,10 @@ the LSM6DS3H sensor. The default SPI mapping is:
- SPI2_SCK : PD3 - SPI2_SCK : PD3
- SPI2_MISO : PB14 - SPI2_MISO : PB14
- SPI2_MOSI : PB15 - SPI2_MOSI : PB15
- SPI4_NSS : PE11
- SPI4_SCK : PE12
- SPI4_MISO : PE13
- SPI4_MOSI : PE14
PWM PWM
--- ---

View file

@ -58,6 +58,16 @@ static const struct pin_config pinconf[] = {
{STM32_PIN_PB14, STM32F4_PINMUX_FUNC_PB14_SPI2_MISO}, {STM32_PIN_PB14, STM32F4_PINMUX_FUNC_PB14_SPI2_MISO},
{STM32_PIN_PB15, STM32F4_PINMUX_FUNC_PB15_SPI2_MOSI}, {STM32_PIN_PB15, STM32F4_PINMUX_FUNC_PB15_SPI2_MOSI},
#endif /* CONFIG_SPI_2 */ #endif /* CONFIG_SPI_2 */
#ifdef CONFIG_SPI_4
#ifdef CONFIG_SPI_STM32_USE_HW_SS
{STM32_PIN_PE11, STM32F4_PINMUX_FUNC_PE11_SPI4_NSS |
STM32_OSPEEDR_VERY_HIGH_SPEED},
#endif /* CONFIG_SPI_STM32_USE_HW_SS */
{STM32_PIN_PE12, STM32F4_PINMUX_FUNC_PE12_SPI4_SCK |
STM32_OSPEEDR_VERY_HIGH_SPEED},
{STM32_PIN_PE13, STM32F4_PINMUX_FUNC_PE13_SPI4_MISO},
{STM32_PIN_PE14, STM32F4_PINMUX_FUNC_PE14_SPI4_MOSI},
#endif /* CONFIG_SPI_4 */
#ifdef CONFIG_I2S_2 #ifdef CONFIG_I2S_2
{STM32_PIN_PC7, STM32F4_PINMUX_FUNC_PC7_I2S2_CK}, {STM32_PIN_PC7, STM32F4_PINMUX_FUNC_PC7_I2S2_CK},
{STM32_PIN_PC1, STM32F4_PINMUX_FUNC_PC1_I2S2_SD}, {STM32_PIN_PC1, STM32F4_PINMUX_FUNC_PC1_I2S2_SD},

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@ -448,9 +448,21 @@
#define STM32F4_PINMUX_FUNC_PE8_UART7_TX \ #define STM32F4_PINMUX_FUNC_PE8_UART7_TX \
(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP) (STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP)
#define STM32F4_PINMUX_FUNC_PE11_SPI4_NSS \
(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
#define STM32F4_PINMUX_FUNC_PE12_SPI4_SCK \
(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
#define STM32F4_PINMUX_FUNC_PE13_SPI4_MISO \
(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
#define STM32F4_PINMUX_FUNC_PE13_PWM1_CH3 \ #define STM32F4_PINMUX_FUNC_PE13_PWM1_CH3 \
(STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_PULLUP) (STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_PULLUP)
#define STM32F4_PINMUX_FUNC_PE14_SPI4_MOSI \
(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
/* Port F */ /* Port F */
#define STM32F4_PINMUX_FUNC_PF0_I2C2_SDA \ #define STM32F4_PINMUX_FUNC_PF0_I2C2_SDA \
(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP) (STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)

View file

@ -30,6 +30,17 @@
label = "SPI_3"; label = "SPI_3";
}; };
spi4: spi@40013400 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
interrupts = <84 5>;
status = "disabled";
label = "SPI_4";
};
i2s2: i2s@40003800 { i2s2: i2s@40003800 {
compatible = "st,stm32-i2s"; compatible = "st,stm32-i2s";
#address-cells = <1>; #address-cells = <1>;

View file

@ -14,7 +14,7 @@ config NUM_IRQS
if GPIO_STM32 if GPIO_STM32
config GPIO_STM32_PORTE config GPIO_STM32_PORTE
default n default y
config GPIO_STM32_PORTH config GPIO_STM32_PORTH
default n default n

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@ -0,0 +1,4 @@
CONFIG_SPI_LOOPBACK_CS_GPIO=y
CONFIG_SPI_LOOPBACK_CS_CTRL_GPIO_DRV_NAME="GPIOE"
CONFIG_SPI_LOOPBACK_CS_CTRL_GPIO_PIN=11
CONFIG_SPI_LOOPBACK_DRV_NAME="SPI_4"