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boards: hexiwear_k64: add pinctrl groups for hexiwear_k64

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Add pinctrl groups for hexiwear_k64, and enable pinctrl

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse 2022-02-28 15:40:31 -06:00 • committed by David Leach
commit d0352f4921
4 changed files with 68 additions and 34 deletions
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60
boards/arm/hexiwear_k64/hexiwear_k64-pinctrl.dtsi Normal file
View file

@ -0,0 +1,60 @@
/*
* NOTE: Autogenerated file by kinetis_signal2dts.py
* for MK64FN1M0VDC12/signal_configuration.xml
*
* Copyright (c) 2022, NXP
* SPDX-License-Identifier: Apache-2.0
*/
#include <nxp/kinetis/MK64FN1M0VDC12-pinctrl.h>
&pinctrl {
ftm3_default: ftm3_default {
group0 {
pinmux = <FTM3_CH4_PTC8>,
<FTM3_CH0_PTD0>;
drive-strength = "low";
slew-rate = "fast";
};
};
i2c0_default: i2c0_default {
group0 {
pinmux = <I2C0_SCL_PTB0>,
<I2C0_SDA_PTB1>;
drive-strength = "low";
drive-open-drain;
slew-rate = "fast";
};
};
i2c1_default: i2c1_default {
group0 {
pinmux = <I2C1_SCL_PTC10>,
<I2C1_SDA_PTC11>;
drive-strength = "low";
drive-open-drain;
slew-rate = "fast";
};
};
uart0_default: uart0_default {
group0 {
pinmux = <UART0_RX_PTB16>,
<UART0_TX_PTB17>;
drive-strength = "low";
slew-rate = "fast";
};
};
uart4_default: uart4_default {
group0 {
pinmux = <UART4_RX_PTE25>,
<UART4_TX_PTE24>;
drive-strength = "low";
slew-rate = "fast";
};
};
};

29
boards/arm/hexiwear_k64/hexiwear_k64.dts
View file

@ -2,8 +2,9 @@
/dts-v1/;
#include <nxp/MK64FN1M0VDC12.dtsi>
#include <nxp/nxp_k6x.dtsi>
#include <dt-bindings/pwm/pwm.h>
#include "hexiwear_k64-pinctrl.dtsi"
/ {
model = "Hexiwear K64 board";
@ -80,13 +81,13 @@
status = "okay";
compatible = "nxp,kinetis-ftm-pwm";
#pwm-cells = <3>;
pinctrl-0 = <&FTM3_CH4_PTC8 &FTM3_CH5_PTC9 &FTM3_CH0_PTD0>;
pinctrl-0 = <&ftm3_default>;
pinctrl-names = "default";
};
&i2c0 {
status = "okay";
pinctrl-0 = <&I2C0_SCL_PTB0 &I2C0_SDA_PTB1>;
pinctrl-0 = <&i2c0_default>;
pinctrl-names = "default";
max30101@57 {
@ -97,17 +98,9 @@
};
};
&I2C0_SCL_PTB0 {
drive-open-drain;
};
&I2C0_SDA_PTB1 {
drive-open-drain;
};
&i2c1 {
status = "okay";
pinctrl-0 = <&I2C1_SCL_PTC10 &I2C1_SDA_PTC11>;
pinctrl-0 = <&i2c1_default>;
pinctrl-names = "default";
fxos8700@1e {
@ -127,25 +120,17 @@
};
};
&I2C1_SCL_PTC10 {
drive-open-drain;
};
&I2C1_SDA_PTC11 {
drive-open-drain;
};
&uart0 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&UART0_RX_PTB16 &UART0_TX_PTB17>;
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
};
&uart4 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&UART4_RX_PTE25 &UART4_TX_PTE24>;
pinctrl-0 = <&uart4_default>;
pinctrl-names = "default";
};

1
boards/arm/hexiwear_k64/hexiwear_k64_defconfig
View file

@ -9,6 +9,7 @@ CONFIG_SERIAL=y
CONFIG_CORTEX_M_SYSTICK=y
CONFIG_GPIO=y
CONFIG_PINMUX=y
CONFIG_PINCTRL=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000
CONFIG_OSC_LOW_POWER=y
CONFIG_ARM_MPU=y

12
boards/arm/hexiwear_k64/pinmux.c
View file

@ -62,18 +62,6 @@ static int hexiwear_k64_pinmux_init(const struct device *dev)
| PORT_PCR_ODE_MASK);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart0), okay) && CONFIG_SERIAL
/* UART0 RX, TX */
pinmux_pin_set(portb, 16, PORT_PCR_MUX(kPORT_MuxAlt3));
pinmux_pin_set(portb, 17, PORT_PCR_MUX(kPORT_MuxAlt3));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart4), okay) && CONFIG_SERIAL
/* UART4 RX, TX - BLE */
pinmux_pin_set(porte, 24, PORT_PCR_MUX(kPORT_MuxAlt3));
pinmux_pin_set(porte, 25, PORT_PCR_MUX(kPORT_MuxAlt3));
#endif
#if defined(CONFIG_MAX30101) && DT_NODE_HAS_STATUS(DT_NODELABEL(gpioa), okay)
const struct device *gpioa =
device_get_binding(DT_LABEL(DT_NODELABEL(gpioa)));