x86: move soc/cpu to top-level under soc/

Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>

soc/x86/apollo_lake/CMakeLists.txt

@@ -0,0 +1,7 @@
+zephyr_library()
+zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
+
+zephyr_cc_option(-march=silvermont)
+zephyr_cc_option_fallback(-march=atom -mtune=silvermont)
+
+zephyr_library_sources(soc.c)

soc/x86/apollo_lake/Kconfig.defconfig

@@ -0,0 +1,75 @@
+#
+# Kconfig - Apollo Lake SoC configuration options
+#
+# Copyright (c) 2018 Intel Corporation
+# Copyright (c) 2014-2015 Wind River Systems, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_APOLLO_LAKE
+
+config SOC
+	default "apollo_lake"
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 150000000 if LOAPIC_TIMER
+	default 25000000  if HPET_TIMER
+
+config CLFLUSH_DETECT
+	def_bool y if CACHE_FLUSHING
+
+if UART_NS16550
+
+config UART_NS16550_PCI
+	def_bool y if PCI
+
+config UART_NS16550_PORT_0
+	def_bool y
+
+if UART_NS16550_PORT_0
+
+config UART_NS16550_PORT_0_OPTIONS
+	default 0
+
+config UART_NS16550_PORT_0_PCI
+	def_bool y if PCI
+
+endif # UART_NS16550_PORT_0
+
+config UART_NS16550_PORT_1
+	def_bool y
+
+if UART_NS16550_PORT_1
+
+config UART_NS16550_PORT_1_OPTIONS
+	default 0
+
+config UART_NS16550_PORT_1_PCI
+	def_bool y if PCI
+
+endif # UART_NS16550_PORT_1
+
+if UART_NS16550_PORT_2
+
+config UART_NS16550_PORT_2_OPTIONS
+	default 0
+
+config UART_NS16550_PORT_2_PCI
+	def_bool y if PCI
+
+endif # UART_NS16550_PORT_2
+
+if UART_NS16550_PORT_3
+
+config UART_NS16550_PORT_3_OPTIONS
+	default 0
+
+config UART_NS16550_PORT_3_PCI
+	def_bool y if PCI
+
+endif # UART_NS16550_PORT_3
+
+endif # UART_NS16550
+
+endif # SOC_APOLLO_LAKE

soc/x86/apollo_lake/Kconfig.soc

@@ -0,0 +1,10 @@
+#
+# Copyright (c) 2018 Intel Corporation Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_APOLLO_LAKE
+	bool "Intel Apollo Lake Soc"
+	select CPU_APOLLO_LAKE
+	select BOOTLOADER_UNKNOWN

soc/x86/apollo_lake/dts.fixup

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2018 Intel Corporation Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* SoC level DTS fixup file */
+
+#define CONFIG_PHYS_RAM_ADDR                    CONFIG_SRAM_BASE_ADDRESS
+
+#define CONFIG_PHYS_LOAD_ADDR                   CONFIG_FLASH_BASE_ADDRESS
+
+#define CONFIG_RAM_SIZE                         CONFIG_SRAM_SIZE
+
+#define CONFIG_ROM_SIZE                         CONFIG_FLASH_SIZE
+
+#define CONFIG_IOAPIC_BASE_ADDRESS              INTEL_IOAPIC_FEC00000_BASE_ADDRESS
+
+/* End of SoC Level DTS fixup file */

soc/x86/apollo_lake/linker.ld

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2011-2014, Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Linker command/script file
+ *
+ * This is the linker script for both standard images and XIP images.
+ */
+
+#include <autoconf.h>
+#include <generated_dts_board.h>
+/* physical address where the kernel is loaded */
+#define PHYS_LOAD_ADDR CONFIG_PHYS_LOAD_ADDR
+
+/* physical address of RAM */
+#ifdef CONFIG_XIP
+  #define PHYS_RAM_ADDR    CONFIG_PHYS_RAM_ADDR
+#else  /* !CONFIG_XIP */
+  #define PHYS_RAM_ADDR    PHYS_LOAD_ADDR
+#endif /* CONFIG_XIP */
+
+MEMORY
+    {
+#ifdef CONFIG_XIP
+    ROM (rx)        : ORIGIN = PHYS_LOAD_ADDR, LENGTH = CONFIG_ROM_SIZE*1K
+    RAM (wx)        : ORIGIN = PHYS_RAM_ADDR, LENGTH = CONFIG_RAM_SIZE*1K
+#else  /* !CONFIG_XIP */
+    RAM (wx)	    : ORIGIN = PHYS_LOAD_ADDR, LENGTH = CONFIG_RAM_SIZE*1K
+#endif /* CONFIG_XIP */
+
+    /*
+     * It doesn't matter where this region goes as it is stripped from the
+     * final ELF image. The address doesn't even have to be valid on the
+     * target. However, it shouldn't overlap any other regions.
+     */
+
+    IDT_LIST        : ORIGIN = 2K, LENGTH = 2K
+#ifdef CONFIG_X86_MMU
+    MMU_LIST	    : ORIGIN = 4k, LENGTH = 1K
+#endif
+    }
+
+#include <arch/x86/linker.ld>
+

soc/x86/apollo_lake/soc.c

@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2018, Intel Corporation
+ * Copyright (c) 2011-2015, Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for the Apollo Lake SoC
+ *
+ * This module provides routines to initialize and support soc-level hardware
+ * for the Apollo Lake SoC.
+ */
+
+#include <kernel.h>
+#include "soc.h"
+#include <uart.h>
+#include <device.h>
+#include <init.h>
+
+#ifdef CONFIG_X86_MMU
+/* loapic */
+MMU_BOOT_REGION(CONFIG_LOAPIC_BASE_ADDRESS, 4 * 1024, MMU_ENTRY_WRITE);
+
+/* ioapic */
+MMU_BOOT_REGION(CONFIG_IOAPIC_BASE_ADDRESS, 1024 * 1024, MMU_ENTRY_WRITE);
+
+#ifdef CONFIG_HPET_TIMER
+MMU_BOOT_REGION(CONFIG_HPET_TIMER_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
+#endif  /* CONFIG_HPET_TIMER */
+
+/* for UARTs */
+#ifdef CONFIG_UART_NS16550
+
+#ifdef CONFIG_UART_NS16550_PORT_0
+MMU_BOOT_REGION(CONFIG_UART_NS16550_PORT_0_BASE_ADDR, 0x1000,
+		(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
+#endif
+
+#ifdef CONFIG_UART_NS16550_PORT_1
+MMU_BOOT_REGION(CONFIG_UART_NS16550_PORT_1_BASE_ADDR, 0x1000,
+		(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
+#endif
+
+#ifdef CONFIG_UART_NS16550_PORT_2
+MMU_BOOT_REGION(CONFIG_UART_NS16550_PORT_2_BASE_ADDR, 0x1000,
+		(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
+#endif
+
+#ifdef CONFIG_UART_NS16550_PORT_3
+MMU_BOOT_REGION(CONFIG_UART_NS16550_PORT_3_BASE_ADDR, 0x1000,
+		(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
+#endif
+
+#endif  /* CONFIG_UART_NS16550 */
+
+/* for I2C controllers */
+#ifdef CONFIG_I2C
+
+#ifdef CONFIG_I2C_0
+MMU_BOOT_REGION(CONFIG_I2C_0_BASE_ADDR, 0x1000,
+		(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
+#endif
+
+#ifdef CONFIG_I2C_1
+MMU_BOOT_REGION(CONFIG_I2C_1_BASE_ADDR, 0x1000,
+		(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
+#endif
+
+#ifdef CONFIG_I2C_2
+MMU_BOOT_REGION(CONFIG_I2C_2_BASE_ADDR, 0x1000,
+		(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
+#endif
+
+#ifdef CONFIG_I2C_3
+MMU_BOOT_REGION(CONFIG_I2C_3_BASE_ADDR, 0x1000,
+		(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
+#endif
+
+#ifdef CONFIG_I2C_4
+MMU_BOOT_REGION(CONFIG_I2C_4_BASE_ADDR, 0x1000,
+		(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
+#endif
+
+#ifdef CONFIG_I2C_5
+MMU_BOOT_REGION(CONFIG_I2C_5_BASE_ADDR, 0x1000,
+		(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
+#endif
+
+#ifdef CONFIG_I2C_6
+MMU_BOOT_REGION(CONFIG_I2C_6_BASE_ADDR, 0x1000,
+		(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
+#endif
+
+#ifdef CONFIG_I2C_7
+MMU_BOOT_REGION(CONFIG_I2C_7_BASE_ADDR, 0x1000,
+		(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
+#endif
+
+#endif  /* CONFIG_I2C */
+
+#endif  /* CONFIG_X86_MMU */

soc/x86/apollo_lake/soc.h

@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2018, Intel Corporation
+ * Copyright (c) 2010-2015, Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Board configuration macros for the Apollo Lake SoC
+ *
+ * This header file is used to specify and describe soc-level aspects for
+ * the 'Apollo Lake' SoC.
+ */
+
+#ifndef __SOC_H_
+#define __SOC_H_
+
+#include <misc/util.h>
+
+#ifndef _ASMLANGUAGE
+#include <device.h>
+#include <random/rand32.h>
+#endif
+
+#ifdef CONFIG_PCI
+
+/*
+ * PCI definitions
+ */
+#define PCI_BUS_NUMBERS                         1
+
+#define PCI_CTRL_ADDR_REG                       0xCF8
+#define PCI_CTRL_DATA_REG                       0xCFC
+
+/**
+ * @brief Convert PCI interrupt PIN to IRQ
+ *
+ * BIOS should have assigned vectors linearly.
+ * If not, override this in board configuration.
+ */
+#define pci_pin2irq(bus, dev, pin)              (pin)
+
+
+/* UARTs */
+#ifdef CONFIG_UART_NS16550_PCI
+
+#ifdef CONFIG_UART_NS16550_PORT_0_PCI
+
+#define UART_NS16550_PORT_0_PCI_CLASS           0x11
+#define UART_NS16550_PORT_0_PCI_BUS             0
+#define UART_NS16550_PORT_0_PCI_DEV             18
+#define UART_NS16550_PORT_0_PCI_VENDOR_ID       0x8086
+#define UART_NS16550_PORT_0_PCI_DEVICE_ID       0x5abc
+#define UART_NS16550_PORT_0_PCI_FUNC            0
+#define UART_NS16550_PORT_0_PCI_BAR             0
+
+#endif /* CONFIG_UART_NS16550_PORT_0_PCI */
+
+#ifdef CONFIG_UART_NS16550_PORT_1_PCI
+
+#define UART_NS16550_PORT_1_PCI_CLASS           0x11
+#define UART_NS16550_PORT_1_PCI_BUS             0
+#define UART_NS16550_PORT_1_PCI_DEV             18
+#define UART_NS16550_PORT_1_PCI_VENDOR_ID       0x8086
+#define UART_NS16550_PORT_1_PCI_DEVICE_ID       0x5abe
+#define UART_NS16550_PORT_1_PCI_FUNC            1
+#define UART_NS16550_PORT_1_PCI_BAR             0
+
+#endif /* CONFIG_UART_NS16550_PORT_1_PCI */
+
+#ifdef CONFIG_UART_NS16550_PORT_2_PCI
+
+#define UART_NS16550_PORT_2_PCI_CLASS           0x11
+#define UART_NS16550_PORT_2_PCI_BUS             0
+#define UART_NS16550_PORT_2_PCI_DEV             18
+#define UART_NS16550_PORT_2_PCI_VENDOR_ID       0x8086
+#define UART_NS16550_PORT_2_PCI_DEVICE_ID       0x5ac0
+#define UART_NS16550_PORT_2_PCI_FUNC            2
+#define UART_NS16550_PORT_2_PCI_BAR             0
+
+#endif /* CONFIG_UART_NS16550_PORT_2_PCI */
+
+#ifdef CONFIG_UART_NS16550_PORT_3_PCI
+
+#define UART_NS16550_PORT_3_PCI_CLASS           0x11
+#define UART_NS16550_PORT_3_PCI_BUS             0
+#define UART_NS16550_PORT_3_PCI_DEV             18
+#define UART_NS16550_PORT_3_PCI_VENDOR_ID       0x8086
+#define UART_NS16550_PORT_3_PCI_DEVICE_ID       0x5aee
+#define UART_NS16550_PORT_3_PCI_FUNC            3
+#define UART_NS16550_PORT_3_PCI_BAR             0
+
+#endif /* CONFIG_UART_NS16550_PORT_3_PCI */
+
+#endif /* CONFIG_UART_NS16550_PCI */
+
+/* I2C controllers */
+#define I2C_DW_0_PCI_VENDOR_ID                  0x8086
+#define I2C_DW_0_PCI_DEVICE_ID                  0x5aac
+#define I2C_DW_0_PCI_CLASS                      0x11
+#define I2C_DW_0_PCI_BUS                        0
+#define I2C_DW_0_PCI_DEV                        16
+#define I2C_DW_0_PCI_FUNCTION                   0
+#define I2C_DW_0_PCI_BAR                        0
+
+#define I2C_DW_1_PCI_VENDOR_ID                  0x8086
+#define I2C_DW_1_PCI_DEVICE_ID                  0x5aae
+#define I2C_DW_1_PCI_CLASS                      0x11
+#define I2C_DW_1_PCI_BUS                        0
+#define I2C_DW_1_PCI_DEV                        16
+#define I2C_DW_1_PCI_FUNCTION                   1
+#define I2C_DW_1_PCI_BAR                        0
+
+#define I2C_DW_2_PCI_VENDOR_ID                  0x8086
+#define I2C_DW_2_PCI_DEVICE_ID                  0x5ab0
+#define I2C_DW_2_PCI_CLASS                      0x11
+#define I2C_DW_2_PCI_BUS                        0
+#define I2C_DW_2_PCI_DEV                        16
+#define I2C_DW_2_PCI_FUNCTION                   2
+#define I2C_DW_2_PCI_BAR                        0
+
+#define I2C_DW_3_PCI_VENDOR_ID                  0x8086
+#define I2C_DW_3_PCI_DEVICE_ID                  0x5ab2
+#define I2C_DW_3_PCI_CLASS                      0x11
+#define I2C_DW_3_PCI_BUS                        0
+#define I2C_DW_3_PCI_DEV                        16
+#define I2C_DW_3_PCI_FUNCTION                   3
+#define I2C_DW_3_PCI_BAR                        0
+
+#define I2C_DW_4_PCI_VENDOR_ID                  0x8086
+#define I2C_DW_4_PCI_DEVICE_ID                  0x5ab4
+#define I2C_DW_4_PCI_CLASS                      0x11
+#define I2C_DW_4_PCI_BUS                        0
+#define I2C_DW_4_PCI_DEV                        17
+#define I2C_DW_4_PCI_FUNCTION                   0
+#define I2C_DW_4_PCI_BAR                        0
+
+#define I2C_DW_5_PCI_VENDOR_ID                  0x8086
+#define I2C_DW_5_PCI_DEVICE_ID                  0x5ab6
+#define I2C_DW_5_PCI_CLASS                      0x11
+#define I2C_DW_5_PCI_BUS                        0
+#define I2C_DW_5_PCI_DEV                        17
+#define I2C_DW_5_PCI_FUNCTION                   1
+#define I2C_DW_5_PCI_BAR                        0
+
+#define I2C_DW_6_PCI_VENDOR_ID                  0x8086
+#define I2C_DW_6_PCI_DEVICE_ID                  0x5ab8
+#define I2C_DW_6_PCI_CLASS                      0x11
+#define I2C_DW_6_PCI_BUS                        0
+#define I2C_DW_6_PCI_DEV                        17
+#define I2C_DW_6_PCI_FUNCTION                   2
+#define I2C_DW_6_PCI_BAR                        0
+
+#define I2C_DW_7_PCI_VENDOR_ID                  0x8086
+#define I2C_DW_7_PCI_DEVICE_ID                  0x5aba
+#define I2C_DW_7_PCI_CLASS                      0x11
+#define I2C_DW_7_PCI_BUS                        0
+#define I2C_DW_7_PCI_DEV                        17
+#define I2C_DW_7_PCI_FUNCTION                   3
+#define I2C_DW_7_PCI_BAR                        0
+
+#endif /* CONFIG_PCI */
+
+#endif /* __SOC_H_ */