drivers: sensor: adxl372: Updated driver with RTIO stream functionality
Updated ADXL372 driver with RTIO stream functionality. RTIO stream is using both FIFO threshold and FIFO full triggers. Together with RTIO stream, RTIO async read is also implemented. Signed-off-by: Vladislav Pejic <vladislav.pejic@orioninc.com>
This commit is contained in:
Vladislav Pejic
Anas Nashif
parent
9356999229
commit
cfe64f7f1c
8 changed files with 957 additions and 21 deletions
445
drivers/sensor/adi/adxl372/adxl372_stream.c
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445
drivers/sensor/adi/adxl372/adxl372_stream.c
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@ -0,0 +1,445 @@
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/*
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* Copyright (c) 2024 Analog Devices Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/logging/log.h>
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#include <zephyr/drivers/sensor.h>
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#include "adxl372.h"
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LOG_MODULE_DECLARE(ADXL372, CONFIG_SENSOR_LOG_LEVEL);
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static void adxl372_irq_en_cb(struct rtio *r, const struct rtio_sqe *sqr, void *arg)
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{
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const struct device *dev = (const struct device *)arg;
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const struct adxl372_dev_config *cfg = dev->config;
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gpio_pin_interrupt_configure_dt(&cfg->interrupt, GPIO_INT_EDGE_TO_ACTIVE);
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}
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static void adxl372_fifo_flush_rtio(const struct device *dev)
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{
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struct adxl372_data *data = dev->data;
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uint8_t pow_reg = data->pwr_reg;
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const struct adxl372_dev_config *cfg = dev->config;
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uint8_t fifo_config;
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pow_reg &= ~ADXL372_POWER_CTL_MODE_MSK;
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pow_reg |= ADXL372_POWER_CTL_MODE(ADXL372_STANDBY);
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struct rtio_sqe *sqe = rtio_sqe_acquire(data->rtio_ctx);
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const uint8_t reg_addr_w[2] = {ADXL372_REG_WRITE(ADXL372_POWER_CTL), pow_reg};
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rtio_sqe_prep_tiny_write(sqe, data->iodev, RTIO_PRIO_NORM, reg_addr_w, 2, NULL);
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fifo_config = (ADXL372_FIFO_CTL_FORMAT_MODE(data->fifo_config.fifo_format) |
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ADXL372_FIFO_CTL_MODE_MODE(ADXL372_FIFO_BYPASSED) |
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ADXL372_FIFO_CTL_SAMPLES_MODE(data->fifo_config.fifo_samples));
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sqe = rtio_sqe_acquire(data->rtio_ctx);
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const uint8_t reg_addr_w2[2] = {ADXL372_REG_WRITE(ADXL372_FIFO_CTL), fifo_config};
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rtio_sqe_prep_tiny_write(sqe, data->iodev, RTIO_PRIO_NORM, reg_addr_w2, 2, NULL);
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fifo_config = (ADXL372_FIFO_CTL_FORMAT_MODE(data->fifo_config.fifo_format) |
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ADXL372_FIFO_CTL_MODE_MODE(data->fifo_config.fifo_mode) |
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ADXL372_FIFO_CTL_SAMPLES_MODE(data->fifo_config.fifo_samples));
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sqe = rtio_sqe_acquire(data->rtio_ctx);
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const uint8_t reg_addr_w3[2] = {ADXL372_REG_WRITE(ADXL372_FIFO_CTL), fifo_config};
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rtio_sqe_prep_tiny_write(sqe, data->iodev, RTIO_PRIO_NORM, reg_addr_w3, 2, NULL);
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pow_reg = data->pwr_reg;
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pow_reg &= ~ADXL372_POWER_CTL_MODE_MSK;
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pow_reg |= ADXL372_POWER_CTL_MODE(cfg->op_mode);
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sqe = rtio_sqe_acquire(data->rtio_ctx);
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struct rtio_sqe *complete_op = rtio_sqe_acquire(data->rtio_ctx);
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const uint8_t reg_addr_w4[2] = {ADXL372_REG_WRITE(ADXL372_POWER_CTL), pow_reg};
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rtio_sqe_prep_tiny_write(sqe, data->iodev, RTIO_PRIO_NORM, reg_addr_w4, 2, NULL);
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sqe->flags |= RTIO_SQE_CHAINED;
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rtio_sqe_prep_callback(complete_op, adxl372_irq_en_cb, (void *)dev, NULL);
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rtio_submit(data->rtio_ctx, 0);
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}
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void adxl372_submit_stream(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe)
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{
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const struct sensor_read_config *cfg =
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(const struct sensor_read_config *)iodev_sqe->sqe.iodev->data;
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struct adxl372_data *data = (struct adxl372_data *)dev->data;
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const struct adxl372_dev_config *cfg_372 = dev->config;
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uint8_t int_value = (uint8_t)~ADXL372_INT1_MAP_FIFO_FULL_MSK;
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uint8_t fifo_full_irq = 0;
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int rc = gpio_pin_interrupt_configure_dt(&cfg_372->interrupt, GPIO_INT_DISABLE);
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if (rc < 0) {
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return;
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}
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for (size_t i = 0; i < cfg->count; i++) {
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if ((cfg->triggers[i].trigger == SENSOR_TRIG_FIFO_WATERMARK) ||
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(cfg->triggers[i].trigger == SENSOR_TRIG_FIFO_FULL)) {
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int_value = ADXL372_INT1_MAP_FIFO_FULL_MSK;
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fifo_full_irq = 1;
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}
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}
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if (fifo_full_irq != data->fifo_full_irq) {
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data->fifo_full_irq = fifo_full_irq;
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rc = data->hw_tf->write_reg_mask(dev, ADXL372_INT1_MAP,
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ADXL372_INT1_MAP_FIFO_FULL_MSK, int_value);
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if (rc < 0) {
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return;
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}
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/* Flush the FIFO by disabling it. Save current mode for after the reset. */
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enum adxl372_fifo_mode current_fifo_mode = data->fifo_config.fifo_mode;
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adxl372_configure_fifo(dev, ADXL372_FIFO_BYPASSED, data->fifo_config.fifo_format,
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data->fifo_config.fifo_samples);
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if (current_fifo_mode == ADXL372_FIFO_BYPASSED) {
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current_fifo_mode = ADXL372_FIFO_STREAMED;
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}
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adxl372_configure_fifo(dev, current_fifo_mode, data->fifo_config.fifo_format,
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data->fifo_config.fifo_samples);
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adxl372_set_op_mode(dev, cfg_372->op_mode);
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}
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rc = gpio_pin_interrupt_configure_dt(&cfg_372->interrupt, GPIO_INT_EDGE_TO_ACTIVE);
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if (rc < 0) {
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return;
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}
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data->sqe = iodev_sqe;
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}
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static void adxl372_fifo_read_cb(struct rtio *rtio_ctx, const struct rtio_sqe *sqe, void *arg)
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{
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const struct device *dev = (const struct device *)arg;
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const struct adxl372_dev_config *cfg = (const struct adxl372_dev_config *)dev->config;
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struct rtio_iodev_sqe *iodev_sqe = sqe->userdata;
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rtio_iodev_sqe_ok(iodev_sqe, 0);
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gpio_pin_interrupt_configure_dt(&cfg->interrupt, GPIO_INT_EDGE_TO_ACTIVE);
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}
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size_t adxl372_get_packet_size(const struct adxl372_dev_config *cfg)
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{
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/* If one sample contains XYZ values. */
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size_t packet_size;
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switch (cfg->fifo_config.fifo_format) {
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case ADXL372_X_FIFO:
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case ADXL372_Y_FIFO:
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case ADXL372_Z_FIFO:
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packet_size = 2;
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break;
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case ADXL372_XY_FIFO:
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case ADXL372_XZ_FIFO:
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case ADXL372_YZ_FIFO:
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packet_size = 4;
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break;
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default:
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packet_size = 6;
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break;
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}
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return packet_size;
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}
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static void adxl372_process_fifo_samples_cb(struct rtio *r, const struct rtio_sqe *sqr, void *arg)
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{
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const struct device *dev = (const struct device *)arg;
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struct adxl372_data *data = (struct adxl372_data *)dev->data;
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const struct adxl372_dev_config *cfg = (const struct adxl372_dev_config *)dev->config;
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struct rtio_iodev_sqe *current_sqe = data->sqe;
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uint16_t fifo_samples = (((data->fifo_ent[0] & 0x3) << 8) | data->fifo_ent[1]);
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size_t sample_set_size = adxl372_get_packet_size(cfg);
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/* At least one sample set must remain in FIFO to encure that data
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* is not overwritten and stored out of order.
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*/
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if (fifo_samples > sample_set_size / 2) {
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fifo_samples -= sample_set_size / 2;
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} else {
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LOG_ERR("fifo sample count error %d\n", fifo_samples);
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gpio_pin_interrupt_configure_dt(&cfg->interrupt, GPIO_INT_EDGE_TO_ACTIVE);
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return;
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}
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uint16_t fifo_bytes = fifo_samples * 2 /*sample size*/;
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data->sqe = NULL;
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/* Not inherently an underrun/overrun as we may have a buffer to fill next time */
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if (current_sqe == NULL) {
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LOG_ERR("No pending SQE");
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gpio_pin_interrupt_configure_dt(&cfg->interrupt, GPIO_INT_EDGE_TO_ACTIVE);
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return;
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}
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const size_t min_read_size = sizeof(struct adxl372_fifo_data) + sample_set_size;
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const size_t ideal_read_size = sizeof(struct adxl372_fifo_data) + fifo_bytes;
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uint8_t *buf;
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uint32_t buf_len;
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if (rtio_sqe_rx_buf(current_sqe, min_read_size, ideal_read_size, &buf, &buf_len) != 0) {
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LOG_ERR("Failed to get buffer");
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rtio_iodev_sqe_err(current_sqe, -ENOMEM);
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gpio_pin_interrupt_configure_dt(&cfg->interrupt, GPIO_INT_EDGE_TO_ACTIVE);
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return;
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}
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LOG_DBG("Requesting buffer [%u, %u] got %u", (unsigned int)min_read_size,
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(unsigned int)ideal_read_size, buf_len);
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/* Read FIFO and call back to rtio with rtio_sqe completion */
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struct adxl372_fifo_data *hdr = (struct adxl372_fifo_data *)buf;
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hdr->is_fifo = 1;
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hdr->timestamp = data->timestamp;
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hdr->int_status = data->status1;
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hdr->accel_odr = cfg->odr;
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hdr->sample_set_size = sample_set_size;
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if ((cfg->fifo_config.fifo_format == ADXL372_X_FIFO) ||
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(cfg->fifo_config.fifo_format == ADXL372_XY_FIFO) ||
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(cfg->fifo_config.fifo_format == ADXL372_XZ_FIFO) ||
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(cfg->fifo_config.fifo_format == ADXL372_XYZ_FIFO)) {
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hdr->has_x = 1;
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}
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if ((cfg->fifo_config.fifo_format == ADXL372_Y_FIFO) ||
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(cfg->fifo_config.fifo_format == ADXL372_XY_FIFO) ||
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(cfg->fifo_config.fifo_format == ADXL372_YZ_FIFO) ||
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(cfg->fifo_config.fifo_format == ADXL372_XYZ_FIFO)) {
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hdr->has_y = 1;
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}
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if ((cfg->fifo_config.fifo_format == ADXL372_Z_FIFO) ||
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(cfg->fifo_config.fifo_format == ADXL372_XZ_FIFO) ||
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(cfg->fifo_config.fifo_format == ADXL372_YZ_FIFO) ||
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(cfg->fifo_config.fifo_format == ADXL372_XYZ_FIFO)) {
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hdr->has_z = 1;
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}
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uint32_t buf_avail = buf_len;
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buf_avail -= sizeof(*hdr);
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uint32_t read_len = MIN(fifo_bytes, buf_avail);
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uint32_t pkts = read_len / sample_set_size;
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read_len = pkts * sample_set_size;
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((struct adxl372_fifo_data *)buf)->fifo_byte_count = read_len;
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__ASSERT_NO_MSG(read_len % pkt_size == 0);
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uint8_t *read_buf = buf + sizeof(*hdr);
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/* Flush completions */
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struct rtio_cqe *cqe;
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int res = 0;
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do {
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cqe = rtio_cqe_consume(data->rtio_ctx);
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if (cqe != NULL) {
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if ((cqe->result < 0 && res == 0)) {
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LOG_ERR("Bus error: %d", cqe->result);
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res = cqe->result;
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}
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rtio_cqe_release(data->rtio_ctx, cqe);
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}
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} while (cqe != NULL);
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/* Bail/cancel attempt to read sensor on any error */
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if (res != 0) {
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rtio_iodev_sqe_err(current_sqe, res);
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return;
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}
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/* Setup new rtio chain to read the fifo data and report then check the
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* result
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*/
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struct rtio_sqe *write_fifo_addr = rtio_sqe_acquire(data->rtio_ctx);
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struct rtio_sqe *read_fifo_data = rtio_sqe_acquire(data->rtio_ctx);
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struct rtio_sqe *complete_op = rtio_sqe_acquire(data->rtio_ctx);
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const uint8_t reg_addr = ADXL372_REG_READ(ADXL372_FIFO_DATA);
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rtio_sqe_prep_tiny_write(write_fifo_addr, data->iodev, RTIO_PRIO_NORM, ®_addr, 1, NULL);
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write_fifo_addr->flags = RTIO_SQE_TRANSACTION;
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rtio_sqe_prep_read(read_fifo_data, data->iodev, RTIO_PRIO_NORM, read_buf, read_len,
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current_sqe);
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read_fifo_data->flags = RTIO_SQE_CHAINED;
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rtio_sqe_prep_callback(complete_op, adxl372_fifo_read_cb, (void *)dev, current_sqe);
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rtio_submit(data->rtio_ctx, 0);
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}
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static void adxl372_process_status1_cb(struct rtio *r, const struct rtio_sqe *sqr, void *arg)
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{
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const struct device *dev = (const struct device *)arg;
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struct adxl372_data *data = (struct adxl372_data *)dev->data;
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const struct adxl372_dev_config *cfg = (const struct adxl372_dev_config *)dev->config;
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struct rtio_iodev_sqe *current_sqe = data->sqe;
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struct sensor_read_config *read_config;
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uint8_t status1 = data->status1;
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if (data->sqe == NULL) {
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return;
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}
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read_config = (struct sensor_read_config *)data->sqe->sqe.iodev->data;
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if (read_config == NULL) {
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return;
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}
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if (read_config->is_streaming == false) {
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return;
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}
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gpio_pin_interrupt_configure_dt(&cfg->interrupt, GPIO_INT_DISABLE);
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struct sensor_stream_trigger *fifo_wmark_cfg = NULL;
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struct sensor_stream_trigger *fifo_full_cfg = NULL;
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for (int i = 0; i < read_config->count; ++i) {
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if (read_config->triggers[i].trigger == SENSOR_TRIG_FIFO_WATERMARK) {
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fifo_wmark_cfg = &read_config->triggers[i];
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continue;
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}
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if (read_config->triggers[i].trigger == SENSOR_TRIG_FIFO_FULL) {
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fifo_full_cfg = &read_config->triggers[i];
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continue;
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}
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}
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bool fifo_full_irq = false;
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if ((fifo_wmark_cfg != NULL) && (fifo_full_cfg != NULL) &&
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FIELD_GET(ADXL372_INT1_MAP_FIFO_FULL_MSK, status1)) {
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fifo_full_irq = true;
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}
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if (!fifo_full_irq) {
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gpio_pin_interrupt_configure_dt(&cfg->interrupt, GPIO_INT_EDGE_TO_ACTIVE);
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return;
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}
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struct rtio_cqe *cqe;
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int res = 0;
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do {
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cqe = rtio_cqe_consume(data->rtio_ctx);
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if (cqe != NULL) {
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if ((cqe->result < 0) && (res == 0)) {
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LOG_ERR("Bus error: %d", cqe->result);
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res = cqe->result;
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}
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rtio_cqe_release(data->rtio_ctx, cqe);
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}
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} while (cqe != NULL);
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/* Bail/cancel attempt to read sensor on any error */
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if (res != 0) {
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rtio_iodev_sqe_err(current_sqe, res);
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return;
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}
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enum sensor_stream_data_opt data_opt;
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if ((fifo_wmark_cfg != NULL) && (fifo_full_cfg == NULL)) {
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data_opt = fifo_wmark_cfg->opt;
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} else if ((fifo_wmark_cfg == NULL) && (fifo_full_cfg != NULL)) {
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data_opt = fifo_full_cfg->opt;
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} else {
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data_opt = MIN(fifo_wmark_cfg->opt, fifo_full_cfg->opt);
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}
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if (data_opt == SENSOR_STREAM_DATA_NOP || data_opt == SENSOR_STREAM_DATA_DROP) {
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uint8_t *buf;
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uint32_t buf_len;
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/* Clear streaming_sqe since we're done with the call */
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data->sqe = NULL;
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if (rtio_sqe_rx_buf(current_sqe, sizeof(struct adxl372_fifo_data),
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sizeof(struct adxl372_fifo_data), &buf, &buf_len) != 0) {
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rtio_iodev_sqe_err(current_sqe, -ENOMEM);
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gpio_pin_interrupt_configure_dt(&cfg->interrupt, GPIO_INT_EDGE_TO_ACTIVE);
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return;
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}
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struct adxl372_fifo_data *rx_data = (struct adxl372_fifo_data *)buf;
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memset(buf, 0, buf_len);
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rx_data->is_fifo = 1;
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rx_data->timestamp = data->timestamp;
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rx_data->int_status = status1;
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rx_data->fifo_byte_count = 0;
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rtio_iodev_sqe_ok(current_sqe, 0);
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if (data_opt == SENSOR_STREAM_DATA_DROP) {
|
||||
/* Flush the FIFO by disabling it. Save current mode for after the reset. */
|
||||
adxl372_fifo_flush_rtio(dev);
|
||||
return;
|
||||
}
|
||||
|
||||
gpio_pin_interrupt_configure_dt(&cfg->interrupt, GPIO_INT_EDGE_TO_ACTIVE);
|
||||
return;
|
||||
}
|
||||
|
||||
struct rtio_sqe *write_fifo_addr = rtio_sqe_acquire(data->rtio_ctx);
|
||||
struct rtio_sqe *read_fifo_data = rtio_sqe_acquire(data->rtio_ctx);
|
||||
struct rtio_sqe *complete_op = rtio_sqe_acquire(data->rtio_ctx);
|
||||
const uint8_t reg_addr = ADXL372_REG_READ(ADXL372_FIFO_ENTRIES_2);
|
||||
|
||||
rtio_sqe_prep_tiny_write(write_fifo_addr, data->iodev, RTIO_PRIO_NORM, ®_addr, 1, NULL);
|
||||
write_fifo_addr->flags = RTIO_SQE_TRANSACTION;
|
||||
rtio_sqe_prep_read(read_fifo_data, data->iodev, RTIO_PRIO_NORM, data->fifo_ent, 2,
|
||||
current_sqe);
|
||||
read_fifo_data->flags = RTIO_SQE_CHAINED;
|
||||
rtio_sqe_prep_callback(complete_op, adxl372_process_fifo_samples_cb, (void *)dev,
|
||||
current_sqe);
|
||||
|
||||
rtio_submit(data->rtio_ctx, 0);
|
||||
}
|
||||
|
||||
void adxl372_stream_irq_handler(const struct device *dev)
|
||||
{
|
||||
struct adxl372_data *data = (struct adxl372_data *)dev->data;
|
||||
|
||||
if (data->sqe == NULL) {
|
||||
return;
|
||||
}
|
||||
|
||||
data->timestamp = k_ticks_to_ns_floor64(k_uptime_ticks());
|
||||
|
||||
struct rtio_sqe *write_status_addr = rtio_sqe_acquire(data->rtio_ctx);
|
||||
struct rtio_sqe *read_status_reg = rtio_sqe_acquire(data->rtio_ctx);
|
||||
struct rtio_sqe *check_status_reg = rtio_sqe_acquire(data->rtio_ctx);
|
||||
uint8_t reg = ADXL372_REG_READ(ADXL372_STATUS_1);
|
||||
|
||||
rtio_sqe_prep_tiny_write(write_status_addr, data->iodev, RTIO_PRIO_NORM, ®, 1, NULL);
|
||||
write_status_addr->flags = RTIO_SQE_TRANSACTION;
|
||||
rtio_sqe_prep_read(read_status_reg, data->iodev, RTIO_PRIO_NORM, &data->status1, 1, NULL);
|
||||
read_status_reg->flags = RTIO_SQE_CHAINED;
|
||||
rtio_sqe_prep_callback(check_status_reg, adxl372_process_status1_cb, (void *)dev, NULL);
|
||||
rtio_submit(data->rtio_ctx, 0);
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue