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drivers: flash: flash_mcux_flexspi: add support for W25Q512NW-IQ/IN

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Add support for the W25Q512NW-IQ/IN with the FLEXSPI, using a custom
LUT table.

Fixes #80592

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse 2024-10-16 16:20:51 -05:00 • committed by Mahesh Mahadevan
commit cfb7322107
1 changed files with 38 additions and 0 deletions
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38
drivers/flash/flash_mcux_flexspi_nor.c
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@ -1008,6 +1008,44 @@ static int flash_flexspi_nor_check_jedec(struct flash_flexspi_nor_data *data,
/* Device uses bit 1 of status reg 2 for QE */
return flash_flexspi_nor_quad_enable(data, flexspi_lut,
JESD216_DW15_QER_VAL_S2B1v5);
case 0x60ef:
if ((vendor_id & 0xFFFFFF) != 0x2060ef) {
/*
* This is not the correct flash chip, and will not
* support the LUT table. Return here
*/
return -ENOTSUP;
}
/* W25Q512NW-IQ/IN flash, use 4 byte read/write */
flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_4READ_4B,
kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 32);
/* Flash needs 8 dummy cycles (at 133MHz) */
flexspi_lut[READ][1] = FLEXSPI_LUT_SEQ(
kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 8,
kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04);
/* Only 1S-1S-4S page program supported */
flexspi_lut[PAGE_PROGRAM][0] = FLEXSPI_LUT_SEQ(
kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP_1_1_4_4B,
kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
flexspi_lut[PAGE_PROGRAM][1] = FLEXSPI_LUT_SEQ(
kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x4,
kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
/* Update ERASE commands for 4 byte mode */
flexspi_lut[ERASE_SECTOR][0] = FLEXSPI_LUT_SEQ(
kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE_4B,
kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
flexspi_lut[ERASE_BLOCK][0] = FLEXSPI_LUT_SEQ(
kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xDC,
kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32),
/* Read instruction used for polling is 0x05 */
data->legacy_poll = true;
flexspi_lut[READ_STATUS_REG][0] = FLEXSPI_LUT_SEQ(
kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01);
/* Device uses bit 1 of status reg 2 for QE */
return flash_flexspi_nor_quad_enable(data, flexspi_lut,
JESD216_DW15_QER_VAL_S2B1v5);
case 0x25C2:
/* MX25 flash, use 4 byte read/write */
flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(