driver: timer: Add timer driver initial version of RTS5912.
Add timer driver for Realtek RTS5912. Signed-off-by: Lin Yu-Cheng <lin_yu_cheng@realtek.com>
This commit is contained in:
Lin Yu-Cheng
Benjamin Cabé
parent
471cc3512d
commit
cfb2074a5e
8 changed files with 363 additions and 0 deletions
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@ -33,6 +33,7 @@ zephyr_library_sources_ifdef(CONFIG_NRF_RTC_TIMER nrf_rtc_timer.c)
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zephyr_library_sources_ifdef(CONFIG_RCAR_CMT_TIMER rcar_cmt_timer.c)
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zephyr_library_sources_ifdef(CONFIG_RISCV_MACHINE_TIMER riscv_machine_timer.c)
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zephyr_library_sources_ifdef(CONFIG_RV32M1_LPTMR_TIMER rv32m1_lptmr_timer.c)
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zephyr_library_sources_ifdef(CONFIG_REALTEK_RTS5912_RTMR realtek_rts5912_rtmr.c)
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zephyr_library_sources_ifdef(CONFIG_SAM0_RTC_TIMER sam0_rtc_timer.c)
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zephyr_library_sources_ifdef(CONFIG_SILABS_SLEEPTIMER_TIMER silabs_sleeptimer_timer.c)
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zephyr_library_sources_ifdef(CONFIG_STM32_LPTIM_TIMER stm32_lptim_timer.c)
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@ -91,6 +91,7 @@ source "drivers/timer/Kconfig.nrf_xrtc"
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source "drivers/timer/Kconfig.rcar_cmt"
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source "drivers/timer/Kconfig.riscv_machine"
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source "drivers/timer/Kconfig.rv32m1_lptmr"
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source "drivers/timer/Kconfig.realtek_rts5912_rtmr"
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source "drivers/timer/Kconfig.sam0_rtc"
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source "drivers/timer/Kconfig.silabs"
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source "drivers/timer/Kconfig.smartbond"
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13
drivers/timer/Kconfig.realtek_rts5912_rtmr
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13
drivers/timer/Kconfig.realtek_rts5912_rtmr
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@ -0,0 +1,13 @@
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# SPDX-License-Identifier: Apache-2.0
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#
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# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7
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#
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config REALTEK_RTS5912_RTMR
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bool "Realtek RTS5912 RTOS Timer"
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default y if DT_HAS_REALTEK_RTS5912_RTMR_ENABLED
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select TICKLESS_CAPABLE
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select SYSTEM_TIMER_HAS_DISABLE_SUPPORT
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help
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This module implements a kernel device driver for the Realtek
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RTS5912 series RTOS timer.
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251
drivers/timer/realtek_rts5912_rtmr.c
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251
drivers/timer/realtek_rts5912_rtmr.c
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@ -0,0 +1,251 @@
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/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7
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* Author: Lin Yu-Cheng <lin_yu_cheng@realtek.com>
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*/
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#define DT_DRV_COMPAT realtek_rts5912_rtmr
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#include <stdint.h>
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#include <zephyr/init.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/sys_clock.h>
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#include <zephyr/irq.h>
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#include <zephyr/spinlock.h>
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#include <zephyr/drivers/timer/system_timer.h>
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#include <reg/reg_rtmr.h>
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#include <reg/reg_system.h>
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#define RTS5912_SCCON_REG_BASE ((SYSTEM_Type *)(DT_REG_ADDR(DT_NODELABEL(sccon))))
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#define CYCLES_PER_TICK (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
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BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
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"Realtek RTOS timer is not supported multiple instances");
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#define RTMR_REG ((RTOSTMR_Type *)DT_INST_REG_ADDR(0))
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#define SLWTMR_REG \
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((RTOSTMR_Type *)(DT_REG_ADDR(DT_COMPAT_GET_ANY_STATUS_OKAY(realtek_rts5912_slwtimer))))
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#define SSCON_REG ((SYSTEM_Type *)(DT_REG_ADDR(DT_NODELABEL(sccon))))
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#define RTMR_COUNTER_MAX 0x0ffffffful
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#define RTMR_COUNTER_MSK 0x0ffffffful
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#define RTMR_TIMER_STOPPED 0xf0000000ul
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#define MAX_TICKS ((k_ticks_t)(RTMR_COUNTER_MAX / CYCLES_PER_TICK) - 1)
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#define RTMR_ADJUST_LIMIT 2
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#define RTMR_ADJUST_CYCLES 1
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static struct k_spinlock lock;
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static uint32_t accumulated_cycles;
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static uint32_t previous_cnt; /* Record the counter set into RTMR */
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static uint32_t last_announcement; /* Record the last tick announced to system */
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static void rtmr_restart(uint32_t counter)
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{
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RTMR_REG->CTRL = 0ul;
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RTMR_REG->LDCNT = counter;
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RTMR_REG->CTRL = RTOSTMR_CTRL_INTEN_Msk | RTOSTMR_CTRL_EN_Msk;
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}
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static uint32_t rtmr_get_counter(void)
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{
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uint32_t counter = RTMR_REG->CNT;
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if ((counter == 0) && (RTMR_REG->CTRL & RTOSTMR_CTRL_EN_Msk)) {
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counter = previous_cnt;
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}
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return counter;
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}
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static void rtmr_isr(const void *arg)
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{
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ARG_UNUSED(arg);
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uint32_t cycles;
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int32_t ticks;
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k_spinlock_key_t key = k_spin_lock(&lock);
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rtmr_restart(RTMR_COUNTER_MAX * CYCLES_PER_TICK);
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cycles = previous_cnt;
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previous_cnt = RTMR_COUNTER_MAX * CYCLES_PER_TICK;
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accumulated_cycles += cycles;
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if (accumulated_cycles > RTMR_COUNTER_MSK) {
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accumulated_cycles &= RTMR_COUNTER_MSK;
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}
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ticks = accumulated_cycles - last_announcement;
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ticks &= RTMR_COUNTER_MSK;
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ticks /= CYCLES_PER_TICK;
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last_announcement = accumulated_cycles;
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k_spin_unlock(&lock, key);
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sys_clock_announce(ticks);
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}
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void sys_clock_set_timeout(int32_t ticks, bool idle)
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{
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ARG_UNUSED(idle);
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uint32_t cur_cnt, temp;
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int full_ticks;
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uint32_t full_cycles;
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uint32_t partial_cycles;
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if (idle && (ticks == K_TICKS_FOREVER)) {
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RTMR_REG->CTRL = 0U;
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previous_cnt = RTMR_TIMER_STOPPED;
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return;
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}
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if (ticks < 1) {
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full_ticks = 0;
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} else if ((ticks == K_TICKS_FOREVER) || (ticks > MAX_TICKS)) {
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full_ticks = MAX_TICKS - 1;
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} else {
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full_ticks = ticks - 1;
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}
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full_cycles = full_ticks * CYCLES_PER_TICK;
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k_spinlock_key_t key = k_spin_lock(&lock);
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cur_cnt = rtmr_get_counter();
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RTMR_REG->CTRL = 0U;
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temp = accumulated_cycles;
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temp += previous_cnt - cur_cnt;
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temp &= RTMR_COUNTER_MSK;
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accumulated_cycles = temp;
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partial_cycles = CYCLES_PER_TICK - (accumulated_cycles % CYCLES_PER_TICK);
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previous_cnt = full_cycles + partial_cycles;
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temp = previous_cnt;
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if (temp > RTMR_ADJUST_LIMIT) {
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temp -= RTMR_ADJUST_CYCLES;
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}
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rtmr_restart(temp);
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k_spin_unlock(&lock, key);
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}
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uint32_t sys_clock_elapsed(void)
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{
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uint32_t cur_cnt;
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uint32_t ticks;
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int32_t elapsed;
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k_spinlock_key_t key = k_spin_lock(&lock);
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cur_cnt = rtmr_get_counter();
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elapsed = (int32_t)accumulated_cycles - (int32_t)last_announcement;
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if (elapsed < 0) {
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elapsed = -1 * elapsed;
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}
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ticks = (uint32_t)elapsed;
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ticks += previous_cnt - cur_cnt;
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ticks /= CYCLES_PER_TICK;
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ticks &= RTMR_COUNTER_MSK;
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k_spin_unlock(&lock, key);
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return ticks;
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}
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void sys_clock_idle_exit(void)
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{
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if (previous_cnt == RTMR_TIMER_STOPPED) {
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previous_cnt = CYCLES_PER_TICK;
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rtmr_restart(previous_cnt);
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}
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}
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void sys_clock_disable(void)
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{
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/* Disable RTMR. */
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RTMR_REG->CTRL = 0ul;
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}
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uint32_t sys_clock_cycle_get_32(void)
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{
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uint32_t ret;
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uint32_t cur_cnt;
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k_spinlock_key_t key = k_spin_lock(&lock);
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cur_cnt = rtmr_get_counter();
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ret = (accumulated_cycles + (previous_cnt - cur_cnt)) & RTMR_COUNTER_MSK;
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k_spin_unlock(&lock, key);
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return ret;
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}
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#ifdef CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT
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void arch_busy_wait(uint32_t n_usec)
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{
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if (n_usec == 0) {
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return;
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}
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uint32_t start = SLWTMR_REG->CNT;
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for (;;) {
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uint32_t curr = SLWTMR_REG->CNT;
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if ((start - curr) >= n_usec) {
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break;
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}
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}
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}
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#endif
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static int sys_clock_driver_init(void)
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{
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/* Enable RTMR clock power */
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SYSTEM_Type *sys_reg = RTS5912_SCCON_REG_BASE;
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sys_reg->PERICLKPWR1 |= SYSTEM_PERICLKPWR1_RTMRCLKPWR_Msk;
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/* Enable RTMR interrupt. */
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IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), rtmr_isr, 0, 0);
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irq_enable(DT_INST_IRQN(0));
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/* Trigger RTMR and wait it start to counting */
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previous_cnt = RTMR_COUNTER_MAX;
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rtmr_restart(previous_cnt);
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while (RTMR_REG->CNT == 0) {
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};
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#ifdef CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT
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/* Enable SLWTMR0 clock power */
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SSCON_REG->PERICLKPWR1 |= BIT(SYSTEM_PERICLKPWR1_SLWTMR0CLKPWR_Pos);
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/* Enable SLWTMR0 */
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SLWTMR_REG->LDCNT = UINT32_MAX;
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SLWTMR_REG->CTRL = RTOSTMR_CTRL_MDSEL_Msk | RTOSTMR_CTRL_EN_Msk;
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#endif
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return 0;
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}
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SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2, CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
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@ -73,6 +73,25 @@
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clock-names = "rc25m", "pll";
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};
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slwtmr0: slwtmr0@4000c200 {
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compatible = "realtek,rts5912-slwtimer";
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reg = <0x4000c200 0x10>;
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interrupts = <202 0>;
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clocks = <&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_SLWTMR0_CLKPWR>;
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clock-names = "slwtmr";
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max-value = <0xFFFFFFFF>;
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clock-frequency = <1000000>;
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prescaler = <0>;
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status = "okay";
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};
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rtmr: rtmr@4000c500 {
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compatible = "realtek,rts5912-rtmr";
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reg = <0x4000c500 0x10>;
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interrupts = <204 0>;
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status = "okay";
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};
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pinctrl: pin-controller@40090000 {
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compatible = "realtek,rts5912-pinctrl";
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#address-cells = <1>;
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17
dts/bindings/timer/realtek,rts5912-rtmr.yaml
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17
dts/bindings/timer/realtek,rts5912-rtmr.yaml
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@ -0,0 +1,17 @@
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# SPDX-License-Identifier: Apache-2.0
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#
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# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7
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#
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description: RTOS Timer on Realtek RTS5912 EC
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compatible: "realtek,rts5912-rtmr"
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include: base.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true
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30
dts/bindings/timer/realtek,rts5912-slwtimer.yaml
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dts/bindings/timer/realtek,rts5912-slwtimer.yaml
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@ -0,0 +1,30 @@
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# SPDX-License-Identifier: Apache-2.0
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#
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# Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7
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#
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description: Realtek RTS5912 32-bit slow timer
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compatible: "realtek,rts5912-slwtimer"
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include: rtc.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true
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max-value:
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type: int
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required: true
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description: Maximum counter value the instance can handle
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clock-frequency:
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required: true
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prescaler:
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type: int
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required: true
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description: Timer frequency equals clock-frequency divided by the prescaler value
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31
soc/realtek/ec/rts5912/reg/reg_rtmr.h
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31
soc/realtek/ec/rts5912/reg/reg_rtmr.h
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@ -0,0 +1,31 @@
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/*
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* Copyright (c) 2023 Realtek, SIBG-SD7
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_REALTEK_RTS5912_REG_RTMR_H
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#define ZEPHYR_SOC_REALTEK_RTS5912_REG_RTMR_H
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/*
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* @brief RTOS Timer Controller (RTMR)
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*/
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typedef struct {
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volatile uint32_t LDCNT;
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volatile uint32_t CNT;
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volatile uint32_t CTRL;
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volatile uint32_t INTSTS;
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} RTOSTMR_Type;
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/* CTRL */
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#define RTOSTMR_CTRL_EN_Pos (0UL)
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#define RTOSTMR_CTRL_EN_Msk BIT(RTOSTMR_CTRL_EN_Pos)
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#define RTOSTMR_CTRL_MDSEL_Pos (1UL)
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#define RTOSTMR_CTRL_MDSEL_Msk BIT(RTOSTMR_CTRL_MDSEL_Pos)
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#define RTOSTMR_CTRL_INTEN_Pos (2UL)
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#define RTOSTMR_CTRL_INTEN_Msk BIT(RTOSTMR_CTRL_INTEN_Pos)
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/* INTSTS */
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#define RTOSTMR_INTSTS_STS_Pos (0UL)
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#define RTOSTMR_INTSTS_STS_Msk BIT(RTOSTMR_INTSTS_STS_Pos)
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#endif /* ZEPHYR_SOC_REALTEK_RTS5912_REG_RTMR_H */
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