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dts: arm: silabs: change siwg917 board ram start address

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The first 1 KB is reserved for the NWP (Network Coprocessor). This
change also resolves the null pointer error issue, as a .data or a
_ramfunc might get the address 0x0.

Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
This commit is contained in:
Martin Hoff 2025-05-13 16:59:12 +02:00 • committed by Benjamin Cabé
commit cfb0a80df4
2 changed files with 22 additions and 12 deletions
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21
dts/arm/silabs/siwg917.dtsi
View file

@ -27,19 +27,28 @@
}; };
}; };
sram0: memory@0 { /* The first 1KB of SRAM is reserved for the NWP (Network Processor).
* It also protects against null pointer exceptions.
*/
nwp_reserved: memory@0 {
compatible = "zephyr,memory-region","mmio-sram";
reg = <0x00000000 DT_SIZE_K(1)>;
zephyr,memory-region = "NWP_RESERVED_RAM";
};
sram0: memory@400 {
compatible = "mmio-sram"; compatible = "mmio-sram";
/* siwx91x has 672kB of SRAM shared between the Cortex-M4 /* siwx91x has 671kB of SRAM shared between the Cortex-M4
* (Zephyr) and the NWP (Network Processor). 3 memory * (Zephyr) and the NWP (Network Processor). 3 memory
* configurations are * configurations are
* possible: * possible:
* - 196kB * - 195kB
* - 256kB * - 255kB
* - 320kB * - 319kB
* Less memory is allocated to Zephyr, more memory is allocated * Less memory is allocated to Zephyr, more memory is allocated
* to NWP, better are the WiFi and BLE performances. * to NWP, better are the WiFi and BLE performances.
*/ */
reg = <0x00000000 DT_SIZE_K(256)>; reg = <0x00000400 DT_SIZE_K(255)>;
}; };
sram_dma1: memory-dma@24061c00 { sram_dma1: memory-dma@24061c00 {

13
soc/silabs/silabs_siwx91x/siwg917/nwp.c
View file

@ -22,9 +22,9 @@
LOG_MODULE_REGISTER(siwx91x_nwp); LOG_MODULE_REGISTER(siwx91x_nwp);
BUILD_ASSERT(DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(196) || BUILD_ASSERT(DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(195) ||
DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(256) || DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(255) ||
DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(320)); DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(319));
int siwg91x_get_nwp_config(int wifi_oper_mode, sl_wifi_device_configuration_t *get_config) int siwg91x_get_nwp_config(int wifi_oper_mode, sl_wifi_device_configuration_t *get_config)
{ {
@ -49,11 +49,12 @@ int siwg91x_get_nwp_config(int wifi_oper_mode, sl_wifi_device_configuration_t *g
__ASSERT(get_config, "get_config cannot be NULL"); __ASSERT(get_config, "get_config cannot be NULL");
if (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(196)) { /* The size does not match exactly because 1 KB is reserved at the start of the RAM */
if (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(195)) {
boot_config->ext_custom_feature_bit_map |= SL_SI91X_EXT_FEAT_480K_M4SS_192K; boot_config->ext_custom_feature_bit_map |= SL_SI91X_EXT_FEAT_480K_M4SS_192K;
} else if (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(256)) { } else if (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(255)) {
boot_config->ext_custom_feature_bit_map |= SL_SI91X_EXT_FEAT_416K_M4SS_256K; boot_config->ext_custom_feature_bit_map |= SL_SI91X_EXT_FEAT_416K_M4SS_256K;
} else if (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(320)) { } else if (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(319)) {
boot_config->ext_custom_feature_bit_map |= SL_SI91X_EXT_FEAT_352K_M4SS_320K; boot_config->ext_custom_feature_bit_map |= SL_SI91X_EXT_FEAT_352K_M4SS_320K;
} else { } else {
k_panic(); k_panic();