soc: nxp_imx: mimxrt1064_evk: Enable ethernet support

The i.MX RT1064 evk has one ethernet (10/100M) connector via KSZ8081RNB
phy. Enable related dts nodes and config flags

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>

boards/arm/mimxrt1064_evk/Kconfig.defconfig

@@ -27,4 +27,14 @@ config UART_MCUX_LPUART_1
 
 endif # UART_MCUX_LPUART
 
+if NETWORKING
+
+config NET_L2_ETHERNET
+	def_bool y
+
+config ETH_MCUX_0
+	def_bool y if NET_L2_ETHERNET
+
+endif # NETWORKING
+
 endif # BOARD_MIMXRT1064_EVK

boards/arm/mimxrt1064_evk/doc/index.rst

@@ -99,6 +99,8 @@ features:
 | UART      | on-chip    | serial port-polling;                |
 |           |            | serial port-interrupt               |
 +-----------+------------+-------------------------------------+
+| ENET      | on-chip    | ethernet                            |
++-----------+------------+-------------------------------------+
 
 The default configuration can be found in the defconfig file:
 ``boards/arm/mimxrt1064_evk/mimxrt1064_evk_defconfig``
@@ -113,7 +115,10 @@ The MIMXRT1064 SoC has four pairs of pinmux/gpio controllers.
 +---------------+-----------------+---------------------------+
 | Name          | Function        | Usage                     |
 +===============+=================+===========================+
-| GPIO_AD_B0_09 | GPIO            | LED                       |
++---------------+-----------------+---------------------------+
+| GPIO_AD_B0_09 | GPIO/ENET_RST   | LED/Ethernet              |
++---------------+-----------------+---------------------------+
+| GPIO_AD_B0_10 | GPIO/ENET_INT   | GPIO/Ethernet             |
 +---------------+-----------------+---------------------------+
 | GPIO_AD_B0_12 | LPUART1_TX      | UART Console              |
 +---------------+-----------------+---------------------------+
@@ -121,6 +126,30 @@ The MIMXRT1064 SoC has four pairs of pinmux/gpio controllers.
 +---------------+-----------------+---------------------------+
 | WAKEUP        | GPIO            | SW0                       |
 +---------------+-----------------+---------------------------+
+| GPIO_B1_04    | ENET_RX_DATA00  | Ethernet                  |
++---------------+-----------------+---------------------------+
+| GPIO_B1_05    | ENET_RX_DATA01  | Ethernet                  |
++---------------+-----------------+---------------------------+
+| GPIO_B1_06    | ENET_RX_EN      | Ethernet                  |
++---------------+-----------------+---------------------------+
+| GPIO_B1_07    | ENET_TX_DATA00  | Ethernet                  |
++---------------+-----------------+---------------------------+
+| GPIO_B1_08    | ENET_TX_DATA01  | Ethernet                  |
++---------------+-----------------+---------------------------+
+| GPIO_B1_09    | ENET_TX_EN      | Ethernet                  |
++---------------+-----------------+---------------------------+
+| GPIO_B1_10    | ENET_REF_CLK    | Ethernet                  |
++---------------+-----------------+---------------------------+
+| GPIO_B1_11    | ENET_RX_ER      | Ethernet                  |
++---------------+-----------------+---------------------------+
+| GPIO_EMC_40   | ENET_MDC        | Ethernet                  |
++---------------+-----------------+---------------------------+
+| GPIO_EMC_41   | ENET_MDIO       | Ethernet                  |
++---------------+-----------------+---------------------------+
+| GPIO_AD_B0_09 | ENET_RST        | Ethernet                  |
++---------------+-----------------+---------------------------+
+| GPIO_AD_B0_10 | ENET_INT        | Ethernet                  |
++---------------+-----------------+---------------------------+
 
 System Clock
 ============

boards/arm/mimxrt1064_evk/mimxrt1064_evk.dts

@@ -21,6 +21,7 @@
 		uart-1 = &uart1;
 		led0 = &green_led;
 		sw0 = &user_button;
+		eth = ð
 	};
 
 	chosen {
@@ -66,3 +67,10 @@
 	status = "ok";
 	current-speed = <115200>;
 };
+
+&eth {
+	status = "ok";
+	ptp {
+		status = "ok";
+	};
+};

boards/arm/mimxrt1064_evk/mimxrt1064_evk.yaml

@@ -16,3 +16,4 @@ ram: 128
 flash: 128
 supported:
   - hwinfo
+  - netif:eth

boards/arm/mimxrt1064_evk/pinmux.c

@@ -6,6 +6,15 @@
 
 #include <init.h>
 #include <fsl_iomuxc.h>
+#include <fsl_gpio.h>
+
+#ifdef CONFIG_ETH_MCUX_0
+static gpio_pin_config_t enet_gpio_config = {
+	.direction = kGPIO_DigitalOutput,
+	.outputLogic = 0,
+	.interruptMode = kGPIO_NoIntmode
+};
+#endif
 
 static int mimxrt1064_evk_init(struct device *dev)
 {
@@ -14,6 +23,7 @@ static int mimxrt1064_evk_init(struct device *dev)
 	CLOCK_EnableClock(kCLOCK_Iomuxc);
 	CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
 
+#ifndef CONFIG_ETH_MCUX_0
 	/* LED */
 	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0);
 
@@ -24,6 +34,7 @@ static int mimxrt1064_evk_init(struct device *dev)
 
 	/* SW0 */
 	IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0);
+#endif
 
 #ifdef CONFIG_UART_MCUX_LPUART_1
 	/* LPUART1 TX/RX */
@@ -41,7 +52,59 @@ static int mimxrt1064_evk_init(struct device *dev)
 			    IOMUXC_SW_PAD_CTL_PAD_DSE(6));
 #endif
 
+#ifdef CONFIG_ETH_MCUX_0
+	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, 0U);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 1);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDC, 0);
+	IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0);
+
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0xB0A9u);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, 0xB0A9u);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0xB0E9);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0xB0E9);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0xB0E9);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0xB0E9);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0xB0E9);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0xB0E9);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 0x31);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0xB0E9);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_40_ENET_MDC, 0xB0E9);
+	IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0xB829);
+
+	IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
+
+	/* Intialize ENET_INT GPIO */
+	GPIO_PinInit(GPIO1, 9, &enet_gpio_config);
+	GPIO_PinInit(GPIO1, 10, &enet_gpio_config);
+
+	/* pull up the ENET_INT before RESET. */
+	GPIO_WritePinOutput(GPIO1, 10, 1);
+	GPIO_WritePinOutput(GPIO1, 9, 0);
+#endif
+
 	return 0;
 }
 
+#ifdef CONFIG_ETH_MCUX_0
+static int mimxrt1064_evk_phy_reset(struct device *dev)
+{
+	/* RESET PHY chip. */
+	k_busy_wait(10*USEC_PER_MSEC);
+	GPIO_WritePinOutput(GPIO1, 9, 1);
+
+	return 0;
+}
+#endif
+
 SYS_INIT(mimxrt1064_evk_init, PRE_KERNEL_1, 0);
+#ifdef CONFIG_ETH_MCUX_0
+SYS_INIT(mimxrt1064_evk_phy_reset, PRE_KERNEL_2, 0);
+#endif

soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1064

@@ -23,4 +23,11 @@ config IPG_DIV
 config GPIO
 	def_bool y
 
+if NET_L2_ETHERNET
+
+config INIT_ENET_PLL
+	def_bool y
+
+endif # NET_L2_ETHERNET
+
 endif # SOC_MIMXRT1064

soc/arm/nxp_imx/rt/Kconfig.soc

@@ -99,6 +99,7 @@ config SOC_MIMXRT1062
 config SOC_MIMXRT1064
 	bool "SOC_MIMXRT1064"
 	select HAS_MCUX
+	select HAS_MCUX_CACHE
 	select HAS_MCUX_CCM
 	select HAS_MCUX_ELCDIF
 	select HAS_MCUX_ENET