diff --git a/soc/arm/CMakeLists.txt b/soc/arm/CMakeLists.txt index b42e9be8863..f854c3b7d1e 100644 --- a/soc/arm/CMakeLists.txt +++ b/soc/arm/CMakeLists.txt @@ -1,5 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 +add_subdirectory_ifdef(CONFIG_CPU_CORTEX_M common/cortex_m) + if(SOC_FAMILY) add_subdirectory(${SOC_FAMILY}) else() diff --git a/soc/arm/Kconfig b/soc/arm/Kconfig index 189b98e1bbd..5be3950aeda 100644 --- a/soc/arm/Kconfig +++ b/soc/arm/Kconfig @@ -17,6 +17,15 @@ config CPU_HAS_NXP_MPU This option is enabled when the CPU has a Memory Protection Unit (MPU) in NXP flavor. +config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + bool "Custom fixed SoC MPU region definition" + help + If enabled, this option signifies that the SoC will + define and configure its own fixed MPU regions in the + SoC definition. These fixed MPU regions are currently + used to set Flash and SRAM default access policies and + they are programmed at boot time. + config CPU_HAS_ARM_SAU bool select CPU_HAS_TEE diff --git a/soc/arm/common/cortex_m/CMakeLists.txt b/soc/arm/common/cortex_m/CMakeLists.txt new file mode 100644 index 00000000000..f6016604726 --- /dev/null +++ b/soc/arm/common/cortex_m/CMakeLists.txt @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_ARM_MPU AND NOT CONFIG_CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS) + + zephyr_library() + + zephyr_library_sources_ifdef(CONFIG_CPU_HAS_ARM_MPU + arm_mpu_regions.c + ) + zephyr_library_sources_ifdef(CONFIG_CPU_HAS_NXP_MPU + nxp_mpu_regions.c + ) +endif() diff --git a/soc/arm/common/cortex_m/arm_mpu_mem_cfg.h b/soc/arm/common/cortex_m/arm_mpu_mem_cfg.h new file mode 100644 index 00000000000..4720423b417 --- /dev/null +++ b/soc/arm/common/cortex_m/arm_mpu_mem_cfg.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2017 Linaro Limited. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _ARM_CORTEX_M_MPU_MEM_CFG_H_ +#define _ARM_CORTEX_M_MPU_MEM_CFG_H_ + +#include + +#if !defined(CONFIG_ARMV8_M_BASELINE) && !defined(CONFIG_ARMV8_M_MAINLINE) + +/* Flash Region Definitions */ +#if CONFIG_FLASH_SIZE <= 64 +#define REGION_FLASH_SIZE REGION_64K +#elif CONFIG_FLASH_SIZE <= 128 +#define REGION_FLASH_SIZE REGION_128K +#elif CONFIG_FLASH_SIZE <= 256 +#define REGION_FLASH_SIZE REGION_256K +#elif CONFIG_FLASH_SIZE <= 512 +#define REGION_FLASH_SIZE REGION_512K +#elif CONFIG_FLASH_SIZE <= 1024 +#define REGION_FLASH_SIZE REGION_1M +#elif CONFIG_FLASH_SIZE <= 2048 +#define REGION_FLASH_SIZE REGION_2M +#elif CONFIG_FLASH_SIZE <= 4096 +#define REGION_FLASH_SIZE REGION_4M +#elif CONFIG_FLASH_SIZE <= 8192 +#define REGION_FLASH_SIZE REGION_8M +#elif CONFIG_FLASH_SIZE <= 16384 +#define REGION_FLASH_SIZE REGION_16M +#elif CONFIG_FLASH_SIZE <= 65536 +#define REGION_FLASH_SIZE REGION_64M +#else +#error "Unsupported configuration" +#endif + +/* SRAM Region Definitions */ +#if CONFIG_SRAM_SIZE <= 16 +#define REGION_SRAM_SIZE REGION_16K +#elif CONFIG_SRAM_SIZE <= 32 +#define REGION_SRAM_SIZE REGION_32K +#elif CONFIG_SRAM_SIZE <= 64 +#define REGION_SRAM_SIZE REGION_64K +#elif CONFIG_SRAM_SIZE <= 128 +#define REGION_SRAM_SIZE REGION_128K +#elif CONFIG_SRAM_SIZE <= 256 +#define REGION_SRAM_SIZE REGION_256K +#elif CONFIG_SRAM_SIZE <= 512 +#define REGION_SRAM_SIZE REGION_512K +#elif CONFIG_SRAM_SIZE <= 1024 +#define REGION_SRAM_SIZE REGION_1M +#elif CONFIG_SRAM_SIZE <= 2048 +#define REGION_SRAM_SIZE REGION_2M +#elif CONFIG_SRAM_SIZE <= 4096 +#define REGION_SRAM_SIZE REGION_4M +#elif CONFIG_SRAM_SIZE == 32768 +#define REGION_SRAM_SIZE REGION_32M +#else +#error "Unsupported configuration" +#endif + +#endif /* !ARMV8_M_BASELINE && !ARMV8_M_MAINLINE */ + +#endif /* _ARM_CORTEX_M_MPU_MEM_CFG_H_ */ diff --git a/soc/arm/common/cortex_m/arm_mpu_regions.c b/soc/arm/common/cortex_m/arm_mpu_regions.c new file mode 100644 index 00000000000..2428e2f473c --- /dev/null +++ b/soc/arm/common/cortex_m/arm_mpu_regions.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2017 Linaro Limited. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#include "arm_mpu_mem_cfg.h" + +static const struct arm_mpu_region mpu_regions[] = { + /* Region 0 */ + MPU_REGION_ENTRY("FLASH_0", + CONFIG_FLASH_BASE_ADDRESS, +#if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE) + REGION_FLASH_ATTR(CONFIG_FLASH_BASE_ADDRESS, \ + CONFIG_FLASH_SIZE * 1024)), +#else + REGION_FLASH_ATTR(REGION_FLASH_SIZE)), +#endif + /* Region 1 */ + MPU_REGION_ENTRY("SRAM_0", + CONFIG_SRAM_BASE_ADDRESS, +#if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE) + REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS, \ + CONFIG_SRAM_SIZE * 1024)), +#else + REGION_RAM_ATTR(REGION_SRAM_SIZE)), +#endif +}; + +const struct arm_mpu_config mpu_config = { + .num_regions = ARRAY_SIZE(mpu_regions), + .mpu_regions = mpu_regions, +};