arm: cmsis: Convert _ScbIsNestedExc to use direct CMSIS register access
Jira: ZEP-1568 Change-Id: I3d41fe88293bab2f40d9177cedb56e9265250dff Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
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3 changed files with 3 additions and 17 deletions
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@ -88,7 +88,7 @@ _stack_frame_endif:
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eors.n r0, r0
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msr BASEPRI, r0
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/* this reimplements _ScbIsNestedExc() */
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/* this checks to see if we are in a nested exception */
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ldr ip, =_SCS_ICSR
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ldr ip, [ip]
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ands.w ip, #_SCS_ICSR_RETTOBASE
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@ -53,7 +53,8 @@ static ALWAYS_INLINE int _IsInIsr(void)
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#if defined(CONFIG_ARMV6_M)
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return (vector > 10) || (vector == 3);
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#elif defined(CONFIG_ARMV7_M)
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return (vector > 10) || (vector && _ScbIsNestedExc());
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return (vector > 10) ||
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(vector && !(SCB->ICSR & SCB_ICSR_RETTOBASE_Msk));
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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@ -61,21 +61,6 @@ static inline uint32_t _ScbActiveVectorGet(void)
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_ARMV7_M)
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/**
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*
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* @brief Find out if the currently executing exception is nested
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*
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* This routine determines if the currently executing exception is nested.
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*
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* @return 1 if nested, 0 otherwise
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*/
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static inline int _ScbIsNestedExc(void)
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{
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/* !bit == preempted exceptions */
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return !__scs.scb.icsr.bit.rettobase;
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}
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/**
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*
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* @brief Enable faulting on division by zero
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