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arm: cmsis: Convert _ScbIsNestedExc to use direct CMSIS register access

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Jira: ZEP-1568

Change-Id: I3d41fe88293bab2f40d9177cedb56e9265250dff
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2017-01-25 08:32:54 -06:00 • committed by Maureen Helm
commit cecdc99f38
3 changed files with 3 additions and 17 deletions
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2
arch/arm/core/fault_s.S
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@ -88,7 +88,7 @@ _stack_frame_endif:
eors.n r0, r0 eors.n r0, r0
msr BASEPRI, r0 msr BASEPRI, r0
/* this reimplements _ScbIsNestedExc() */ /* this checks to see if we are in a nested exception */
ldr ip, =_SCS_ICSR ldr ip, =_SCS_ICSR
ldr ip, [ip] ldr ip, [ip]
ands.w ip, #_SCS_ICSR_RETTOBASE ands.w ip, #_SCS_ICSR_RETTOBASE

3
arch/arm/include/cortex_m/exc.h
View file

@ -53,7 +53,8 @@ static ALWAYS_INLINE int _IsInIsr(void)
#if defined(CONFIG_ARMV6_M) #if defined(CONFIG_ARMV6_M)
return (vector > 10) || (vector == 3); return (vector > 10) || (vector == 3);
#elif defined(CONFIG_ARMV7_M) #elif defined(CONFIG_ARMV7_M)
return (vector > 10) || (vector && _ScbIsNestedExc()); return (vector > 10) ||
(vector && !(SCB->ICSR & SCB_ICSR_RETTOBASE_Msk));
#else #else
#error Unknown ARM architecture #error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */ #endif /* CONFIG_ARMV6_M */

15
include/arch/arm/cortex_m/scb.h
View file

@ -61,21 +61,6 @@ static inline uint32_t _ScbActiveVectorGet(void)
#if defined(CONFIG_ARMV6_M) #if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_ARMV7_M) #elif defined(CONFIG_ARMV7_M)
/**
*
* @brief Find out if the currently executing exception is nested
*
* This routine determines if the currently executing exception is nested.
*
* @return 1 if nested, 0 otherwise
*/
static inline int _ScbIsNestedExc(void)
{
/* !bit == preempted exceptions */
return !__scs.scb.icsr.bit.rettobase;
}
/** /**
* *
* @brief Enable faulting on division by zero * @brief Enable faulting on division by zero