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drivers/flash: qspi stm32: use new pinctrl API

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Use the new pinctrl API to configure pins.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2021-11-08 10:49:45 +01:00 • committed by Carles Cufí
commit cec2cb69dd
2 changed files with 7 additions and 16 deletions
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17
drivers/flash/flash_stm32_qspi.c
View file

@ -13,7 +13,7 @@
#include <arch/common/ffs.h> #include <arch/common/ffs.h>
#include <sys/util.h> #include <sys/util.h>
#include <soc.h> #include <soc.h>
#include <pinmux/pinmux_stm32.h> #include <drivers/pinctrl.h>
#include <drivers/clock_control/stm32_clock_control.h> #include <drivers/clock_control/stm32_clock_control.h>
#include <drivers/clock_control.h> #include <drivers/clock_control.h>
#include <drivers/flash.h> #include <drivers/flash.h>
@ -63,8 +63,7 @@ struct flash_stm32_qspi_config {
irq_config_func_t irq_config; irq_config_func_t irq_config;
size_t flash_size; size_t flash_size;
uint32_t max_frequency; uint32_t max_frequency;
const struct soc_gpio_pinctrl *pinctrl_list; const struct pinctrl_dev_config *pcfg;
size_t pinctrl_list_size;
}; };
struct flash_stm32_qspi_data { struct flash_stm32_qspi_data {
@ -652,9 +651,7 @@ static int flash_stm32_qspi_init(const struct device *dev)
int ret; int ret;
/* Signals configuration */ /* Signals configuration */
ret = stm32_dt_pinctrl_configure(dev_cfg->pinctrl_list, ret = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT);
dev_cfg->pinctrl_list_size,
(uint32_t)dev_cfg->regs);
if (ret < 0) { if (ret < 0) {
LOG_ERR("QSPI pinctrl setup failed (%d)", ret); LOG_ERR("QSPI pinctrl setup failed (%d)", ret);
return ret; return ret;
@ -860,11 +857,10 @@ static int flash_stm32_qspi_init(const struct device *dev)
static void flash_stm32_qspi_irq_config_func(const struct device *dev); static void flash_stm32_qspi_irq_config_func(const struct device *dev);
static const struct soc_gpio_pinctrl qspi_pins[] =
ST_STM32_DT_PINCTRL(quadspi, 0);
#define STM32_QSPI_NODE DT_PARENT(DT_DRV_INST(0)) #define STM32_QSPI_NODE DT_PARENT(DT_DRV_INST(0))
PINCTRL_DT_DEFINE(STM32_QSPI_NODE)
static const struct flash_stm32_qspi_config flash_stm32_qspi_cfg = { static const struct flash_stm32_qspi_config flash_stm32_qspi_cfg = {
.regs = (QUADSPI_TypeDef *)DT_REG_ADDR(STM32_QSPI_NODE), .regs = (QUADSPI_TypeDef *)DT_REG_ADDR(STM32_QSPI_NODE),
.pclken = { .pclken = {
@ -874,8 +870,7 @@ static const struct flash_stm32_qspi_config flash_stm32_qspi_cfg = {
.irq_config = flash_stm32_qspi_irq_config_func, .irq_config = flash_stm32_qspi_irq_config_func,
.flash_size = DT_INST_PROP(0, size) / 8U, .flash_size = DT_INST_PROP(0, size) / 8U,
.max_frequency = DT_INST_PROP(0, qspi_max_frequency), .max_frequency = DT_INST_PROP(0, qspi_max_frequency),
.pinctrl_list = qspi_pins, .pcfg = PINCTRL_DT_DEV_CONFIG_GET(STM32_QSPI_NODE),
.pinctrl_list_size = ARRAY_SIZE(qspi_pins),
}; };
static struct flash_stm32_qspi_data flash_stm32_qspi_dev_data = { static struct flash_stm32_qspi_data flash_stm32_qspi_dev_data = {

6
dts/bindings/qspi/st,stm32-qspi.yaml
View file

@ -18,7 +18,7 @@ description: |
compatible: "st,stm32-qspi" compatible: "st,stm32-qspi"
include: base.yaml include: [base.yaml, pinctrl-device.yaml]
bus: qspi bus: qspi
@ -44,7 +44,3 @@ properties:
For example For example
dma-names = "tx_rx"; dma-names = "tx_rx";
pinctrl-0:
type: phandles
required: true