drivers: pinctrl: add NXP S32 SIUL2 driver

Introduce Pinctrl driver for SIUL2 module present on NXP S32 devices,
which provides control over all pins, such as function selection and
electrical characteristics that appear on external chip pins.

Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>

drivers/pinctrl/CMakeLists.txt

@@ -25,3 +25,4 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_RV32M1 pinctrl_rv32m1.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_XLNX_ZYNQ pinctrl_xlnx_zynq.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_SMARTBOND pinctrl_smartbond.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_XMC4XXX pinctrl_xmc4xxx.c)
+zephyr_library_sources_ifdef(CONFIG_PINCTRL_S32 pinctrl_s32.c)

drivers/pinctrl/Kconfig

@@ -54,5 +54,6 @@ source "drivers/pinctrl/Kconfig.rv32m1"
 source "drivers/pinctrl/Kconfig.xlnx"
 source "drivers/pinctrl/Kconfig.smartbond"
 source "drivers/pinctrl/Kconfig.xmc4xxx"
+source "drivers/pinctrl/Kconfig.s32"
 
 endif # PINCTRL

drivers/pinctrl/Kconfig.s32

@@ -0,0 +1,9 @@
+# Copyright 2022 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config PINCTRL_S32
+	bool "Pin controller driver for NXP S32 processors"
+	default y
+	depends on DT_HAS_NXP_S32ZE_PINCTRL_ENABLED
+	help
+	  Enable pin controller driver for NXP S32 processors.

drivers/pinctrl/pinctrl_s32.c

@@ -0,0 +1,24 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/pinctrl.h>
+
+#include <Siul2_Port_Ip.h>
+
+int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
+{
+	/*
+	 * By invoking Siul2_Port_Ip_Init multiple times on each group of pins,
+	 * some functions like Siul2_Port_Ip_GetPinConfiguration and
+	 * Siul2_Port_Ip_RevertPinConfiguration cannot be used since the internal
+	 * state is not preserved between calls. Nevertheless, those functions
+	 * are not needed to implement Pinctrl driver, so it's safe to use it
+	 * until a public API exists to init each pin individually.
+	 */
+	Siul2_Port_Ip_Init(pin_cnt, pins);
+
+	return 0;
+}

dts/bindings/pinctrl/nxp,s32ze-pinctrl.yaml

@@ -0,0 +1,119 @@
+# Copyright 2022 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  NXP S32 pinctrl node for S32Z/E SoCs.
+
+  The NXP S32 pin controller is a singleton node responsible for controlling
+  the pin function selection and pin properties. This node, labeled 'pinctrl' in
+  the SoC's devicetree, will define pin configurations in pin groups. Each group
+  within the pin configuration defines the pin configuration for a peripheral,
+  and each numbered subgroup in the pin group defines all the pins for that
+  peripheral with the same configuration properties. The 'pinmux' property in
+  a group selects the pins to be configured, and the remaining properties set
+  configuration values for those pins.
+
+  For example, to configure the pinmux for UART0, modify the 'pinctrl' from your
+  board or application devicetree overlay as follows:
+
+    /* Include the SoC package header containing the predefined pins definitions */
+    #include <nxp/s32/S32Z27-BGA594-pinctrl.h>
+
+    &pinctrl {
+      uart0_default: uart0_default {
+        group1 {
+          pinmux = <PB10_LIN_0_TX>;
+          output-enable;
+        };
+        group2 {
+          pinmux = <PB11_LIN_0_RX>;
+          input-enable;
+        };
+      };
+    };
+
+  The 'uart0_default' node contains the pin configurations for a particular state
+  of a device. The 'default' state is the active state. Other states for the same
+  device can be specified in separate child nodes of 'pinctrl'.
+
+  In addition to 'pinmux' property, each group can contain other properties such as
+  'bias-pull-up' or 'slew-rate' that will be applied to all the pins defined in
+  'pinmux' array. To enable the input buffer use 'input-enable' and to enable the
+  output buffer use 'output-enable'.
+
+  To link the pin configurations with UART0 device, use pinctrl-N property in the
+  device node, where 'N' is the zero-based state index (0 is the default state).
+  Following previous example:
+
+    &uart0 {
+      pinctrl-0 = <&uart0_default>;
+      pinctrl-names = "default";
+      status = "okay";
+    };
+
+  If only the required properties are supplied, the pin configuration register
+  will be assigned the following reset values:
+    - input and output buffers disabled
+    - internal pull not enabled
+    - open drain disabled
+    - slew rate 4 (see description in property below).
+
+  Additionally, Safe Mode is always disabled (reset value) and configuration that
+  only applies to LVDS pads, which are not supported, default to reset values:
+    - termination resistor disabled
+    - receiver single ended
+    - current reference control disabled
+    - Rx current boost disabled.
+
+compatible: "nxp,s32ze-pinctrl"
+
+include:
+  - name: base.yaml
+  - name: pincfg-node-group.yaml
+    child-binding:
+      child-binding:
+        property-allowlist:
+          - bias-pull-down
+          - bias-pull-up
+          - drive-open-drain
+          - slew-rate
+          - input-enable
+          - output-enable
+
+child-binding:
+  description: NXP S32 pin controller pin group.
+  child-binding:
+    description: NXP S32 pin controller pin configuration node.
+    properties:
+      pinmux:
+        required: true
+        type: array
+        description: |
+          An array of pins sharing the same group properties. The pins must be
+          defined using the macros from the SoC package header. These macros
+          encode all the pin muxing information in a 32-bit value.
+
+      slew-rate:
+        required: false
+        enum: [0, 4, 5, 6, 7]
+        default: 4
+        description: |
+          Slew rate control. Reset value is 4.
+          - For 3.3 V / 1.8 V FAST pads:
+            0: FMAX_3318 = 208 MHz (at 1.8 V), 166 MHz (at 3.3 V)
+            4: FMAX_3318 = 166 MHz (at 1.8 V), 150 MHz (at 3.3 V)
+            5: FMAX_3318 = 150 MHz (at 1.8 V), 133 MHz (at 3.3 V)
+            6: FMAX_3318 = 133 MHz (at 1.8 V), 100 MHz (at 3.3 V)
+            7: FMAX_3318 = 100 MHz (at 1.8 V), 83 MHz (at 3.3 V)
+          - For 1.8 V GPIO pads:
+            0: FMAX_18 = 208 MHz
+            4: FMAX_18 = 150 MHz
+            5: FMAX_18 = 133 MHz
+            6: FMAX_18 = 100 MHz
+            7: FMAX_18 = 50 MHz
+          - For 3.3 V GPIO pads:
+            0: Reserved
+            4: FMAX_33 = 50 MHz
+            5: FMAX_33 = 50 MHz
+            6: FMAX_33 = 50 MHz
+            7: FMAX_33 = 1 MHz