From cdcba384bc544cd9859cf1e635cb8d5cbe002633 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Manuel=20Arg=C3=BCelles?= Date: Fri, 15 Sep 2023 18:54:28 +0700 Subject: [PATCH] spi: nxp_s32: use clock control APIs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use clock control API to retrieve the module's frequency and update the boards using it to provide the source clocks. Signed-off-by: Manuel Argüelles --- boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi | 40 ----------------- drivers/spi/spi_nxp_s32.c | 43 +++++++++++++++---- drivers/spi/spi_nxp_s32.h | 5 ++- dts/arm/nxp/nxp_s32z27x_r52.dtsi | 10 +++++ dts/bindings/spi/nxp,s32-spi.yaml | 7 +-- 5 files changed, 49 insertions(+), 56 deletions(-) diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi b/boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi index a0dc5df74c3..0176ebc4458 100644 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi +++ b/boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi @@ -7,46 +7,6 @@ #include #include "s32z270dc2_r52-pinctrl-common.dtsi" -&spi0 { - clock-frequency = <100000000>; -}; - -&spi1 { - clock-frequency = <100000000>; -}; - -&spi2 { - clock-frequency = <100000000>; -}; - -&spi3 { - clock-frequency = <120000000>; -}; - -&spi4 { - clock-frequency = <120000000>; -}; - -&spi5 { - clock-frequency = <120000000>; -}; - -&spi6 { - clock-frequency = <120000000>; -}; - -&spi7 { - clock-frequency = <100000000>; -}; - -&spi8 { - clock-frequency = <100000000>; -}; - -&spi9 { - clock-frequency = <100000000>; -}; - &stm0 { clock-frequency = <133333333>; }; diff --git a/drivers/spi/spi_nxp_s32.c b/drivers/spi/spi_nxp_s32.c index 30dbe4d134a..f0d59ea443d 100644 --- a/drivers/spi/spi_nxp_s32.c +++ b/drivers/spi/spi_nxp_s32.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include #include "spi_nxp_s32.h" @@ -273,12 +274,20 @@ static int spi_nxp_s32_configure(const struct device *dev, uint8_t frame_size; struct spi_nxp_s32_baudrate_param best_baud = {0}; + uint32_t clock_rate; + int err; if (spi_context_configured(&data->ctx, spi_cfg)) { /* This configuration is already in use */ return 0; } + err = clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_rate); + if (err) { + LOG_ERR("Failed to get clock frequency"); + return err; + } + clk_phase = !!(SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPHA); clk_polarity = !!(SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL); @@ -340,7 +349,7 @@ static int spi_nxp_s32_configure(const struct device *dev, return -ENOTSUP; } - spi_nxp_s32_getbestfreq(config->clock_frequency, spi_cfg->frequency, &best_baud); + spi_nxp_s32_getbestfreq(clock_rate, spi_cfg->frequency, &best_baud); data->transfer_cfg.Ctar &= ~(SPI_CTAR_BR_MASK | SPI_CTAR_PBR_MASK); data->transfer_cfg.Ctar |= SPI_CTAR_BR(best_baud.scaler) | @@ -486,12 +495,29 @@ static int spi_nxp_s32_init(const struct device *dev) { const struct spi_nxp_s32_config *config = dev->config; struct spi_nxp_s32_data *data = dev->data; - + uint32_t clock_rate; uint8_t scaler, prescaler; uint32_t ctar = 0; int ret = 0; + if (!device_is_ready(config->clock_dev)) { + LOG_ERR("Clock control device not ready"); + return -ENODEV; + } + + ret = clock_control_on(config->clock_dev, config->clock_subsys); + if (ret) { + LOG_ERR("Failed to enable clock"); + return ret; + } + + ret = clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_rate); + if (ret) { + LOG_ERR("Failed to get clock frequency"); + return ret; + } + ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT); if (ret < 0) { return ret; @@ -513,18 +539,15 @@ static int spi_nxp_s32_init(const struct device *dev) * Update the delay timings configuration that are * applied for all inner CS signals of SPI module. */ - spi_nxp_s32_getbestdelay(config->clock_frequency, - config->sck_cs_delay, &scaler, &prescaler); + spi_nxp_s32_getbestdelay(clock_rate, config->sck_cs_delay, &scaler, &prescaler); ctar |= SPI_CTAR_ASC(scaler) | SPI_CTAR_PASC(prescaler); - spi_nxp_s32_getbestdelay(config->clock_frequency, - config->cs_sck_delay, &scaler, &prescaler); + spi_nxp_s32_getbestdelay(clock_rate, config->cs_sck_delay, &scaler, &prescaler); ctar |= SPI_CTAR_CSSCK(scaler) | SPI_CTAR_PCSSCK(prescaler); - spi_nxp_s32_getbestdelay(config->clock_frequency, - config->cs_cs_delay, &scaler, &prescaler); + spi_nxp_s32_getbestdelay(clock_rate, config->cs_cs_delay, &scaler, &prescaler); ctar |= SPI_CTAR_DT(scaler) | SPI_CTAR_PDT(prescaler); @@ -654,7 +677,9 @@ static const struct spi_driver_api spi_nxp_s32_driver_api = { static const struct spi_nxp_s32_config spi_nxp_s32_config_##n = { \ .instance = n, \ .num_cs = SPI_NXP_S32_NUM_CS(n), \ - .clock_frequency = DT_PROP(SPI_NXP_S32_NODE(n), clock_frequency), \ + .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(SPI_NXP_S32_NODE(n))), \ + .clock_subsys = (clock_control_subsys_t) \ + DT_CLOCKS_CELL(SPI_NXP_S32_NODE(n), name), \ .sck_cs_delay = DT_PROP_OR(SPI_NXP_S32_NODE(n), spi_sck_cs_delay, 0U), \ .cs_sck_delay = DT_PROP_OR(SPI_NXP_S32_NODE(n), spi_cs_sck_delay, 0U), \ .cs_cs_delay = DT_PROP_OR(SPI_NXP_S32_NODE(n), spi_cs_cs_delay, 0U), \ diff --git a/drivers/spi/spi_nxp_s32.h b/drivers/spi/spi_nxp_s32.h index 39bf630e646..3d01d1625bf 100644 --- a/drivers/spi/spi_nxp_s32.h +++ b/drivers/spi/spi_nxp_s32.h @@ -1,5 +1,5 @@ /* - * Copyright 2022 NXP + * Copyright 2022-2023 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -49,7 +49,8 @@ struct spi_nxp_s32_data { struct spi_nxp_s32_config { uint8_t instance; uint8_t num_cs; - uint32_t clock_frequency; + const struct device *clock_dev; + clock_control_subsys_t clock_subsys; uint32_t sck_cs_delay; uint32_t cs_sck_delay; uint32_t cs_cs_delay; diff --git a/dts/arm/nxp/nxp_s32z27x_r52.dtsi b/dts/arm/nxp/nxp_s32z27x_r52.dtsi index 5728e3e3ff9..691df7750f5 100644 --- a/dts/arm/nxp/nxp_s32z27x_r52.dtsi +++ b/dts/arm/nxp/nxp_s32z27x_r52.dtsi @@ -457,6 +457,7 @@ compatible = "nxp,s32-spi"; reg = <0x40130000 0x10000>; interrupts = ; + clocks = <&clock NXP_S32_SPI0_CLK>; num-cs = <5>; #address-cells = <1>; #size-cells = <0>; @@ -467,6 +468,7 @@ compatible = "nxp,s32-spi"; reg = <0x40140000 0x10000>; interrupts = ; + clocks = <&clock NXP_S32_SPI1_CLK>; num-cs = <5>; #address-cells = <1>; #size-cells = <0>; @@ -477,6 +479,7 @@ compatible = "nxp,s32-spi"; reg = <0x40930000 0x10000>; interrupts = ; + clocks = <&clock NXP_S32_SPI2_CLK>; num-cs = <5>; #address-cells = <1>; #size-cells = <0>; @@ -487,6 +490,7 @@ compatible = "nxp,s32-spi"; reg = <0x40940000 0x10000>; interrupts = ; + clocks = <&clock NXP_S32_SPI3_CLK>; num-cs = <5>; #address-cells = <1>; #size-cells = <0>; @@ -497,6 +501,7 @@ compatible = "nxp,s32-spi"; reg = <0x40950000 0x10000>; interrupts = ; + clocks = <&clock NXP_S32_SPI4_CLK>; num-cs = <5>; #address-cells = <1>; #size-cells = <0>; @@ -507,6 +512,7 @@ compatible = "nxp,s32-spi"; reg = <0x42130000 0x10000>; interrupts = ; + clocks = <&clock NXP_S32_SPI5_CLK>; num-cs = <5>; #address-cells = <1>; #size-cells = <0>; @@ -517,6 +523,7 @@ compatible = "nxp,s32-spi"; reg = <0x42140000 0x10000>; interrupts = ; + clocks = <&clock NXP_S32_SPI6_CLK>; num-cs = <5>; #address-cells = <1>; #size-cells = <0>; @@ -527,6 +534,7 @@ compatible = "nxp,s32-spi"; reg = <0x42150000 0x10000>; interrupts = ; + clocks = <&clock NXP_S32_SPI7_CLK>; num-cs = <5>; #address-cells = <1>; #size-cells = <0>; @@ -537,6 +545,7 @@ compatible = "nxp,s32-spi"; reg = <0x42930000 0x10000>; interrupts = ; + clocks = <&clock NXP_S32_SPI8_CLK>; num-cs = <5>; #address-cells = <1>; #size-cells = <0>; @@ -547,6 +556,7 @@ compatible = "nxp,s32-spi"; reg = <0x42940000 0x10000>; interrupts = ; + clocks = <&clock NXP_S32_SPI9_CLK>; num-cs = <5>; #address-cells = <1>; #size-cells = <0>; diff --git a/dts/bindings/spi/nxp,s32-spi.yaml b/dts/bindings/spi/nxp,s32-spi.yaml index 722b3add3db..f505da6d8d1 100644 --- a/dts/bindings/spi/nxp,s32-spi.yaml +++ b/dts/bindings/spi/nxp,s32-spi.yaml @@ -1,4 +1,4 @@ -# Copyright 2022 NXP +# Copyright 2022-2023 NXP # SPDX-License-Identifier: Apache-2.0 description: NXP S32 SPI controller @@ -20,11 +20,8 @@ properties: description: | The number of the Chip Select signals. - clock-frequency: - type: int + clocks: required: true - description: | - Module clock frequency in Hz. pinctrl-0: required: true