arch: common: refactor multi-level IRQ code
Refactor multi-level IRQ related code from `sw_isr_common.c` to `multilevel_irq.c` to simplify `sw_isr_common` & macrologies. Signed-off-by: Yong Cong Sin <ycsin@meta.com>
This commit is contained in:
Yong Cong Sin
Carles Cufí
parent
ec93404a26
commit
cdb606aa03
3 changed files with 179 additions and 179 deletions
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@ -12,6 +12,11 @@ zephyr_library_sources_ifdef(
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sw_isr_common.c
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sw_isr_common.c
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)
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)
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zephyr_library_sources_ifdef(
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CONFIG_MULTI_LEVEL_INTERRUPTS
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multilevel_irq.c
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)
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zephyr_library_sources_ifdef(CONFIG_SHARED_INTERRUPTS shared_irq.c)
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zephyr_library_sources_ifdef(CONFIG_SHARED_INTERRUPTS shared_irq.c)
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if(NOT CONFIG_ARCH_HAS_TIMING_FUNCTIONS AND
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if(NOT CONFIG_ARCH_HAS_TIMING_FUNCTIONS AND
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167
arch/common/multilevel_irq.c
Normal file
167
arch/common/multilevel_irq.c
Normal file
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@ -0,0 +1,167 @@
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/*
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* Copyright (c) 2018 Intel Corporation.
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* Copyright (c) 2023 Meta.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/device.h>
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#include <zephyr/sw_isr_table.h>
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#include <zephyr/sys/util.h>
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/*
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* Insert code if the node_id is an interrupt controller
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*/
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#define Z_IF_DT_IS_INTC(node_id, code) \
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IF_ENABLED(DT_NODE_HAS_PROP(node_id, interrupt_controller), (code))
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/*
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* Expands to node_id if its IRQN is equal to `irq`, nothing otherwise
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* This only works for `irq` between 0 & 4095, see `IS_EQ`
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*/
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#define Z_IF_DT_INTC_IRQN_EQ(node_id, irq) IF_ENABLED(IS_EQ(DT_IRQ(node_id, irq), irq), (node_id))
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/*
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* Expands to node_id if it's an interrupt controller & its IRQN is `irq`, or nothing otherwise
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*/
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#define Z_DT_INTC_GET_IRQN(node_id, irq) \
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Z_IF_DT_IS_INTC(node_id, Z_IF_DT_INTC_IRQN_EQ(node_id, irq))
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/**
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* Loop through child of "/soc" and get root interrupt controllers with `irq` as IRQN,
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* this assumes only one device has the IRQN
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* @param irq irq number
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* @return node_id(s) that has the `irq` number, or empty if none of them has the `irq`
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*/
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#define INTC_DT_IRQN_GET(irq) \
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DT_FOREACH_CHILD_STATUS_OKAY_VARGS(DT_PATH(soc), Z_DT_INTC_GET_IRQN, irq)
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/* If can't find any matching interrupt controller, fills with `NULL` */
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#define INTC_DEVICE_INIT(node_id) .dev = DEVICE_DT_GET_OR_NULL(node_id),
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#define INIT_IRQ_PARENT_OFFSET(d, i, o) { \
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INTC_DEVICE_INIT(d) \
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.irq = i, \
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.offset = o, \
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}
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#define IRQ_INDEX_TO_OFFSET(i, base) (base + i * CONFIG_MAX_IRQ_PER_AGGREGATOR)
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#define CAT_2ND_LVL_LIST(i, base) \
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INIT_IRQ_PARENT_OFFSET(INTC_DT_IRQN_GET(CONFIG_2ND_LVL_INTR_0##i##_OFFSET), \
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CONFIG_2ND_LVL_INTR_0##i##_OFFSET, IRQ_INDEX_TO_OFFSET(i, base))
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const struct _irq_parent_entry _lvl2_irq_list[CONFIG_NUM_2ND_LEVEL_AGGREGATORS]
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= { LISTIFY(CONFIG_NUM_2ND_LEVEL_AGGREGATORS, CAT_2ND_LVL_LIST, (,),
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CONFIG_2ND_LVL_ISR_TBL_OFFSET) };
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#define CAT_3RD_LVL_LIST(i, base) \
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INIT_IRQ_PARENT_OFFSET(INTC_DT_IRQN_GET(CONFIG_3RD_LVL_INTR_0##i##_OFFSET), \
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CONFIG_3RD_LVL_INTR_0##i##_OFFSET, IRQ_INDEX_TO_OFFSET(i, base))
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#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
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const struct _irq_parent_entry _lvl3_irq_list[CONFIG_NUM_3RD_LEVEL_AGGREGATORS]
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= { LISTIFY(CONFIG_NUM_3RD_LEVEL_AGGREGATORS, CAT_3RD_LVL_LIST, (,),
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CONFIG_3RD_LVL_ISR_TBL_OFFSET) };
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#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
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static const struct _irq_parent_entry *get_parent_entry(unsigned int parent_irq,
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const struct _irq_parent_entry list[],
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unsigned int length)
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{
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unsigned int i;
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const struct _irq_parent_entry *entry = NULL;
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for (i = 0U; i < length; ++i) {
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if (list[i].irq == parent_irq) {
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entry = &list[i];
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break;
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}
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}
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__ASSERT(i != length, "Invalid argument: %i", parent_irq);
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return entry;
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}
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const struct device *z_get_sw_isr_device_from_irq(unsigned int irq)
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{
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const struct device *dev = NULL;
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unsigned int level, parent_irq;
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const struct _irq_parent_entry *entry = NULL;
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level = irq_get_level(irq);
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if (level == 2U) {
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parent_irq = irq_parent_level_2(irq);
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entry = get_parent_entry(parent_irq,
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_lvl2_irq_list,
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CONFIG_NUM_2ND_LEVEL_AGGREGATORS);
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}
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#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
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else if (level == 3U) {
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parent_irq = irq_parent_level_3(irq);
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entry = get_parent_entry(parent_irq,
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_lvl3_irq_list,
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CONFIG_NUM_3RD_LEVEL_AGGREGATORS);
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}
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#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
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dev = entry != NULL ? entry->dev : NULL;
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return dev;
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}
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unsigned int z_get_sw_isr_irq_from_device(const struct device *dev)
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{
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for (size_t i = 0U; i < CONFIG_NUM_2ND_LEVEL_AGGREGATORS; ++i) {
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if (_lvl2_irq_list[i].dev == dev) {
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return _lvl2_irq_list[i].irq;
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}
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}
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#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
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for (size_t i = 0U; i < CONFIG_NUM_3RD_LEVEL_AGGREGATORS; ++i) {
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if (_lvl3_irq_list[i].dev == dev) {
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return _lvl3_irq_list[i].irq;
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}
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}
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#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
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return 0;
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}
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unsigned int z_get_sw_isr_table_idx(unsigned int irq)
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{
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unsigned int table_idx;
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unsigned int level, parent_irq, parent_offset;
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const struct _irq_parent_entry *entry = NULL;
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level = irq_get_level(irq);
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if (level == 2U) {
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parent_irq = irq_parent_level_2(irq);
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entry = get_parent_entry(parent_irq,
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_lvl2_irq_list,
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CONFIG_NUM_2ND_LEVEL_AGGREGATORS);
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parent_offset = entry != NULL ? entry->offset : 0U;
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table_idx = parent_offset + irq_from_level_2(irq);
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}
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#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
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else if (level == 3U) {
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parent_irq = irq_parent_level_3(irq);
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entry = get_parent_entry(parent_irq,
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_lvl3_irq_list,
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CONFIG_NUM_3RD_LEVEL_AGGREGATORS);
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parent_offset = entry != NULL ? entry->offset : 0U;
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table_idx = parent_offset + irq_from_level_3(irq);
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}
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#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
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else {
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table_idx = irq;
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}
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table_idx -= CONFIG_GEN_IRQ_START_VECTOR;
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return table_idx;
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}
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@ -4,194 +4,22 @@
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*/
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*/
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#include <zephyr/device.h>
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#include "sw_isr_common.h"
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#include <zephyr/sw_isr_table.h>
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#include <zephyr/sw_isr_table.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/irq.h>
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#include <zephyr/irq.h>
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#include <zephyr/irq_multilevel.h>
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#include <zephyr/sys/__assert.h>
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#include <zephyr/sys/__assert.h>
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/*
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/*
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* Common code for arches that use software ISR tables (CONFIG_GEN_ISR_TABLES)
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* Common code for arches that use software ISR tables (CONFIG_GEN_ISR_TABLES)
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*/
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*/
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unsigned int __weak z_get_sw_isr_table_idx(unsigned int irq)
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{
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return irq - CONFIG_GEN_IRQ_START_VECTOR;
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}
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#ifdef CONFIG_DYNAMIC_INTERRUPTS
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#ifdef CONFIG_DYNAMIC_INTERRUPTS
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#ifdef CONFIG_MULTI_LEVEL_INTERRUPTS
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/*
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* Insert code if the node_id is an interrupt controller
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*/
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#define Z_IF_DT_IS_INTC(node_id, code) \
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IF_ENABLED(DT_NODE_HAS_PROP(node_id, interrupt_controller), (code))
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/*
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* Expands to node_id if its IRQN is equal to `irq`, nothing otherwise
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* This only works for `irq` between 0 & 4095, see `IS_EQ`
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*/
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#define Z_IF_DT_INTC_IRQN_EQ(node_id, irq) IF_ENABLED(IS_EQ(DT_IRQ(node_id, irq), irq), (node_id))
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/*
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* Expands to node_id if it's an interrupt controller & its IRQN is `irq`, or nothing otherwise
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*/
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#define Z_DT_INTC_GET_IRQN(node_id, irq) \
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Z_IF_DT_IS_INTC(node_id, Z_IF_DT_INTC_IRQN_EQ(node_id, irq))
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/**
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* Loop through child of "/soc" and get root interrupt controllers with `irq` as IRQN,
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* this assumes only one device has the IRQN
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* @param irq irq number
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* @return node_id(s) that has the `irq` number, or empty if none of them has the `irq`
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*/
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#define INTC_DT_IRQN_GET(irq) \
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DT_FOREACH_CHILD_STATUS_OKAY_VARGS(DT_PATH(soc), Z_DT_INTC_GET_IRQN, irq)
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/* If can't find any matching interrupt controller, fills with `NULL` */
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#define INTC_DEVICE_INIT(node_id) .dev = DEVICE_DT_GET_OR_NULL(node_id),
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#define INIT_IRQ_PARENT_OFFSET(d, i, o) { \
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INTC_DEVICE_INIT(d) \
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.irq = i, \
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.offset = o, \
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}
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#define IRQ_INDEX_TO_OFFSET(i, base) (base + i * CONFIG_MAX_IRQ_PER_AGGREGATOR)
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#ifdef CONFIG_2ND_LEVEL_INTERRUPTS
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#define CAT_2ND_LVL_LIST(i, base) \
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INIT_IRQ_PARENT_OFFSET(INTC_DT_IRQN_GET(CONFIG_2ND_LVL_INTR_0##i##_OFFSET), \
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CONFIG_2ND_LVL_INTR_0##i##_OFFSET, IRQ_INDEX_TO_OFFSET(i, base))
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const struct _irq_parent_entry _lvl2_irq_list[CONFIG_NUM_2ND_LEVEL_AGGREGATORS]
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= { LISTIFY(CONFIG_NUM_2ND_LEVEL_AGGREGATORS, CAT_2ND_LVL_LIST, (,),
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CONFIG_2ND_LVL_ISR_TBL_OFFSET) };
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#endif/* CONFIG_2ND_LEVEL_INTERRUPTS */
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#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
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#define CAT_3RD_LVL_LIST(i, base) \
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INIT_IRQ_PARENT_OFFSET(INTC_DT_IRQN_GET(CONFIG_3RD_LVL_INTR_0##i##_OFFSET), \
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CONFIG_3RD_LVL_INTR_0##i##_OFFSET, IRQ_INDEX_TO_OFFSET(i, base))
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const struct _irq_parent_entry _lvl3_irq_list[CONFIG_NUM_3RD_LEVEL_AGGREGATORS]
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= { LISTIFY(CONFIG_NUM_3RD_LEVEL_AGGREGATORS, CAT_3RD_LVL_LIST, (,),
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CONFIG_3RD_LVL_ISR_TBL_OFFSET) };
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#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
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static const struct _irq_parent_entry *get_parent_entry(unsigned int parent_irq,
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const struct _irq_parent_entry list[],
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unsigned int length)
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{
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unsigned int i;
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const struct _irq_parent_entry *entry = NULL;
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for (i = 0U; i < length; ++i) {
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if (list[i].irq == parent_irq) {
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entry = &list[i];
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break;
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}
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}
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__ASSERT(i != length, "Invalid argument: %i", parent_irq);
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return entry;
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}
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#endif /* CONFIG_MULTI_LEVEL_INTERRUPTS */
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const struct device *z_get_sw_isr_device_from_irq(unsigned int irq)
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{
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const struct device *dev = NULL;
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#ifdef CONFIG_MULTI_LEVEL_INTERRUPTS
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unsigned int level, parent_irq;
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const struct _irq_parent_entry *entry = NULL;
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level = irq_get_level(irq);
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if (level == 2U) {
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parent_irq = irq_parent_level_2(irq);
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entry = get_parent_entry(parent_irq,
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_lvl2_irq_list,
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CONFIG_NUM_2ND_LEVEL_AGGREGATORS);
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}
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#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
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else if (level == 3U) {
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parent_irq = irq_parent_level_3(irq);
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entry = get_parent_entry(parent_irq,
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_lvl3_irq_list,
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CONFIG_NUM_3RD_LEVEL_AGGREGATORS);
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}
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#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
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dev = entry != NULL ? entry->dev : NULL;
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#endif /* CONFIG_MULTI_LEVEL_INTERRUPTS */
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return dev;
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}
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unsigned int z_get_sw_isr_irq_from_device(const struct device *dev)
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{
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#ifdef CONFIG_MULTI_LEVEL_INTERRUPTS
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for (size_t i = 0U; i < CONFIG_NUM_2ND_LEVEL_AGGREGATORS; ++i) {
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if (_lvl2_irq_list[i].dev == dev) {
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return _lvl2_irq_list[i].irq;
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}
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}
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#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
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for (size_t i = 0U; i < CONFIG_NUM_3RD_LEVEL_AGGREGATORS; ++i) {
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if (_lvl3_irq_list[i].dev == dev) {
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return _lvl3_irq_list[i].irq;
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}
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}
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#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
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#else
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ARG_UNUSED(dev);
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#endif
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return 0;
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}
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unsigned int z_get_sw_isr_table_idx(unsigned int irq)
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{
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unsigned int table_idx;
|
|
||||||
|
|
||||||
#ifdef CONFIG_MULTI_LEVEL_INTERRUPTS
|
|
||||||
unsigned int level, parent_irq, parent_offset;
|
|
||||||
const struct _irq_parent_entry *entry = NULL;
|
|
||||||
|
|
||||||
level = irq_get_level(irq);
|
|
||||||
|
|
||||||
if (level == 2U) {
|
|
||||||
parent_irq = irq_parent_level_2(irq);
|
|
||||||
entry = get_parent_entry(parent_irq,
|
|
||||||
_lvl2_irq_list,
|
|
||||||
CONFIG_NUM_2ND_LEVEL_AGGREGATORS);
|
|
||||||
parent_offset = entry != NULL ? entry->offset : 0U;
|
|
||||||
table_idx = parent_offset + irq_from_level_2(irq);
|
|
||||||
}
|
|
||||||
#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
|
|
||||||
else if (level == 3U) {
|
|
||||||
parent_irq = irq_parent_level_3(irq);
|
|
||||||
entry = get_parent_entry(parent_irq,
|
|
||||||
_lvl3_irq_list,
|
|
||||||
CONFIG_NUM_3RD_LEVEL_AGGREGATORS);
|
|
||||||
parent_offset = entry != NULL ? entry->offset : 0U;
|
|
||||||
table_idx = parent_offset + irq_from_level_3(irq);
|
|
||||||
}
|
|
||||||
#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
|
|
||||||
else {
|
|
||||||
table_idx = irq;
|
|
||||||
}
|
|
||||||
|
|
||||||
table_idx -= CONFIG_GEN_IRQ_START_VECTOR;
|
|
||||||
#else
|
|
||||||
table_idx = irq - CONFIG_GEN_IRQ_START_VECTOR;
|
|
||||||
#endif /* CONFIG_MULTI_LEVEL_INTERRUPTS */
|
|
||||||
|
|
||||||
return table_idx;
|
|
||||||
}
|
|
||||||
|
|
||||||
void __weak z_isr_install(unsigned int irq, void (*routine)(const void *),
|
void __weak z_isr_install(unsigned int irq, void (*routine)(const void *),
|
||||||
const void *param)
|
const void *param)
|
||||||
{
|
{
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue