arch: arm: Optimise Cortex-R exception return function.
z_arm_exc_exit (z_arm_int_exit) requires the current execution mode to be specified as a parameter (through r0). This is not necessary because this value can be directly read from CPSR. This commit modifies the exception return function to retrieve the current execution mode from CPSR and removes all provisions for passing the execution mode parameter. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
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1c3b46daff
commit
cd90d49a86
4 changed files with 4 additions and 27 deletions
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@ -71,10 +71,6 @@ SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_int_exit)
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*/
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SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_exc_exit)
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#if defined(CONFIG_CPU_CORTEX_R)
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/* r0 contains the caller mode */
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push {r0, lr}
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#endif
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#ifdef CONFIG_PREEMPT_ENABLED
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ldr r0, =_kernel
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@ -117,9 +113,6 @@ _EXIT_EXC:
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#if defined(CONFIG_CPU_CORTEX_M)
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bx lr
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#elif defined(CONFIG_CPU_CORTEX_R)
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/* Restore the caller mode to r0 */
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pop {r0, lr}
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/*
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* Restore r0-r3, r12 and lr stored into the process stack by the mode
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* entry function. These registers are saved by _isr_wrapper for IRQ mode
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@ -128,22 +121,15 @@ _EXIT_EXC:
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* r0-r3 are either the values from the thread before it was switched out
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* or they are the args to _new_thread for a new thread.
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*/
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push {r4, r5}
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push {r4-r6}
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mrs r6, cpsr
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cmp r0, #RET_FROM_SVC
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cps #MODE_SYS
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ldmia sp!, {r0-r5}
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beq _svc_exit
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msr cpsr_c, r6
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cps #MODE_IRQ
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b _exc_exit
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_svc_exit:
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cps #MODE_SVC
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_exc_exit:
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mov r12, r4
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mov lr, r5
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pop {r4, r5}
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pop {r4-r6}
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movs pc, lr
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#endif
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@ -195,10 +195,6 @@ _idle_state_cleared:
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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#if defined(CONFIG_CPU_CORTEX_R)
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mov r0, #RET_FROM_IRQ
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#endif
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/* Use 'bx' instead of 'b' because 'bx' can jump further, and use
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* 'bx' instead of 'blx' because exception return is done in
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* z_arm_int_exit() */
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@ -625,7 +625,6 @@ demux:
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blx z_irq_do_offload /* call C routine which executes the offload */
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/* exception return is done in z_arm_int_exit() */
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mov r0, #RET_FROM_SVC
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b z_arm_int_exit
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#endif
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@ -633,7 +632,6 @@ _context_switch:
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/* handler mode exit, to PendSV */
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bl z_arm_pendsv
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mov r0, #RET_FROM_SVC
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b z_arm_int_exit
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_oops:
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@ -31,9 +31,6 @@
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#define FPEXC_EN (1 << 30)
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#define RET_FROM_SVC 0
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#define RET_FROM_IRQ 1
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#define __ISB() __asm__ volatile ("isb sy" : : : "memory")
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#define __DMB() __asm__ volatile ("dmb sy" : : : "memory")
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