arch: added support for the riscv32 architecture

RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.

1) exceptions/interrupts/faults are handled at the architecture
   level via the __irq_wrapper handler. Context saving/restoring
   of registers can be handled at both architecture and SOC levels.
   If SOC-specific registers need to be saved, SOC level needs to
   provide __soc_save_context and __soc_restore_context functions
   that shall be accounted by the architecture level, when
   corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.

2) As RISC-V architecture does not provide a clear ISA specification
   about interrupt handling, each RISC-V SOC handles it in its own
   way. Hence, at the architecture level, the __irq_wrapper handler
   expects the following functions to be provided by the SOC level:
   __soc_is_irq: to check if the exception is the result of an
                 interrupt or not.
   __soc_handle_irq: handle pending IRQ at SOC level (ex: clear
                     pending IRQ in SOC-specific IRQ register)

3) Thread/task scheduling, as well as IRQ offloading are handled via
   the RISC-V system call ("ecall"), which is also handled via the
   __irq_wrapper handler. The _Swap asm function just calls "ecall"
   to generate an exception.

4) As there is no conventional way of handling CPU power save in
   RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
   functions just unlock interrupts and return to the caller, without
   issuing any CPU power saving instruction. Nonetheless, to allow
   SOC-level to implement proper CPU power save, nano_cpu_idle and
   nano_cpu_atomic_idle functions are defined as __weak
   at the architecture level.

Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>

arch/riscv32/core/swap.S

@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#define _ASMLANGUAGE
+#include <irq.h>
+#include <kernel_structs.h>
+#include <offsets_short.h>
+
+/* exports */
+GTEXT(_Swap)
+GTEXT(_thread_entry_wrapper)
+
+/* Use ABI name of registers for the sake of simplicity */
+
+/*
+ * unsigned int _Swap(unsigned int key)
+ *
+ * Always called with interrupts locked
+ * key is stored in a0 register
+ */
+SECTION_FUNC(exception.other, _Swap)
+
+	/* Make a system call to perform context switch */
+	ecall
+
+	/*
+	 * when thread is rescheduled, unlock irq and return.
+	 * Restored register a0 contains IRQ lock state of thread.
+	 *
+	 * Prior to unlocking irq, load return value of
+	 * _Swap to temp register t2 (from _thread_offset_to_swap_return_value).
+	 * Normally, it should be -EAGAIN, unless someone has previously
+	 * called _set_thread_return_value(..).
+	 */
+	la t0, _kernel
+
+	/* Get pointer to _kernel.current */
+	lw t1, _kernel_offset_to_current(t0)
+
+	/* Load return value of _Swap function in temp register t2 */
+	lw t2, _thread_offset_to_swap_return_value(t1)
+
+	/*
+	 * Unlock irq, following IRQ lock state in a0 register.
+	 * Use atomic instruction csrrs to do so.
+	 */
+	andi a0, a0, SOC_MSTATUS_IEN
+	csrrs t0, mstatus, a0
+
+	/* Set value of return register a0 to value of register t2 */
+	addi a0, t2, 0
+
+	/* Return */
+	jalr x0, ra
+
+
+/*
+ * void _thread_entry_wrapper(_thread_entry_t, void *, void *, void *)
+ */
+SECTION_FUNC(TEXT, _thread_entry_wrapper)
+	/*
+	 * _thread_entry_wrapper is called for every new thread upon the return
+	 * of _Swap or ISR. Its address, as well as its input function arguments
+	 * thread_entry_t, void *, void *, void * are restored from the thread
+	 * stack (initialized via function _thread).
+	 * In this case, thread_entry_t, * void *, void * and void * are stored
+	 * in registers a0, a1, a2 and a3. These registers are used as arguments
+	 * to function _thread_entry. Hence, just call _thread_entry with
+	 * return address set to 0 to indicate a non-returning function call.
+	 */
+
+	jal x0, _thread_entry