michaelh/zephyr
1
0
Fork 0
Code Releases Activity

soc: riscv: opentitan: reduce the scope of some definitions

Browse source 
Some definitions were only used in soc.c, there's no need to expose them
in a public header like soc.h.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit is contained in:
Gerard Marull-Paretas 2024-01-16 14:58:08 +01:00 • committed by Fabio Baltieri
commit cce467034f
2 changed files with 15 additions and 18 deletions
Download patch file Download diff file Expand all files Collapse all files

15
soc/riscv/opentitan/soc.c
View file

@ -8,8 +8,23 @@
#include <zephyr/devicetree.h> #include <zephyr/devicetree.h>
#include <zephyr/init.h> #include <zephyr/init.h>
/* OpenTitan power management regs. */
#define PWRMGR_BASE (DT_REG_ADDR(DT_NODELABEL(pwrmgr))) #define PWRMGR_BASE (DT_REG_ADDR(DT_NODELABEL(pwrmgr)))
#define PWRMGR_CFG_CDC_SYNC_REG_OFFSET 0x018
#define PWRMGR_RESET_EN_REG_OFFSET 0x02c
#define PWRMGR_RESET_EN_WDOG_SRC_MASK 0x002
/* Ibex timer registers. */
#define RV_TIMER_BASE (DT_REG_ADDR(DT_NODELABEL(mtimer))) #define RV_TIMER_BASE (DT_REG_ADDR(DT_NODELABEL(mtimer)))
#define RV_TIMER_CTRL_REG_OFFSET 0x004
#define RV_TIMER_INTR_ENABLE_REG_OFFSET 0x100
#define RV_TIMER_CFG0_REG_OFFSET 0x10c
#define RV_TIMER_CFG0_PRESCALE_MASK 0xfff
#define RV_TIMER_CFG0_PRESCALE_OFFSET 0
#define RV_TIMER_CFG0_STEP_MASK 0xff
#define RV_TIMER_CFG0_STEP_OFFSET 16
#define RV_TIMER_LOWER0_OFFSET 0x110
#define RV_TIMER_COMPARE_LOWER0_OFFSET 0x118
static int soc_opentitan_init(void) static int soc_opentitan_init(void)
{ {

18
soc/riscv/opentitan/soc.h
View file

@ -7,22 +7,4 @@
#ifndef __RISCV_OPENTITAN_SOC_H_ #ifndef __RISCV_OPENTITAN_SOC_H_
#define __RISCV_OPENTITAN_SOC_H_ #define __RISCV_OPENTITAN_SOC_H_
#include <zephyr/devicetree.h>
/* OpenTitan power management regs. */
#define PWRMGR_CFG_CDC_SYNC_REG_OFFSET 0x018
#define PWRMGR_RESET_EN_REG_OFFSET 0x02c
#define PWRMGR_RESET_EN_WDOG_SRC_MASK 0x002
/* Ibex timer registers. */
#define RV_TIMER_CTRL_REG_OFFSET 0x004
#define RV_TIMER_INTR_ENABLE_REG_OFFSET 0x100
#define RV_TIMER_CFG0_REG_OFFSET 0x10c
#define RV_TIMER_CFG0_PRESCALE_MASK 0xfff
#define RV_TIMER_CFG0_PRESCALE_OFFSET 0
#define RV_TIMER_CFG0_STEP_MASK 0xff
#define RV_TIMER_CFG0_STEP_OFFSET 16
#define RV_TIMER_LOWER0_OFFSET 0x110
#define RV_TIMER_COMPARE_LOWER0_OFFSET 0x118
#endif /* __RISCV_OPENTITAN_SOC_H_ */ #endif /* __RISCV_OPENTITAN_SOC_H_ */