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arch: arm64: mmu: support using MT_NS attribute

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According to CONFIG_ARMV8_A_NS, using MT_SECURE or MT_NS, to simplify
code change, use MT_DEFAULT_SECURE_STATE instead

Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan 2020-11-21 20:38:09 +08:00 • committed by Anas Nashif
commit cca070c80a
2 changed files with 10 additions and 4 deletions
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8
arch/arm/core/aarch64/mmu/arm_mmu.c
View file

@ -265,7 +265,7 @@ static const struct arm_mmu_region mmu_zephyr_regions[] = {
MMU_REGION_FLAT_ENTRY("SRAM",
(uintptr_t)CONFIG_SRAM_BASE_ADDRESS,
(uintptr_t)KB(CONFIG_SRAM_SIZE),
MT_NORMAL | MT_P_RW_U_NA | MT_SECURE),
MT_NORMAL | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
/* Mark rest of the zephyr execution regions (data, bss, noinit, etc.)
* cacheable, read-write
@ -274,19 +274,19 @@ static const struct arm_mmu_region mmu_zephyr_regions[] = {
MMU_REGION_FLAT_ENTRY("zephyr_data",
(uintptr_t)__kernel_ram_start,
(uintptr_t)__kernel_ram_size,
MT_NORMAL | MT_P_RW_U_NA | MT_SECURE),
MT_NORMAL | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
/* Mark text segment cacheable,read only and executable */
MMU_REGION_FLAT_ENTRY("zephyr_code",
(uintptr_t)_image_text_start,
(uintptr_t)_image_text_size,
MT_NORMAL | MT_P_RX_U_NA | MT_SECURE),
MT_NORMAL | MT_P_RX_U_NA | MT_DEFAULT_SECURE_STATE),
/* Mark rodata segment cacheable, read only and execute-never */
MMU_REGION_FLAT_ENTRY("zephyr_rodata",
(uintptr_t)_image_rodata_start,
(uintptr_t)_image_rodata_size,
MT_NORMAL | MT_P_RO_U_NA | MT_SECURE),
MT_NORMAL | MT_P_RO_U_NA | MT_DEFAULT_SECURE_STATE),
};
static void setup_page_tables(void)

6
include/arch/arm/aarch64/arm_mmu.h
View file

@ -67,6 +67,12 @@
#define MT_P_RX_U_RX (MT_RO | MT_RW_AP_ELx | MT_P_EXECUTE | MT_U_EXECUTE)
#define MT_P_RX_U_NA (MT_RO | MT_RW_AP_EL_HIGHER | MT_P_EXECUTE | MT_U_EXECUTE_NEVER)
#ifdef CONFIG_ARMV8_A_NS
#define MT_DEFAULT_SECURE_STATE MT_NS
#else
#define MT_DEFAULT_SECURE_STATE MT_SECURE
#endif
/*
* PTE descriptor can be Block descriptor or Table descriptor
* or Page descriptor.