soc/intel_adsp: Low level HDA driver and tests
Adds a header only low level driver for HDA streams along with smoke tests to ensure basic host in and out stream functionality. The tests require host side interaction. In cavstool a new HDAStream class encapsulates somewhat a single stream and its registers. This is manipulated in the tests using IPC with the Host ensuring that a specific order of operations is done. This low level driver allows testing certain hardware configurations and flows with easy to use register dump debugging. It is not intended to be the end API an application might use. That would be a DMA driver using this. Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
This commit is contained in:
Tom Burdick
Anas Nashif
parent
345a536794
commit
cc6e9c094a
9 changed files with 764 additions and 7 deletions
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@ -18,7 +18,7 @@ log.setLevel(logging.INFO)
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PAGESZ = 4096
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HUGEPAGESZ = 2 * 1024 * 1024
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HUGEPAGE_FILE = "/dev/hugepages/cavs-fw-dma.tmp"
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HUGEPAGE_FILE = "/dev/hugepages/cavs-fw-dma.tmp."
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# SRAM windows. Each appears in a 128k region starting at 512k.
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#
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@ -30,6 +30,155 @@ OUTBOX_OFFSET = (512 + (0 * 128)) * 1024 + 4096
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INBOX_OFFSET = (512 + (1 * 128)) * 1024
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WINSTREAM_OFFSET = (512 + (3 * 128)) * 1024
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class HDAStream:
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# creates an hda stream with at 2 buffers of buf_len
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def __init__(self, stream_id: int):
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self.stream_id = stream_id
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self.base = hdamem + 0x0080 + (stream_id * 0x20)
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log.info(f"Mapping registers for hda stream {self.stream_id} at base {self.base:x}")
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self.hda = Regs(hdamem)
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self.hda.GCAP = 0x0000
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self.hda.GCTL = 0x0008
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self.hda.DPLBASE = 0x0070
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self.hda.DPUBASE = 0x0074
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self.hda.SPBFCH = 0x0700
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self.hda.SPBFCTL = 0x0704
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self.hda.PPCH = 0x0800
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self.hda.PPCTL = 0x0804
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self.hda.PPSTS = 0x0808
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self.hda.SPIB = 0x0708 + stream_id*0x08
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self.hda.freeze()
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self.regs = Regs(self.base)
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self.regs.CTL = 0x00
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self.regs.STS = 0x03
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self.regs.LPIB = 0x04
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self.regs.CBL = 0x08
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self.regs.LVI = 0x0c
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self.regs.FIFOW = 0x0e
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self.regs.FIFOS = 0x10
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self.regs.FMT = 0x12
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self.regs.FIFOL= 0x14
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self.regs.BDPL = 0x18
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self.regs.BDPU = 0x1c
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self.regs.freeze()
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self.dbg0 = Regs(hdamem + 0x0084 + (0x20*stream_id))
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self.dbg0.DPIB = 0x00
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self.dbg0.EFIFOS = 0x10
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self.dbg0.freeze()
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self.reset()
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def __del__(self):
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self.reset()
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def config(self, buf_len: int):
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log.info(f"Configuring stream {self.stream_id}")
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self.buf_len = buf_len
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log.info("Allocating huge page and setting up buffers")
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self.mem, self.hugef, self.buf_list_addr, self.pos_buf_addr, self.n_bufs = self.setup_buf(buf_len)
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log.info("Setting buffer list, length, and stream id and traffic priority bit")
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self.regs.CTL = ((self.stream_id & 0xFF) << 20) | (1 << 18) # must be set to something other than 0?
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self.regs.BDPU = (self.buf_list_addr >> 32) & 0xffffffff
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self.regs.BDPL = self.buf_list_addr & 0xffffffff
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self.regs.CBL = buf_len
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self.regs.LVI = self.n_bufs - 1
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self.debug()
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log.info(f"Configured stream {self.stream_id}")
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def write(self, data):
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bufl = min(len(data), self.buf_len)
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log.info(f"Writing data to stream {self.stream_id}, len {bufl}, SPBFCTL {self.hda.SPBFCTL:x}, SPIB {self.hda.SPIB}")
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self.mem[0:bufl] = data[0:bufl]
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self.mem[bufl:bufl+bufl] = data[0:bufl]
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self.hda.SPBFCTL |= (1 << self.stream_id)
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self.hda.SPIB += bufl
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log.info(f"Wrote data to stream {self.stream_id}, SPBFCTL {self.hda.SPBFCTL:x}, SPIB {self.hda.SPIB}")
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def start(self):
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log.info(f"Starting stream {self.stream_id}, CTL {self.regs.CTL:x}")
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self.regs.CTL |= 2
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log.info(f"Started stream {self.stream_id}, CTL {self.regs.CTL:x}")
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def stop(self):
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log.info(f"Stopping stream {self.stream_id}, CTL {self.regs.CTL:x}")
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self.regs.CTL &= 2
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time.sleep(0.1)
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self.regs.CTL |= 1
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log.info(f"Stopped stream {self.stream_id}, CTL {self.regs.CTL:x}")
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def setup_buf(self, buf_len: int):
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(mem, phys_addr, hugef) = map_phys_mem(self.stream_id)
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log.info(f"Mapped 2M huge page at 0x{phys_addr:x} for buf size ({buf_len})")
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# create two buffers in the page of buf_len and mark them
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# in a buffer descriptor list for the hardware to use
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buf0_len = buf_len
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buf1_len = buf_len
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bdl_off = buf0_len + buf1_len
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# bdl is 2 (64bits, 16 bytes) per entry, we have two
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mem[bdl_off:bdl_off + 32] = struct.pack("<QQQQ",
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phys_addr,
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buf0_len,
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phys_addr + buf0_len,
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buf1_len)
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dpib_off = bdl_off+32
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# ensure buffer is initialized, sanity
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for i in range(0, buf_len*2):
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mem[i] = 0
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log.info("Filled the buffer descriptor list (BDL) for DMA.")
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return (mem, hugef, phys_addr + bdl_off, phys_addr+dpib_off, 2)
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def debug(self):
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log.info("HDA %d: PPROC %d, CTL 0x%x, LPIB 0x%x, BDPU 0x%x, BDPL 0x%x, CBL 0x%x, LVI 0x%x",
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self.stream_id, (hda.PPCTL >> self.stream_id) & 1, self.regs.CTL, self.regs.LPIB, self.regs.BDPU,
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self.regs.BDPL, self.regs.CBL, self.regs.LVI)
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log.info(" FIFOW %d, FIFOS %d, FMT %x, FIFOL %d, DPIB %d, EFIFOS %d",
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self.regs.FIFOW & 0x7, self.regs.FIFOS, self.regs.FMT, self.regs.FIFOL, self.dbg0.DPIB, self.dbg0.EFIFOS)
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log.info(" status: FIFORDY %d, DESE %d, FIFOE %d, BCIS %d",
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(self.regs.STS >> 5) & 1, (self.regs.STS >> 4) & 1, (self.regs.STS >> 3) & 1, (self.regs.STS >> 2) & 1)
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def reset(self):
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# Turn DMA off and reset the stream. Clearing START first is a
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# noop per the spec, but absolutely required for stability.
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# Apparently the reset doesn't stop the stream, and the next load
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# starts before it's ready and kills the load (and often the DSP).
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# The sleep too is required, on at least one board (a fast
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# chromebook) putting the two writes next each other also hangs
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# the DSP!
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log.info(f"Resetting stream {self.stream_id}")
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self.debug()
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self.regs.CTL &= ~2 # clear START
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time.sleep(0.1)
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# set enter reset bit
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self.regs.CTL = 1
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while (self.regs.CTL & 1) == 0: pass
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# clear enter reset bit to exit reset
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self.regs.CTL = 0
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while (self.regs.CTL & 1) == 1: pass
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log.info(f"Disable SPIB and set position 0 of stream {self.stream_id}")
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self.hda.SPBFCTL = 0
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self.hda.SPIB = 0
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#log.info("Setting dma position buffer and enable it")
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#self.hda.DPUBASE = self.pos_buf_addr >> 32 & 0xffffffff
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#self.hda.DPLBASE = self.pos_buf_addr & 0xfffffff0 | 1
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log.info(f"Enabling dsp capture (PROCEN) of stream {self.stream_id}")
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self.hda.PPCTL |= (1 << self.stream_id)
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self.debug()
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log.info(f"Reset stream {self.stream_id}")
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def map_regs():
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p = runx(f"grep -iPl 'PCI_CLASS=40(10|38)0' /sys/bus/pci/devices/*/uevent")
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pcidir = os.path.dirname(p)
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@ -62,6 +211,7 @@ def map_regs():
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cfg.write(b'\x06\x04')
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# Standard HD Audio Registers
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global hdamem
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(hdamem, _) = bar_map(pcidir, 0)
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hda = Regs(hdamem)
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hda.GCAP = 0x0000
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@ -75,6 +225,7 @@ def map_regs():
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hda.SD_SPIB = 0x0708 + (8 * hda_ostream_id)
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hda.freeze()
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# Standard HD Audio Stream Descriptor
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sd = Regs(hdamem + 0x0080 + (hda_ostream_id * 0x20))
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sd.CTL = 0x00
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@ -101,7 +252,7 @@ def map_regs():
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return (hda, sd, dsp, hda_ostream_id)
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def setup_dma_mem(fw_bytes):
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(mem, phys_addr) = map_phys_mem()
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(mem, phys_addr, _) = map_phys_mem(hda_ostream_id)
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mem[0:len(fw_bytes)] = fw_bytes
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log.info("Mapped 2M huge page at 0x%x to contain %d bytes of firmware"
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@ -124,7 +275,7 @@ global_mmaps = [] # protect mmap mappings from garbage collection!
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# Maps 2M of contiguous memory using a single page from hugetlbfs,
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# then locates its physical address for use as a DMA buffer.
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def map_phys_mem():
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def map_phys_mem(stream_id):
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# Make sure hugetlbfs is mounted (not there on chromeos)
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os.system("mount | grep -q hugetlbfs ||"
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+ " (mkdir -p /dev/hugepages; "
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@ -136,11 +287,13 @@ def map_phys_mem():
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tot = 1 + int(runx("awk '/HugePages_Total/ {print $2}' /proc/meminfo"))
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os.system(f"echo {tot} > /proc/sys/vm/nr_hugepages")
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hugef = open(HUGEPAGE_FILE, "w+")
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hugef_name = HUGEPAGE_FILE + str(stream_id)
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hugef = open(hugef_name, "w+")
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hugef.truncate(HUGEPAGESZ)
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mem = mmap.mmap(hugef.fileno(), HUGEPAGESZ)
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log.info("type of mem is %s", str(type(mem)))
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global_mmaps.append(mem)
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os.unlink(HUGEPAGE_FILE)
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os.unlink(hugef_name)
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# Find the local process address of the mapping, then use that to extract
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# the physical address from the kernel's pagemap interface. The physical
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@ -153,7 +306,7 @@ def map_phys_mem():
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pent = pagemap.read(8)
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paddr = (struct.unpack("Q", pent)[0] & ((1 << 55) - 1)) * PAGESZ
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pagemap.close()
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return (mem, paddr)
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return (mem, paddr, hugef)
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# Maps a PCI BAR and returns the in-process address
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def bar_map(pcidir, barnum):
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@ -337,6 +490,7 @@ ipc_timestamp = 0
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def ipc_command(data, ext_data):
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send_msg = False
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done = True
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log.debug ("ipc data %d, ext_data %x", data, ext_data)
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if data == 0: # noop, with synchronous DONE
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pass
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elif data == 1: # async command: signal DONE after a delay (on 1.8+)
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@ -358,6 +512,45 @@ def ipc_command(data, ext_data):
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dst = INBOX_OFFSET + 4 * (ext_data & 0xffff)
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for i in range(4):
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bar4_mmap[dst + i] = bar4_mmap[src + i]
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elif data == 6: # HDA RESET (init if not exists)
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stream_id = ext_data & 0xff
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if stream_id in hda_streams:
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hda_streams[stream_id].reset()
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else:
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hda_str = HDAStream(stream_id)
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hda_streams[stream_id] = hda_str
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elif data == 7: # HDA CONFIG
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stream_id = ext_data & 0xFF
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buf_len = ext_data >> 8 & 0xFFFF
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hda_str = hda_streams[stream_id]
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hda_str.config(buf_len)
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elif data == 8: # HDA START
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stream_id = ext_data & 0xFF
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hda_streams[stream_id].start()
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elif data == 9: # HDA STOP
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stream_id = ext_data & 0xFF
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hda_streams[stream_id].stop()
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elif data == 10: # HDA VALIDATE
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stream_id = ext_data & 0xFF
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hda_str = hda_streams[stream_id]
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hda_str.debug()
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is_ramp_data = True
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hda_str.mem.seek(0)
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for (i, val) in enumerate(hda_str.mem.read(256)):
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if i != val:
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is_ramp_data = False
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# log.info("stream[%d][%d]: %d", stream_id, i, val) # debug helper
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log.info("Is ramp data? " + str(is_ramp_data))
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ext_data = int(is_ramp_data)
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log.info(f"Ext data to send back on ramp status {ext_data}")
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send_msg = True
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elif data == 11: # HDA HOST OUT SEND
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stream_id = ext_data & 0xff
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buf = bytearray(256)
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for i in range(0, 256):
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buf[i] = i
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hda_streams[stream_id].write(buf)
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else:
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log.warning(f"cavstool: Unrecognized IPC command 0x{data:x} ext 0x{ext_data:x}")
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@ -372,7 +565,8 @@ def ipc_command(data, ext_data):
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dsp.HIPCIDR = (1<<31) | ext_data
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async def main():
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global hda, sd, dsp, hda_ostream_id
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#TODO this bit me, remove the globals, write a little FirmwareLoader class or something to contain.
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global hda, sd, dsp, hda_ostream_id, hda_streams
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try:
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(hda, sd, dsp, hda_ostream_id) = map_regs()
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except Exception as e:
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@ -394,6 +588,7 @@ async def main():
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if not args.quiet:
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sys.stdout.write("--\n")
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hda_streams = dict()
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last_seq = 0
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while True:
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await asyncio.sleep(0.03)
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