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Convert remaining code to using newly introduced integer sized types

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Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.  This handles the remaining includes and kernel, plus
touching up various points that we skipped because of include
dependancies.  We also convert the PRI printf formatters in the arch
code over to normal formatters.

Jira: ZEP-2051

Change-Id: Iecbb12601a3ee4ea936fd7ddea37788a645b08b0
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2017-04-21 10:55:34 -05:00
commit cc334c7273
132 changed files with 1420 additions and 1429 deletions
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29
arch/arm/core/cortex_m/exc_manage.c
View file

@ -15,24 +15,23 @@
#include <misc/printk.h>
void sys_exc_esf_dump(NANO_ESF *esf)
{
printk("r0/a1: %" PRIx32 " ", esf->a1);
printk("r1/a2: %" PRIx32 " ", esf->a2);
printk("r2/a3: %" PRIx32 "\n", esf->a3);
printk("r3/a4: %" PRIx32 " ", esf->a4);
printk("r12/ip: %" PRIx32 " ", esf->ip);
printk("r14/lr: %" PRIx32 "\n", esf->lr);
printk("r15/pc: %" PRIx32 " ", esf->pc);
printk("xpsr: %" PRIx32 "\n", esf->xpsr);
printk("r0/a1: %x ", esf->a1);
printk("r1/a2: %x ", esf->a2);
printk("r2/a3: %x\n", esf->a3);
printk("r3/a4: %x ", esf->a4);
printk("r12/ip: %x ", esf->ip);
printk("r14/lr: %x\n", esf->lr);
printk("r15/pc: %x ", esf->pc);
printk("xpsr: %x\n", esf->xpsr);
#ifdef CONFIG_FLOAT
for (int i = 0; i < 16; i += 4) {
printk("s[%d]: %" PRIx32 " s[%d]: %" PRIx32 " s[%d]: %"
PRIx32 " s[%d]: %" PRIx32 "\n",
i, (uint32_t)esf->s[i],
i + 1, (uint32_t)esf->s[i + 1],
i + 2, (uint32_t)esf->s[i + 2],
i + 3, (uint32_t)esf->s[i + 3]);
printk("s[%d]: %x s[%d]: %x s[%d]: %x s[%d]: %x\n",
i, (u32_t)esf->s[i],
i + 1, (u32_t)esf->s[i + 1],
i + 2, (u32_t)esf->s[i + 2],
i + 3, (u32_t)esf->s[i + 3]);
}
printk("fpscr: %" PRIx32 "\n", esf->fpscr);
printk("fpscr: %x\n", esf->fpscr);
#endif
}

2
arch/arm/core/fatal.c
View file

@ -89,7 +89,7 @@ FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int reason,
break;
}
PR_EXC("Current thread ID = %p\n"
"Faulting instruction address = 0x%" PRIx32 "\n",
"Faulting instruction address = 0x%x\n",
k_current_get(), pEsf->pc);
/*

16
arch/arm/core/fault.c
View file

@ -54,7 +54,7 @@
*/
void _FaultDump(const NANO_ESF *esf, int fault)
{
PR_EXC("Fault! EXC #%d, Thread: %p, instr @ 0x%" PRIx32 "\n",
PR_EXC("Fault! EXC #%d, Thread: %p, instr @ 0x%x\n",
fault,
k_current_get(),
esf->pc);
@ -70,18 +70,18 @@ void _FaultDump(const NANO_ESF *esf, int fault)
: "Bus fault on vector table read\n");
}
PR_EXC("MMFSR: 0x%" PRIx32 ", BFSR: 0x%" PRIx32 ", UFSR: 0x%"
PRIx32 "\n", SCB_MMFSR, SCB_BFSR, SCB_MMFSR);
PR_EXC("MMFSR: 0x%x, BFSR: 0x%x, UFSR: 0x%x\n",
SCB_MMFSR, SCB_BFSR, SCB_MMFSR);
if (SCB->CFSR & CFSR_MMARVALID_Msk) {
PR_EXC("MMFAR: 0x%" PRIx32 "\n", SCB->MMFAR);
PR_EXC("MMFAR: 0x%x\n", SCB->MMFAR);
if (escalation) {
/* clear MMAR[VALID] to reset */
SCB->CFSR &= ~CFSR_MMARVALID_Msk;
}
}
if (SCB->CFSR & CFSR_BFARVALID_Msk) {
PR_EXC("BFAR: 0x%" PRIx32 "\n", SCB->BFAR);
PR_EXC("BFAR: 0x%x\n", SCB->BFAR);
if (escalation) {
/* clear CFSR_BFAR[VALID] to reset */
SCB->CFSR &= ~CFSR_BFARVALID_Msk;
@ -108,7 +108,7 @@ void _FaultDump(const NANO_ESF *esf, int fault)
static void _FaultThreadShow(const NANO_ESF *esf)
{
PR_EXC(" Executing thread ID (thread): %p\n"
" Faulting instruction address: 0x%" PRIx32 "\n",
" Faulting instruction address: 0x%x\n",
k_current_get(), esf->pc);
}
@ -136,7 +136,7 @@ static void _MpuFault(const NANO_ESF *esf, int fromHardFault)
} else if (SCB->CFSR & CFSR_DACCVIOL_Msk) {
PR_EXC(" Data Access Violation\n");
if (SCB->CFSR & CFSR_MMARVALID_Msk) {
PR_EXC(" Address: 0x%" PRIx32 "\n", SCB->MMFAR);
PR_EXC(" Address: 0x%x\n", (u32_t)SCB->MMFAR);
if (fromHardFault) {
/* clear MMAR[VALID] to reset */
SCB->CFSR &= ~CFSR_MMARVALID_Msk;
@ -168,7 +168,7 @@ static void _BusFault(const NANO_ESF *esf, int fromHardFault)
} else if (SCB->CFSR & CFSR_PRECISERR_Msk) {
PR_EXC(" Precise data bus error\n");
if (SCB->CFSR & CFSR_BFARVALID_Msk) {
PR_EXC(" Address: 0x%" PRIx32 "\n", SCB->BFAR);
PR_EXC(" Address: 0x%x\n", (u32_t)SCB->BFAR);
if (fromHardFault) {
/* clear CFSR_BFAR[VALID] to reset */
SCB->CFSR &= ~CFSR_BFARVALID_Msk;

2
arch/arm/core/irq_manage.c
View file

@ -82,7 +82,7 @@ int _arch_irq_is_enabled(unsigned int irq)
*
* @return N/A
*/
void _irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
void _irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags)
{
/* Hardware priority levels 0 and 1 reserved for Kernel use.
* So we add 2 to the requested priority level. If we support