mxrt685: Add USDHC support for RT685

Add USDHC support for RT685

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>

boards/arm/mimxrt685_evk/Kconfig.defconfig

@@ -38,4 +38,7 @@ config HEAP_MEM_POOL_SIZE
 
 endif # DMA_MCUX_LPC
 
+config DISK_DRIVER_SDMMC
+	default y if DISK_DRIVERS
+
 endif # BOARD_MIMXRT685_EVK

boards/arm/mimxrt685_evk/doc/index.rst

@@ -91,6 +91,8 @@ features:
 +-----------+------------+-------------------------------------+
 | WDT       | on-chip    | watchdog                            |
 +-----------+------------+-------------------------------------+
+| SDHC      | on-chip    | disk access                         |
++-----------+------------+-------------------------------------+
 
 The default configuration can be found in the defconfig file:
 
@@ -165,6 +167,24 @@ functionality of a pin.
 +---------+-----------------+----------------------------+
 | PIO0_27 | SCT0_OUT7       | PWM                        |
 +---------+-----------------+----------------------------+
+| PIO1_30 | SD0_CLK         | SD card                    |
++---------+-----------------+----------------------------+
+| PIO1_31 | SD0_CMD         | SD card                    |
++---------+-----------------+----------------------------+
+| PIO2_0  | SD0_D0          | SD card                    |
++---------+-----------------+----------------------------+
+| PIO2_1  | SD0_D1          | SD card                    |
++---------+-----------------+----------------------------+
+| PIO2_2  | SD0_D2          | SD card                    |
++---------+-----------------+----------------------------+
+| PIO2_3  | SD0_D3          | SD card                    |
++---------+-----------------+----------------------------+
+| PIO2_4  | SD0_WR_PRT      | SD card                    |
++---------+-----------------+----------------------------+
+| PIO2_9  | SD0_CD          | SD card                    |
++---------+-----------------+----------------------------+
+| PIO2_10 | SD0_RST         | SD card                    |
++---------+-----------------+----------------------------+
 
 System Clock
 ============

boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.dts

@@ -253,6 +253,10 @@ i2s1: &flexcomm3 {
 	status = "okay";
 };
 
+&gpio2 {
+	status = "okay";
+};
+
 &dma0 {
 	/*
 	 * The total number of dma channels available is defined by
@@ -293,3 +297,8 @@ i2s1: &flexcomm3 {
 &sc_timer {
 	status = "okay";
 };
+
+&usdhc1 {
+	status = "okay";
+	pwr-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
+};

boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.yaml

@@ -25,5 +25,6 @@ supported:
   - hwinfo
   - i2c
   - i2s
+  - sdhc
   - spi
   - watchdog

boards/arm/mimxrt685_evk/pinmux.c

@@ -768,6 +768,197 @@ static int mimxrt685_evk_pinmux_init(const struct device *dev)
 	IOPCTL_PinMuxSet(IOPCTL, 0U, 31U, port0_pin31_config);
 #endif
 
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
+	uint32_t port1_pin30_config = (/* Pin is configured as SD0_CLK */
+		IOPCTL_PIO_FUNC1 |
+		/* Disable pull-up / pull-down function */
+		IOPCTL_PIO_PUPD_DI |
+		/* Enable pull-down function */
+		IOPCTL_PIO_PULLDOWN_EN |
+		/* Enables input buffer function */
+		IOPCTL_PIO_INBUF_EN |
+		/* Normal mode */
+		IOPCTL_PIO_SLEW_RATE_NORMAL |
+		/* Normal drive */
+		IOPCTL_PIO_FULLDRIVE_DI |
+		/* Analog mux is disabled */
+		IOPCTL_PIO_ANAMUX_DI |
+		/* Pseudo Output Drain is disabled */
+		IOPCTL_PIO_PSEDRAIN_DI |
+		/* Input function is not inverted */
+		IOPCTL_PIO_INV_DI);
+	/* PORT1 PIN30 (coords: P10) is configured as SD0_CLK */
+	IOPCTL_PinMuxSet(IOPCTL, 1U, 30U, port1_pin30_config);
+
+	uint32_t port1_pin31_config = (/* Pin is configured as SD0_CMD */
+		IOPCTL_PIO_FUNC1 |
+		/* Enable pull-up / pull-down function */
+		IOPCTL_PIO_PUPD_EN |
+		/* Enable pull-up function */
+		IOPCTL_PIO_PULLUP_EN |
+		/* Enables input buffer function */
+		IOPCTL_PIO_INBUF_EN |
+		/* Normal mode */
+		IOPCTL_PIO_SLEW_RATE_NORMAL |
+		/* Normal drive */
+		IOPCTL_PIO_FULLDRIVE_DI |
+		/* Analog mux is disabled */
+		IOPCTL_PIO_ANAMUX_DI |
+		/* Pseudo Output Drain is disabled */
+		IOPCTL_PIO_PSEDRAIN_DI |
+		/* Input function is not inverted */
+		IOPCTL_PIO_INV_DI);
+	/* PORT1 PIN31 (coords: R9) is configured as SD0_CMD */
+	IOPCTL_PinMuxSet(IOPCTL, 1U, 31U, port1_pin31_config);
+
+	uint32_t port2_pin0_config = (/* Pin is configured as SD0_D0 */
+		IOPCTL_PIO_FUNC1 |
+		/* Enable pull-up / pull-down function */
+		IOPCTL_PIO_PUPD_EN |
+		/* Enable pull-up function */
+		IOPCTL_PIO_PULLUP_EN |
+		/* Enables input buffer function */
+		IOPCTL_PIO_INBUF_EN |
+		/* Normal mode */
+		IOPCTL_PIO_SLEW_RATE_NORMAL |
+		/* Normal drive */
+		IOPCTL_PIO_FULLDRIVE_DI |
+		/* Analog mux is disabled */
+		IOPCTL_PIO_ANAMUX_DI |
+		/* Pseudo Output Drain is disabled */
+		IOPCTL_PIO_PSEDRAIN_DI |
+		/* Input function is not inverted */
+		IOPCTL_PIO_INV_DI);
+	/* PORT2 PIN0 (coords: R11) is configured as SD0_D0 */
+	IOPCTL_PinMuxSet(IOPCTL, 2U, 0U, port2_pin0_config);
+
+	uint32_t port2_pin1_config = (/* Pin is configured as SD0_D1 */
+		IOPCTL_PIO_FUNC1 |
+		/* Enable pull-up / pull-down function */
+		IOPCTL_PIO_PUPD_EN |
+		/* Enable pull-up function */
+		IOPCTL_PIO_PULLUP_EN |
+		/* Enables input buffer function */
+		IOPCTL_PIO_INBUF_EN |
+		/* Normal mode */
+		IOPCTL_PIO_SLEW_RATE_NORMAL |
+		/* Normal drive */
+		IOPCTL_PIO_FULLDRIVE_DI |
+		/* Analog mux is disabled */
+		IOPCTL_PIO_ANAMUX_DI |
+		/* Pseudo Output Drain is disabled */
+		IOPCTL_PIO_PSEDRAIN_DI |
+		/* Input function is not inverted */
+		IOPCTL_PIO_INV_DI);
+	/* PORT2 PIN1 (coords: T11) is configured as SD0_D1 */
+	IOPCTL_PinMuxSet(IOPCTL, 2U, 1U, port2_pin1_config);
+
+	uint32_t port2_pin10_config = (/* Pin is configured as PIO2_10 */
+		IOPCTL_PIO_FUNC0 |
+		/* Disable pull-up / pull-down function */
+		IOPCTL_PIO_PUPD_DI |
+		/* Enable pull-down function */
+		IOPCTL_PIO_PULLDOWN_EN |
+		/* Disable input buffer function */
+		IOPCTL_PIO_INBUF_DI |
+		/* Normal mode */
+		IOPCTL_PIO_SLEW_RATE_NORMAL |
+		/* Normal drive */
+		IOPCTL_PIO_FULLDRIVE_DI |
+		/* Analog mux is disabled */
+		IOPCTL_PIO_ANAMUX_DI |
+		/* Pseudo Output Drain is disabled */
+		IOPCTL_PIO_PSEDRAIN_DI |
+		/* Input function is not inverted */
+		IOPCTL_PIO_INV_DI);
+	/* PORT2 PIN10 (coords: T15) is configured as PIO2_10 */
+	IOPCTL_PinMuxSet(IOPCTL, 2U, 10U, port2_pin10_config);
+
+	uint32_t port2_pin2_config = (/* Pin is configured as SD0_D2 */
+		IOPCTL_PIO_FUNC1 |
+		/* Enable pull-up / pull-down function */
+		IOPCTL_PIO_PUPD_EN |
+		/* Enable pull-up function */
+		IOPCTL_PIO_PULLUP_EN |
+		/* Enables input buffer function */
+		IOPCTL_PIO_INBUF_EN |
+		/* Normal mode */
+		IOPCTL_PIO_SLEW_RATE_NORMAL |
+		/* Normal drive */
+		IOPCTL_PIO_FULLDRIVE_DI |
+		/* Analog mux is disabled */
+		IOPCTL_PIO_ANAMUX_DI |
+		/* Pseudo Output Drain is disabled */
+		IOPCTL_PIO_PSEDRAIN_DI |
+		/* Input function is not inverted */
+		IOPCTL_PIO_INV_DI);
+	/* PORT2 PIN2 (coords: U11) is configured as SD0_D2 */
+	IOPCTL_PinMuxSet(IOPCTL, 2U, 2U, port2_pin2_config);
+
+	uint32_t port2_pin3_config = (/* Pin is configured as SD0_D3 */
+		IOPCTL_PIO_FUNC1 |
+		/* Enable pull-up / pull-down function */
+		IOPCTL_PIO_PUPD_EN |
+		/* Enable pull-up function */
+		IOPCTL_PIO_PULLUP_EN |
+		/* Enables input buffer function */
+		IOPCTL_PIO_INBUF_EN |
+		/* Normal mode */
+		IOPCTL_PIO_SLEW_RATE_NORMAL |
+		/* Normal drive */
+		IOPCTL_PIO_FULLDRIVE_DI |
+		/* Analog mux is disabled */
+		IOPCTL_PIO_ANAMUX_DI |
+		/* Pseudo Output Drain is disabled */
+		IOPCTL_PIO_PSEDRAIN_DI |
+		/* Input function is not inverted */
+		IOPCTL_PIO_INV_DI);
+	/* PORT2 PIN3 (coords: T12) is configured as SD0_D3 */
+	IOPCTL_PinMuxSet(IOPCTL, 2U, 3U, port2_pin3_config);
+
+	uint32_t port2_pin4_config = (/* Pin is configured as PIO2_4 */
+		IOPCTL_PIO_FUNC0 |
+		/* Disable pull-up / pull-down function */
+		IOPCTL_PIO_PUPD_DI |
+		/* Enable pull-down function */
+		IOPCTL_PIO_PULLDOWN_EN |
+		/* Disable input buffer function */
+		IOPCTL_PIO_INBUF_DI |
+		/* Normal mode */
+		IOPCTL_PIO_SLEW_RATE_NORMAL |
+		/* Normal drive */
+		IOPCTL_PIO_FULLDRIVE_DI |
+		/* Analog mux is disabled */
+		IOPCTL_PIO_ANAMUX_DI |
+		/* Pseudo Output Drain is disabled */
+		IOPCTL_PIO_PSEDRAIN_DI |
+		/* Input function is not inverted */
+		IOPCTL_PIO_INV_DI);
+	/* PORT2 PIN4 (coords: T13) is configured as PIO2_4 */
+	IOPCTL_PinMuxSet(IOPCTL, 2U, 4U, port2_pin4_config);
+
+	uint32_t port2_pin9_config = (/* Pin is configured as SD0_CARD_DET_N */
+		IOPCTL_PIO_FUNC1 |
+		/* Enable pull-up / pull-down function */
+		IOPCTL_PIO_PUPD_EN |
+		/* Enable pull-up function */
+		IOPCTL_PIO_PULLUP_EN |
+		/* Enables input buffer function */
+		IOPCTL_PIO_INBUF_EN |
+		/* Normal mode */
+		IOPCTL_PIO_SLEW_RATE_NORMAL |
+		/* Normal drive */
+		IOPCTL_PIO_FULLDRIVE_DI |
+		/* Analog mux is disabled */
+		IOPCTL_PIO_ANAMUX_DI |
+		/* Pseudo Output Drain is disabled */
+		IOPCTL_PIO_PSEDRAIN_DI |
+		/* Input function is not inverted */
+		IOPCTL_PIO_INV_DI);
+	/* PORT2 PIN9 (coords: R13) is configured as SD0_CARD_DET_N */
+	IOPCTL_PinMuxSet(IOPCTL, 2U, 9U, port2_pin9_config);
 #endif
 
 	return 0;

dts/arm/nxp/nxp_rt6xx_common.dtsi

@@ -277,6 +277,24 @@
 		clk-divider = <1>;
 		label = "WWDT_1";
 	};
+
+	usdhc1: usdhc@136000 {
+		compatible = "nxp,imx-usdhc";
+		reg = <0x136000 0x4000>;
+		status = "disabled";
+		interrupts = <45 0>;
+		clocks = <&clkctl1 MCUX_USDHC1_CLK>;
+		label = "USDHC_1";
+	};
+
+	usdhc2: usdhc@137000 {
+		compatible = "nxp,imx-usdhc";
+		reg = <0x137000 0x4000>;
+		status = "disabled";
+		interrupts = <46 0>;
+		clocks = <&clkctl1 MCUX_USDHC2_CLK>;
+		label = "USDHC_2";
+	};
 };
 
 &nvic {

soc/arm/nxp_imx/rt6xx/Kconfig.soc

@@ -25,6 +25,8 @@ config SOC_MIMXRT685S_CM33
 	select HAS_MCUX_LPC_RTC
 	select HAS_MCUX_TRNG
 	select HAS_MCUX_SCTIMER
+	select HAS_MCUX_USDHC1
+	select HAS_MCUX_USDHC2
 	select INIT_SYS_PLL
 
 endchoice

soc/arm/nxp_imx/rt6xx/soc.c

@@ -171,6 +171,7 @@ static ALWAYS_INLINE void clock_init(void)
 	/* attach AUDIO PLL clock to FLEXCOMM3 (I2S3) */
 	CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM3);
 #endif
+
 #if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(wwdt0), nxp_lpc_wwdt, okay))
 	CLOCK_AttachClk(kLPOSC_to_WDT0_CLK);
 #else
@@ -179,9 +180,34 @@ static ALWAYS_INLINE void clock_init(void)
 	 */
 	CLOCK_AttachClk(kNONE_to_WDT0_CLK);
 #endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
+	/* Make sure USDHC ram buffer has been power up*/
+	POWER_DisablePD(kPDRUNCFG_APD_USDHC0_SRAM);
+	POWER_DisablePD(kPDRUNCFG_PPD_USDHC0_SRAM);
+	POWER_DisablePD(kPDRUNCFG_PD_LPOSC);
+	POWER_ApplyPD();
+
+	/* usdhc depend on 32K clock also */
+	CLOCK_AttachClk(kLPOSC_DIV32_to_32KHZWAKE_CLK);
+	CLOCK_AttachClk(kAUX0_PLL_to_SDIO0_CLK);
+	CLOCK_SetClkDiv(kCLOCK_DivSdio0Clk, 1);
+	CLOCK_EnableClock(kCLOCK_Sdio0);
+	RESET_PeripheralReset(kSDIO0_RST_SHIFT_RSTn);
+#endif
+
 #endif /* CONFIG_SOC_MIMXRT685S_CM33 */
 }
 
+#if (DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC)
+
+void imxrt_usdhc_pinmux(uint16_t nusdhc, bool init,
+	uint32_t speed, uint32_t strength)
+{
+
+}
+#endif
+
 /**
  *
  * @brief Perform basic hardware initialization

soc/arm/nxp_imx/rt6xx/soc.h

@@ -75,4 +75,21 @@
 /*!<@brief Slow mode */
 #define IOPCTL_PIO_SLEW_RATE_SLOW 0x80u
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if CONFIG_DISK_DRIVER_SDMMC &&					\
+	(DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) ||	\
+	 DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc2), okay))
+
+void imxrt_usdhc_pinmux(uint16_t nusdhc,
+	bool init, uint32_t speed, uint32_t strength);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif /* _SOC__H_ */