From cbcf36e1a7afe7ef26680be535b498f519a3e6df Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Fri, 7 Feb 2025 08:02:37 +0900 Subject: [PATCH] dts: arm: renesas: ra: Remove old R7FA4M1AB3CFM configurations Due to historical reasons, there were two implementations of R7FA4M1AB3CFM. However, the migration has been completed, so the old one is now being removed. Signed-off-by: TOKITA Hiroshi --- drivers/gpio/CMakeLists.txt | 1 - drivers/gpio/Kconfig | 1 - drivers/gpio/Kconfig.renesas_ra | 11 - drivers/gpio/gpio_renesas_ra.c | 435 ----------- drivers/interrupt_controller/CMakeLists.txt | 1 - drivers/interrupt_controller/Kconfig | 2 - .../interrupt_controller/Kconfig.renesas_ra | 10 - .../intc_renesas_ra_icu.c | 124 --- drivers/pinctrl/renesas/ra/pinctrl_ra.c | 13 - drivers/serial/CMakeLists.txt | 1 - drivers/serial/Kconfig.renesas_ra | 10 - drivers/serial/uart_renesas_ra.c | 733 ------------------ dts/arm/renesas/ra/r7fa4m1ab3cfm.dtsi | 11 - dts/arm/renesas/ra/ra-cm4-common.dtsi | 355 --------- dts/arm/renesas/ra/ra4-cm4-common.dtsi | 65 -- dts/arm/renesas/ra/ra4/r7fa4m1ab3cfm.dtsi | 16 +- dts/arm/renesas/ra/ra4/r7fa4m1ab3cfp.dtsi | 16 +- dts/bindings/gpio/renesas,ra-gpio.yaml | 83 -- .../renesas,ra-interrupt-controller-unit.yaml | 20 - dts/bindings/serial/renesas,ra-uart-sci.yaml | 8 - .../interrupt_controller/intc_ra_icu.h | 42 - .../dt-bindings/clock/r7fa4m1xxxxxx-clock.h | 12 - .../interrupt-controller/renesas-ra-icu.h | 193 ----- .../pinctrl/renesas/pinctrl-ra-common.h | 46 -- soc/renesas/ra/common_fsp/pinctrl_soc.h | 2 - 25 files changed, 16 insertions(+), 2195 deletions(-) delete mode 100644 drivers/gpio/Kconfig.renesas_ra delete mode 100644 drivers/gpio/gpio_renesas_ra.c delete mode 100644 drivers/interrupt_controller/Kconfig.renesas_ra delete mode 100644 drivers/interrupt_controller/intc_renesas_ra_icu.c delete mode 100644 drivers/serial/uart_renesas_ra.c delete mode 100644 dts/arm/renesas/ra/r7fa4m1ab3cfm.dtsi delete mode 100644 dts/arm/renesas/ra/ra-cm4-common.dtsi delete mode 100644 dts/arm/renesas/ra/ra4-cm4-common.dtsi delete mode 100644 dts/bindings/gpio/renesas,ra-gpio.yaml delete mode 100644 dts/bindings/interrupt-controller/renesas,ra-interrupt-controller-unit.yaml delete mode 100644 dts/bindings/serial/renesas,ra-uart-sci.yaml delete mode 100644 include/zephyr/drivers/interrupt_controller/intc_ra_icu.h delete mode 100644 include/zephyr/dt-bindings/clock/r7fa4m1xxxxxx-clock.h delete mode 100644 include/zephyr/dt-bindings/interrupt-controller/renesas-ra-icu.h delete mode 100644 include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra-common.h diff --git a/drivers/gpio/CMakeLists.txt b/drivers/gpio/CMakeLists.txt index 6ed5384f03d..9a5bf207935 100644 --- a/drivers/gpio/CMakeLists.txt +++ b/drivers/gpio/CMakeLists.txt @@ -80,7 +80,6 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_PCF857X gpio_pcf857x.c) zephyr_library_sources_ifdef(CONFIG_GPIO_PSOC6 gpio_psoc6.c) zephyr_library_sources_ifdef(CONFIG_GPIO_RA_IOPORT gpio_renesas_ra_ioport.c) zephyr_library_sources_ifdef(CONFIG_GPIO_RCAR gpio_rcar.c) -zephyr_library_sources_ifdef(CONFIG_GPIO_RENESAS_RA gpio_renesas_ra.c) zephyr_library_sources_ifdef(CONFIG_GPIO_RENESAS_RZ gpio_renesas_rz.c) zephyr_library_sources_ifdef(CONFIG_GPIO_RP1 gpio_rp1.c) zephyr_library_sources_ifdef(CONFIG_GPIO_RPI_PICO gpio_rpi_pico.c) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 1b8e33ad78e..00aab689e11 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -165,7 +165,6 @@ source "drivers/gpio/Kconfig.pcal64xxa" source "drivers/gpio/Kconfig.pcf857x" source "drivers/gpio/Kconfig.psoc6" source "drivers/gpio/Kconfig.rcar" -source "drivers/gpio/Kconfig.renesas_ra" source "drivers/gpio/Kconfig.renesas_ra_ioport" source "drivers/gpio/Kconfig.renesas_rz" source "drivers/gpio/Kconfig.rp1" diff --git a/drivers/gpio/Kconfig.renesas_ra b/drivers/gpio/Kconfig.renesas_ra deleted file mode 100644 index 2f6fb3c38c4..00000000000 --- a/drivers/gpio/Kconfig.renesas_ra +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config GPIO_RENESAS_RA - bool "Renesas RA Series GPIO driver" - default y - select GPIO_GET_CONFIG - select PINCTRL - depends on DT_HAS_RENESAS_RA_GPIO_ENABLED - help - Enable Renesas RA series GPIO driver. diff --git a/drivers/gpio/gpio_renesas_ra.c b/drivers/gpio/gpio_renesas_ra.c deleted file mode 100644 index 69bb67c18d5..00000000000 --- a/drivers/gpio/gpio_renesas_ra.c +++ /dev/null @@ -1,435 +0,0 @@ -/* - * Copyright (c) 2023 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT renesas_ra_gpio - -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -enum { - PCNTR1_OFFSET = 0x0, - PCNTR2_OFFSET = 0x4, - PCNTR3_OFFSET = 0x8, - PCNTR4_OFFSET = 0xc -}; - -enum { - PCNTR1_PDR0_OFFSET = 0, - PCNTR1_PODR0_OFFSET = 16, -}; - -enum { - PCNTR2_PIDR0_OFFSET = 0, - PCNTR2_EIDR0_OFFSET = 16, -}; - -enum { - PCNTR3_POSR0_OFFSET = 0, - PCNTR3_PORR0_OFFSET = 16, -}; - -enum { - PCNTR4_EOSR0_OFFSET = 0, - PCNTR4_EORR0_OFFSET = 16, -}; - -struct gpio_ra_irq_info { - const uint8_t *const pins; - size_t num; - int port_irq; - int irq; - uint32_t priority; - uint32_t flags; - ra_isr_handler isr; -}; - -struct gpio_ra_pin_irq_info { - const struct gpio_ra_irq_info *info; - uint8_t pin; -}; - -struct gpio_ra_config { - struct gpio_driver_config common; - mem_addr_t regs; - struct gpio_ra_irq_info *irq_info; - uint32_t irq_info_size; - uint16_t port; -}; - -struct gpio_ra_data { - struct gpio_driver_data common; - struct gpio_ra_pin_irq_info port_irq_info[16]; - sys_slist_t callbacks; -}; - -static inline uint32_t gpio_ra_irq_info_event(const struct gpio_ra_irq_info *info) -{ - return ((info->flags & RA_ICU_FLAG_EVENT_MASK) >> RA_ICU_FLAG_EVENT_OFFSET); -} - -static void gpio_ra_isr(const struct device *dev, uint32_t port_irq) -{ - struct gpio_ra_data *data = dev->data; - const struct gpio_ra_pin_irq_info *pin_irq = &data->port_irq_info[port_irq]; - const int irq = ra_icu_query_exists_irq(gpio_ra_irq_info_event(pin_irq->info)); - - if (irq >= 0) { - gpio_fire_callbacks(&data->callbacks, dev, BIT(pin_irq->pin)); - ra_icu_clear_int_flag(irq); - } -} - -static const struct gpio_ra_irq_info *query_irq_info(const struct device *dev, uint32_t pin) -{ - const struct gpio_ra_config *config = dev->config; - - for (int i = 0; i < config->irq_info_size; i++) { - const struct gpio_ra_irq_info *info = &config->irq_info[i]; - - for (int j = 0; j < info->num; j++) { - if (info->pins[j] == pin) { - return info; - } - } - } - - return NULL; -} - -static inline uint32_t reg_read(const struct device *dev, size_t offset) -{ - const struct gpio_ra_config *config = dev->config; - - return sys_read32(config->regs + offset); -} - -static inline void reg_write(const struct device *dev, size_t offset, uint32_t value) -{ - const struct gpio_ra_config *config = dev->config; - - sys_write32(value, config->regs + offset); -} - -static inline uint32_t port_read(const struct device *dev) -{ - return reg_read(dev, PCNTR2_OFFSET) & UINT16_MAX; -} - -static int port_write(const struct device *dev, uint16_t value, uint16_t mask) -{ - const uint16_t set = value & mask; - const uint16_t clr = (~value) & mask; - - reg_write(dev, PCNTR3_OFFSET, (clr << PCNTR3_PORR0_OFFSET) | set << PCNTR3_POSR0_OFFSET); - - return 0; -} - -static int gpio_ra_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) -{ - const enum gpio_int_mode mode = - flags & (GPIO_INT_EDGE | GPIO_INT_DISABLE | GPIO_INT_ENABLE); - const enum gpio_int_trig trig = flags & (GPIO_INT_LOW_0 | GPIO_INT_HIGH_1); - const struct gpio_ra_config *config = dev->config; - struct gpio_ra_data *data = dev->data; - struct ra_pinctrl_soc_pin pincfg = {0}; - - if ((flags & GPIO_OUTPUT) && (flags & GPIO_INPUT)) { - /* Pin cannot be configured as input and output */ - return -ENOTSUP; - } else if (!(flags & (GPIO_INPUT | GPIO_OUTPUT))) { - /* Pin has to be configured as input or output */ - return -ENOTSUP; - } - - if (flags & GPIO_OUTPUT) { - pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_PDR_Pos); - } - - if (flags & GPIO_PULL_UP) { - pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_PCR_Pos); - } - - if ((flags & GPIO_SINGLE_ENDED) && (flags & GPIO_LINE_OPEN_DRAIN)) { - pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_NCODR_Pos); - } - - if (flags & GPIO_INT_ENABLE) { - pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_ISEL_Pos); - } - - pincfg.cfg &= ~BIT(R_PFS_PORT_PIN_PmnPFS_PMR_Pos); - - pincfg.pin_num = pin; - pincfg.port_num = config->port; - - if (flags & GPIO_INT_ENABLE) { - const struct gpio_ra_irq_info *irq_info; - uint32_t intcfg; - int irqn; - - if (mode == GPIO_INT_MODE_LEVEL) { - if (trig != GPIO_INT_TRIG_LOW) { - return -ENOTSUP; - } - - intcfg = ICU_LOW_LEVEL; - } else if (mode == GPIO_INT_MODE_EDGE) { - switch (trig) { - case GPIO_INT_TRIG_LOW: - intcfg = ICU_FALLING; - break; - case GPIO_INT_TRIG_HIGH: - intcfg = ICU_RISING; - break; - case GPIO_INT_TRIG_BOTH: - intcfg = ICU_BOTH_EDGE; - break; - default: - return -ENOTSUP; - } - } else { - return -ENOTSUP; - } - - irq_info = query_irq_info(dev, pin); - if (irq_info == NULL) { - return -EINVAL; - } - - irqn = ra_icu_irq_connect_dynamic( - irq_info->irq, irq_info->priority, irq_info->isr, dev, - (intcfg << RA_ICU_FLAG_INTCFG_OFFSET) | irq_info->flags); - if (irqn < 0) { - return irqn; - } - - data->port_irq_info[irq_info->port_irq].pin = pin; - data->port_irq_info[irq_info->port_irq].info = irq_info; - - irq_enable(irqn); - } - - return pinctrl_configure_pins(&pincfg, 1, PINCTRL_REG_NONE); -} - -#ifdef CONFIG_GPIO_GET_CONFIG -static int gpio_ra_pin_get_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t *flags) -{ - const struct gpio_ra_config *config = dev->config; - const struct gpio_ra_irq_info *irq_info; - struct ra_pinctrl_soc_pin pincfg; - ra_isr_handler cb; - const void *cbarg; - uint32_t intcfg; - int irqn; - int err; - - memset(flags, 0, sizeof(gpio_flags_t)); - - err = ra_pinctrl_query_config(config->port, pin, &pincfg); - if (err < 0) { - return err; - } - - if (pincfg.cfg & BIT(R_PFS_PORT_PIN_PmnPFS_PDR_Pos)) { - *flags |= GPIO_OUTPUT; - } else { - *flags |= GPIO_INPUT; - } - - if (pincfg.cfg & BIT(R_PFS_PORT_PIN_PmnPFS_ISEL_Pos)) { - *flags |= GPIO_INT_ENABLE; - } - - if (pincfg.cfg & BIT(R_PFS_PORT_PIN_PmnPFS_PCR_Pos)) { - *flags |= GPIO_PULL_UP; - } - - irq_info = query_irq_info(dev, pin); - if (irq_info == NULL) { - return 0; - } - - irqn = ra_icu_query_exists_irq(gpio_ra_irq_info_event(irq_info)); - if (irqn < 0) { - return 0; - } - - ra_icu_query_irq_config(irqn, &intcfg, &cb, &cbarg); - - if (cbarg != dev) { - return 0; - } - - if (intcfg == ICU_FALLING) { - *flags |= GPIO_INT_TRIG_LOW; - *flags |= GPIO_INT_MODE_EDGE; - } else if (intcfg == ICU_RISING) { - *flags |= GPIO_INT_TRIG_HIGH; - *flags |= GPIO_INT_MODE_EDGE; - } else if (intcfg == ICU_BOTH_EDGE) { - *flags |= GPIO_INT_TRIG_BOTH; - *flags |= GPIO_INT_MODE_EDGE; - } else if (intcfg == ICU_LOW_LEVEL) { - *flags |= GPIO_INT_TRIG_LOW; - *flags |= GPIO_INT_MODE_LEVEL; - } - - return 0; -} -#endif - -static int gpio_ra_port_get_raw(const struct device *dev, gpio_port_value_t *value) -{ - *value = port_read(dev); - - return 0; -} - -static int gpio_ra_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask, - gpio_port_value_t value) -{ - uint16_t port_val; - - port_val = port_read(dev); - port_val = (port_val & ~mask) | (value & mask); - return port_write(dev, port_val, UINT16_MAX); -} - -static int gpio_ra_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins) -{ - uint16_t port_val; - - port_val = port_read(dev); - port_val |= pins; - return port_write(dev, port_val, UINT16_MAX); -} - -static int gpio_ra_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins) -{ - uint16_t port_val; - - port_val = port_read(dev); - port_val &= ~pins; - return port_write(dev, port_val, UINT16_MAX); -} - -static int gpio_ra_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins) -{ - uint16_t port_val; - - port_val = port_read(dev); - port_val ^= pins; - return port_write(dev, port_val, UINT16_MAX); -} - -static int gpio_ra_manage_callback(const struct device *dev, struct gpio_callback *callback, - bool set) -{ - struct gpio_ra_data *data = dev->data; - - return gpio_manage_callback(&data->callbacks, callback, set); -} - -static int gpio_ra_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin, - enum gpio_int_mode mode, enum gpio_int_trig trig) -{ - gpio_flags_t pincfg; - int err; - - err = gpio_ra_pin_get_config(dev, pin, &pincfg); - if (err < 0) { - return err; - } - - return gpio_ra_pin_configure(dev, pin, pincfg | mode | trig); -} - -static DEVICE_API(gpio, gpio_ra_driver_api) = { - .pin_configure = gpio_ra_pin_configure, -#ifdef CONFIG_GPIO_GET_CONFIG - .pin_get_config = gpio_ra_pin_get_config, -#endif - .port_get_raw = gpio_ra_port_get_raw, - .port_set_masked_raw = gpio_ra_port_set_masked_raw, - .port_set_bits_raw = gpio_ra_port_set_bits_raw, - .port_clear_bits_raw = gpio_ra_port_clear_bits_raw, - .port_toggle_bits = gpio_ra_port_toggle_bits, - .pin_interrupt_configure = gpio_ra_pin_interrupt_configure, - .manage_callback = gpio_ra_manage_callback, -}; - -#define RA_NUM_PORT_IRQ0 0 -#define RA_NUM_PORT_IRQ1 1 -#define RA_NUM_PORT_IRQ2 2 -#define RA_NUM_PORT_IRQ3 3 -#define RA_NUM_PORT_IRQ4 4 -#define RA_NUM_PORT_IRQ5 5 -#define RA_NUM_PORT_IRQ6 6 -#define RA_NUM_PORT_IRQ7 7 -#define RA_NUM_PORT_IRQ8 8 -#define RA_NUM_PORT_IRQ9 9 -#define RA_NUM_PORT_IRQ10 10 -#define RA_NUM_PORT_IRQ11 11 -#define RA_NUM_PORT_IRQ12 12 -#define RA_NUM_PORT_IRQ13 13 -#define RA_NUM_PORT_IRQ14 14 -#define RA_NUM_PORT_IRQ15 15 - -#define GPIO_RA_DECL_PINS(n, p, i) \ - const uint8_t _CONCAT(n, ___pins##i[]) = {DT_FOREACH_PROP_ELEM_SEP( \ - n, _CONCAT(DT_STRING_TOKEN_BY_IDX(n, p, i), _pins), DT_PROP_BY_IDX, (,))}; - -#define GPIO_RA_IRQ_INFO(n, p, i) \ - { \ - .port_irq = _CONCAT(RA_NUM_, DT_STRING_UPPER_TOKEN_BY_IDX(n, p, i)), \ - .irq = DT_IRQ_BY_IDX(n, i, irq), \ - .flags = DT_IRQ_BY_IDX(n, i, flags), \ - .priority = DT_IRQ_BY_IDX(n, i, priority), \ - .pins = _CONCAT(n, ___pins##i), \ - .num = ARRAY_SIZE(_CONCAT(n, ___pins##i)), \ - .isr = _CONCAT(n, _CONCAT(gpio_ra_isr_, DT_STRING_TOKEN_BY_IDX(n, p, i))), \ - }, - -#define GPIO_RA_ISR_DECL(n, p, i) \ - static void _CONCAT(n, _CONCAT(gpio_ra_isr_, DT_STRING_TOKEN_BY_IDX(n, p, i)))( \ - const void *arg) \ - { \ - gpio_ra_isr((const struct device *)arg, \ - _CONCAT(RA_NUM_, DT_STRING_UPPER_TOKEN_BY_IDX(n, p, i))); \ - } - -#define GPIO_RA_INIT(idx) \ - static struct gpio_ra_data gpio_ra_data_##idx = {}; \ - DT_INST_FOREACH_PROP_ELEM(idx, interrupt_names, GPIO_RA_DECL_PINS); \ - DT_INST_FOREACH_PROP_ELEM(idx, interrupt_names, GPIO_RA_ISR_DECL); \ - struct gpio_ra_irq_info gpio_ra_irq_info_##idx[] = { \ - DT_INST_FOREACH_PROP_ELEM(idx, interrupt_names, GPIO_RA_IRQ_INFO)}; \ - static struct gpio_ra_config gpio_ra_config_##idx = { \ - .common = { \ - .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx), \ - }, \ - .regs = DT_INST_REG_ADDR(idx), \ - .port = (DT_INST_REG_ADDR(idx) - DT_REG_ADDR(DT_NODELABEL(ioport0))) / \ - DT_INST_REG_SIZE(idx), \ - .irq_info = gpio_ra_irq_info_##idx, \ - .irq_info_size = ARRAY_SIZE(gpio_ra_irq_info_##idx), \ - }; \ - \ - DEVICE_DT_INST_DEFINE(idx, NULL, NULL, &gpio_ra_data_##idx, &gpio_ra_config_##idx, \ - PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, &gpio_ra_driver_api); - -DT_INST_FOREACH_STATUS_OKAY(GPIO_RA_INIT) diff --git a/drivers/interrupt_controller/CMakeLists.txt b/drivers/interrupt_controller/CMakeLists.txt index 8f3b279eda6..a825f7af787 100644 --- a/drivers/interrupt_controller/CMakeLists.txt +++ b/drivers/interrupt_controller/CMakeLists.txt @@ -40,7 +40,6 @@ zephyr_library_sources_ifdef(CONFIG_NXP_S32_EIRQ intc_eirq_nxp_s32.c) zephyr_library_sources_ifdef(CONFIG_NXP_S32_WKPU intc_wkpu_nxp_s32.c) zephyr_library_sources_ifdef(CONFIG_XMC4XXX_INTC intc_xmc4xxx.c) zephyr_library_sources_ifdef(CONFIG_NXP_PINT intc_nxp_pint.c) -zephyr_library_sources_ifdef(CONFIG_RENESAS_RA_ICU intc_renesas_ra_icu.c) zephyr_library_sources_ifdef(CONFIG_RENESAS_RZ_EXT_IRQ intc_renesas_rz_ext_irq.c) zephyr_library_sources_ifdef(CONFIG_NXP_IRQSTEER intc_nxp_irqsteer.c) zephyr_library_sources_ifdef(CONFIG_INTC_MTK_ADSP intc_mtk_adsp.c) diff --git a/drivers/interrupt_controller/Kconfig b/drivers/interrupt_controller/Kconfig index 388bfd2eb9f..84bc1f54181 100644 --- a/drivers/interrupt_controller/Kconfig +++ b/drivers/interrupt_controller/Kconfig @@ -102,8 +102,6 @@ source "drivers/interrupt_controller/Kconfig.nxp_pint" source "drivers/interrupt_controller/Kconfig.vim" -source "drivers/interrupt_controller/Kconfig.renesas_ra" - source "drivers/interrupt_controller/Kconfig.renesas_rz" source "drivers/interrupt_controller/Kconfig.nxp_irqsteer" diff --git a/drivers/interrupt_controller/Kconfig.renesas_ra b/drivers/interrupt_controller/Kconfig.renesas_ra deleted file mode 100644 index 45cb171d26d..00000000000 --- a/drivers/interrupt_controller/Kconfig.renesas_ra +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config RENESAS_RA_ICU - bool "Renesas RA series interrupt controller unit" - default y - depends on DT_HAS_RENESAS_RA_INTERRUPT_CONTROLLER_UNIT_ENABLED - select GEN_ISR_TABLES - help - Renesas RA series interrupt controller unit diff --git a/drivers/interrupt_controller/intc_renesas_ra_icu.c b/drivers/interrupt_controller/intc_renesas_ra_icu.c deleted file mode 100644 index 57b9ac731ab..00000000000 --- a/drivers/interrupt_controller/intc_renesas_ra_icu.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright (c) 2023 TOKITTA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT renesas_ra_interrupt_controller_unit - -#include -#include -#include -#include -#include -#include - -#define IELSRn_REG(n) (DT_INST_REG_ADDR(0) + IELSRn_OFFSET + (n * 4)) -#define IRQCRi_REG(i) (DT_INST_REG_ADDR(0) + IRQCRi_OFFSET + (i)) - -#define IRQCRi_IRQMD_POS 0 -#define IRQCRi_IRQMD_MASK BIT_MASK(2) -#define IELSRn_IR_POS 16 -#define IELSRn_IR_MASK BIT_MASK(1) - -enum { - IRQCRi_OFFSET = 0x0, - IELSRn_OFFSET = 0x300, -}; - -int ra_icu_query_exists_irq(uint32_t event) -{ - for (uint32_t i = 0; i < CONFIG_NUM_IRQS; i++) { - uint32_t els = sys_read32(IELSRn_REG(i)) & UINT8_MAX; - - if (event == els) { - return i; - } - } - - return -EINVAL; -} - -int ra_icu_query_available_irq(uint32_t event) -{ - int irq = -EINVAL; - - if (ra_icu_query_exists_irq(event) > 0) { - return -EINVAL; - } - - for (uint32_t i = 0; i < CONFIG_NUM_IRQS; i++) { - if (_sw_isr_table[i].isr == z_irq_spurious) { - irq = i; - break; - } - } - - return irq; -} - -void ra_icu_clear_int_flag(unsigned int irqn) -{ - uint32_t cfg = sys_read32(IELSRn_REG(irqn)); - - sys_write32(cfg & ~BIT(IELSRn_IR_POS), IELSRn_REG(irqn)); -} - -void ra_icu_query_irq_config(unsigned int irq, uint32_t *intcfg, ra_isr_handler *cb, - const void **cbarg) -{ - *intcfg = sys_read32(IELSRn_REG(irq)); - *cb = _sw_isr_table[irq].isr; - *cbarg = (void *)_sw_isr_table[irq].arg; -} - -static void ra_icu_irq_configure(unsigned int irqn, uint32_t intcfg) -{ - uint8_t reg = sys_read8(IRQCRi_REG(irqn)) & ~(IRQCRi_IRQMD_MASK); - - sys_write8(reg | (intcfg & IRQCRi_IRQMD_MASK), IRQCRi_REG(irqn)); -} - -int ra_icu_irq_connect_dynamic(unsigned int irq, unsigned int priority, - void (*routine)(const void *parameter), const void *parameter, - uint32_t flags) -{ - uint32_t event = ((flags & RA_ICU_FLAG_EVENT_MASK) >> RA_ICU_FLAG_EVENT_OFFSET); - uint32_t intcfg = ((flags & RA_ICU_FLAG_INTCFG_MASK) >> RA_ICU_FLAG_INTCFG_OFFSET); - int irqn = irq; - - if (irq == RA_ICU_IRQ_UNSPECIFIED) { - irqn = ra_icu_query_available_irq(event); - if (irqn < 0) { - return irqn; - } - } - - irq_disable(irqn); - sys_write32(event, IELSRn_REG(irqn)); - z_isr_install(irqn, routine, parameter); - z_arm_irq_priority_set(irqn, priority, flags); - ra_icu_irq_configure(event, intcfg); - - return irqn; -} - -int ra_icu_irq_disconnect_dynamic(unsigned int irq, unsigned int priority, - void (*routine)(const void *parameter), const void *parameter, - uint32_t flags) -{ - int irqn = irq; - - if (irq == RA_ICU_IRQ_UNSPECIFIED) { - return -EINVAL; - } - - irq_disable(irqn); - sys_write32(0, IELSRn_REG(irqn)); - z_isr_install(irqn, z_irq_spurious, NULL); - z_arm_irq_priority_set(irqn, 0, 0); - - return 0; -} - -DEVICE_DT_INST_DEFINE(0, NULL, NULL, NULL, NULL, PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY, NULL); diff --git a/drivers/pinctrl/renesas/ra/pinctrl_ra.c b/drivers/pinctrl/renesas/ra/pinctrl_ra.c index 0f2bc85bd60..efaac2f34f7 100644 --- a/drivers/pinctrl/renesas/ra/pinctrl_ra.c +++ b/drivers/pinctrl/renesas/ra/pinctrl_ra.c @@ -26,16 +26,3 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp return 0; } - -int ra_pinctrl_query_config(uint32_t port, uint32_t pin, pinctrl_soc_pin_t *pincfg) -{ - if (port >= RA_PINCTRL_PORT_NUM || pin >= RA_PINCTRL_PIN_NUM) { - return -EINVAL; - } - - pincfg->port_num = port; - pincfg->pin_num = pin; - - pincfg->cfg = R_PFS->PORT[port].PIN[pin].PmnPFS; - return 0; -} diff --git a/drivers/serial/CMakeLists.txt b/drivers/serial/CMakeLists.txt index 1b01128c0c9..a026598687f 100644 --- a/drivers/serial/CMakeLists.txt +++ b/drivers/serial/CMakeLists.txt @@ -61,7 +61,6 @@ zephyr_library_sources_ifdef(CONFIG_UART_PSOC6 uart_psoc6.c) zephyr_library_sources_ifdef(CONFIG_UART_QUICKLOGIC_USBSERIALPORT_S3B uart_ql_usbserialport_s3b.c) zephyr_library_sources_ifdef(CONFIG_UART_RA8_SCI_B uart_renesas_ra8_sci_b.c) zephyr_library_sources_ifdef(CONFIG_UART_RCAR uart_rcar.c) -zephyr_library_sources_ifdef(CONFIG_UART_RENESAS_RA uart_renesas_ra.c) zephyr_library_sources_ifdef(CONFIG_UART_RENESAS_RZ_SCI uart_renesas_rz_sci.c) zephyr_library_sources_ifdef(CONFIG_UART_RENESAS_RZ_SCIF uart_renesas_rz_scif.c) zephyr_library_sources_ifdef(CONFIG_UART_RPI_PICO_PIO uart_rpi_pico_pio.c) diff --git a/drivers/serial/Kconfig.renesas_ra b/drivers/serial/Kconfig.renesas_ra index d79081bc506..20c399c0c66 100644 --- a/drivers/serial/Kconfig.renesas_ra +++ b/drivers/serial/Kconfig.renesas_ra @@ -2,16 +2,6 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -config UART_RENESAS_RA - bool "Renesas RA Series UART Driver" - default y - depends on DT_HAS_RENESAS_RA_UART_SCI_ENABLED - select SERIAL_HAS_DRIVER - select SERIAL_SUPPORT_INTERRUPT - select PINCTRL - help - Enable Renesas RA series UART driver. - config UART_SCI_RA bool "Renesas RA SCI UART" default y diff --git a/drivers/serial/uart_renesas_ra.c b/drivers/serial/uart_renesas_ra.c deleted file mode 100644 index 60758db553b..00000000000 --- a/drivers/serial/uart_renesas_ra.c +++ /dev/null @@ -1,733 +0,0 @@ -/* - * Copyright (c) 2023 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT renesas_ra_uart_sci - -#include -#include -#include -#include -#include -#include -#include - -#include - -LOG_MODULE_REGISTER(ra_uart_sci, CONFIG_UART_LOG_LEVEL); - -enum { - UART_RA_INT_RXI, - UART_RA_INT_TXI, - UART_RA_INT_ERI, - NUM_OF_UART_RA_INT, -}; - -struct uart_ra_cfg { - mem_addr_t regs; - const struct device *clock_dev; - const struct clock_control_ra_subsys_cfg clock_id; - const struct pinctrl_dev_config *pcfg; -#ifdef CONFIG_UART_INTERRUPT_DRIVEN - int (*irq_config_func)(const struct device *dev); -#endif -}; - -struct uart_ra_data { - struct uart_config current_config; - uint32_t clk_rate; - struct k_spinlock lock; -#ifdef CONFIG_UART_INTERRUPT_DRIVEN - uint32_t irqn[NUM_OF_UART_RA_INT]; - uart_irq_callback_user_data_t callback; - void *cb_data; -#endif -}; - -#define REG_MASK(reg) (BIT_MASK(_CONCAT(reg, _LEN)) << _CONCAT(reg, _POS)) - -/* Registers */ -#define SMR 0x00 /*!< Serial Mode Register */ -#define BRR 0x01 /*!< Bit Rate Register */ -#define SCR 0x02 /*!< Serial Control Register */ -#define TDR 0x03 /*!< Transmit Data Register */ -#define SSR 0x04 /*!< Serial Status Register */ -#define RDR 0x05 /*!< Receive Data Register */ -#define SEMR 0x07 /*!< Serial Extended Mode Register */ -#define MDDR 0x12 /*!< Modulation Duty Register */ -#define LSR 0x18 /*!< Line Status Register */ - -/* - * SMR (Serial Mode Register) - * - * - CKS[0..2]: Clock Select - * - MP[2..3]: Multi-Processor Mode(Valid only in asynchronous mode) - * - STOP[3..4]: Stop Bit Length(Valid only in asynchronous mode) - * - PM[4..5]: Parity Mode (Valid only when the PE bit is 1) - * - PE[5..6]: Parity Enable(Valid only in asynchronous mode) - * - CHR[6..7]: Character Length(Valid only in asynchronous mode) - * - CM[7..8]: Communication Mode - */ -#define SMR_CKS_POS (0) -#define SMR_CKS_LEN (2) -#define SMR_MP_POS (2) -#define SMR_MP_LEN (1) -#define SMR_STOP_POS (3) -#define SMR_STOP_LEN (1) -#define SMR_PM_POS (4) -#define SMR_PM_LEN (1) -#define SMR_PE_POS (5) -#define SMR_PE_LEN (1) -#define SMR_CHR_POS (6) -#define SMR_CHR_LEN (1) -#define SMR_CM_POS (7) -#define SMR_CM_LEN (1) - -/** - * SCR (Serial Control Register) - * - * - CKE[0..2]: Clock Enable - * - TEIE[2..3]: Transmit End Interrupt Enable - * - MPIE[3..4]: Multi-Processor Interrupt Enable (Valid in asynchronous - * - RE[4..5]: Receive Enable - * - TE[5..6]: Transmit Enable - * - RIE[6..7]: Receive Interrupt Enable - * - TIE[7..8]: Transmit Interrupt Enable - */ -#define SCR_CKE_POS (0) -#define SCR_CKE_LEN (2) -#define SCR_TEIE_POS (2) -#define SCR_TEIE_LEN (1) -#define SCR_MPIE_POS (3) -#define SCR_MPIE_LEN (1) -#define SCR_RE_POS (4) -#define SCR_RE_LEN (1) -#define SCR_TE_POS (5) -#define SCR_TE_LEN (1) -#define SCR_RIE_POS (6) -#define SCR_RIE_LEN (1) -#define SCR_TIE_POS (7) -#define SCR_TIE_LEN (1) - -/** - * SSR (Serial Status Register) - * - * - MPBT[0..1]: Multi-Processor Bit Transfer - * - MPB[1..2]: Multi-Processor - * - TEND[2..3]: Transmit End Flag - * - PER[3..4]: Parity Error Flag - * - FER[4..5]: Framing Error Flag - * - ORER[5..6]: Overrun Error Flag - * - RDRF[6..7]: Receive Data Full Flag - * - TDRE[7..8]: Transmit Data Empty Flag - */ -#define SSR_MPBT_POS (0) -#define SSR_MPBT_LEN (1) -#define SSR_MPB_POS (1) -#define SSR_MPB_LEN (1) -#define SSR_TEND_POS (2) -#define SSR_TEND_LEN (1) -#define SSR_PER_POS (3) -#define SSR_PER_LEN (1) -#define SSR_FER_POS (4) -#define SSR_FER_LEN (1) -#define SSR_ORER_POS (5) -#define SSR_ORER_LEN (1) -#define SSR_RDRF_POS (6) -#define SSR_RDRF_LEN (1) -#define SSR_TDRE_POS (7) -#define SSR_TDRE_LEN (1) - -/** - * SEMR (Serial Extended Mode Register) - * - * - ACS0[0..1]: Asynchronous Mode Clock Source Select - * - PADIS[1..2]: Preamble function Disable - * - BRME[2..3]: Bit Rate Modulation Enable - * - ABCSE[3..4]: Asynchronous Mode Extended Base Clock Select - * - ABCS[4..5]: Asynchronous Mode Base Clock Select - * - NFEN[5..6]: Digital Noise Filter Function Enable - * - BGDM[6..7]: Baud Rate Generator Double-Speed Mode Select - * - RXDESEL[7..8]: Asynchronous Start Bit Edge Detection Select - */ -#define SEMR_ACS0_POS (0) -#define SEMR_ACS0_LEN (1) -#define SEMR_PADIS_POS (1) -#define SEMR_PADIS_LEN (1) -#define SEMR_BRME_POS (2) -#define SEMR_BRME_LEN (1) -#define SEMR_ABCSE_POS (3) -#define SEMR_ABCSE_LEN (1) -#define SEMR_ABCS_POS (4) -#define SEMR_ABCS_LEN (1) -#define SEMR_NFEN_POS (5) -#define SEMR_NFEN_LEN (1) -#define SEMR_BGDM_POS (6) -#define SEMR_BGDM_LEN (1) -#define SEMR_RXDESEL_POS (7) -#define SEMR_RXDESEL_LEN (1) - -/** - * LSR (Line Status Register) - * - * - ORER[0..1]: Overrun Error Flag - * - FNUM[2..7]: Framing Error Count - * - PNUM[8..13]: Parity Error Count - */ -#define LSR_ORER_POS (0) -#define LSR_ORER_LEN (1) -#define LSR_FNUM_POS (2) -#define LSR_FNUM_LEN (5) -#define LSR_PNUM_POS (8) -#define LSR_PNUM_LEN (5) - -static uint8_t uart_ra_read_8(const struct device *dev, uint32_t offs) -{ - const struct uart_ra_cfg *config = dev->config; - - return sys_read8(config->regs + offs); -} - -static void uart_ra_write_8(const struct device *dev, uint32_t offs, uint8_t value) -{ - const struct uart_ra_cfg *config = dev->config; - - sys_write8(value, config->regs + offs); -} - -static uint16_t uart_ra_read_16(const struct device *dev, uint32_t offs) -{ - const struct uart_ra_cfg *config = dev->config; - - return sys_read16(config->regs + offs); -} - -static void uart_ra_write_16(const struct device *dev, uint32_t offs, uint16_t value) -{ - const struct uart_ra_cfg *config = dev->config; - - sys_write16(value, config->regs + offs); -} - -static void uart_ra_set_baudrate(const struct device *dev, uint32_t baud_rate) -{ - struct uart_ra_data *data = dev->data; - uint8_t reg_val; - - reg_val = uart_ra_read_8(dev, SEMR); - reg_val |= (REG_MASK(SEMR_BGDM) | REG_MASK(SEMR_ABCS)); - reg_val &= ~(REG_MASK(SEMR_BRME) | REG_MASK(SEMR_ABCSE)); - uart_ra_write_8(dev, SEMR, reg_val); - - reg_val = (data->clk_rate / (8 * data->current_config.baudrate)) - 1; - uart_ra_write_8(dev, BRR, reg_val); -} - -static int uart_ra_poll_in(const struct device *dev, unsigned char *p_char) -{ - struct uart_ra_data *data = dev->data; - int ret = 0; - - k_spinlock_key_t key = k_spin_lock(&data->lock); - - /* If interrupts are enabled, return -EINVAL */ - if ((uart_ra_read_8(dev, SCR) & REG_MASK(SCR_RIE))) { - ret = -EINVAL; - goto unlock; - } - - if ((uart_ra_read_8(dev, SSR) & REG_MASK(SSR_RDRF)) == 0) { - ret = -1; - goto unlock; - } - - *p_char = uart_ra_read_8(dev, RDR); -unlock: - k_spin_unlock(&data->lock, key); - - return ret; -} - -static void uart_ra_poll_out(const struct device *dev, unsigned char out_char) -{ - struct uart_ra_data *data = dev->data; - uint8_t reg_val; - k_spinlock_key_t key = k_spin_lock(&data->lock); - - while (!(uart_ra_read_8(dev, SSR) & REG_MASK(SSR_TEND)) || - !(uart_ra_read_8(dev, SSR) & REG_MASK(SSR_TDRE))) { - ; - } - - /* If interrupts are enabled, temporarily disable them */ - reg_val = uart_ra_read_8(dev, SCR); - uart_ra_write_8(dev, SCR, reg_val & ~REG_MASK(SCR_TIE)); - - uart_ra_write_8(dev, TDR, out_char); - while (!(uart_ra_read_8(dev, SSR) & REG_MASK(SSR_TEND)) || - !(uart_ra_read_8(dev, SSR) & REG_MASK(SSR_TDRE))) { - ; - } - - uart_ra_write_8(dev, SCR, reg_val); - k_spin_unlock(&data->lock, key); -} - -static int uart_ra_err_check(const struct device *dev) -{ - struct uart_ra_data *data = dev->data; - - uint8_t reg_val; - int errors = 0; - k_spinlock_key_t key; - - key = k_spin_lock(&data->lock); - reg_val = uart_ra_read_8(dev, SSR); - - if (reg_val & REG_MASK(SSR_PER)) { - errors |= UART_ERROR_PARITY; - } - - if (reg_val & REG_MASK(SSR_FER)) { - errors |= UART_ERROR_FRAMING; - } - - if (reg_val & REG_MASK(SSR_ORER)) { - errors |= UART_ERROR_OVERRUN; - } - - reg_val &= ~(REG_MASK(SSR_PER) | REG_MASK(SSR_FER) | REG_MASK(SSR_ORER)); - uart_ra_write_8(dev, SSR, reg_val); - - k_spin_unlock(&data->lock, key); - - return errors; -} - -static int uart_ra_configure(const struct device *dev, const struct uart_config *cfg) -{ - struct uart_ra_data *data = dev->data; - - uint16_t reg_val; - k_spinlock_key_t key; - - if (cfg->parity != UART_CFG_PARITY_NONE || cfg->stop_bits != UART_CFG_STOP_BITS_1 || - cfg->data_bits != UART_CFG_DATA_BITS_8 || cfg->flow_ctrl != UART_CFG_FLOW_CTRL_NONE) { - return -ENOTSUP; - } - - key = k_spin_lock(&data->lock); - - /* Disable Transmit and Receive */ - reg_val = uart_ra_read_8(dev, SCR); - reg_val &= ~(REG_MASK(SCR_TE) | REG_MASK(SCR_RE)); - uart_ra_write_8(dev, SCR, reg_val); - - /* Resetting Errors Registers */ - reg_val = uart_ra_read_8(dev, SSR); - reg_val &= ~(REG_MASK(SSR_PER) | REG_MASK(SSR_FER) | REG_MASK(SSR_ORER) | - REG_MASK(SSR_RDRF) | REG_MASK(SSR_TDRE)); - uart_ra_write_8(dev, SSR, reg_val); - - reg_val = uart_ra_read_16(dev, LSR); - reg_val &= ~(REG_MASK(LSR_ORER)); - uart_ra_write_16(dev, LSR, reg_val); - - /* Select internal clock */ - reg_val = uart_ra_read_8(dev, SCR); - reg_val &= ~(REG_MASK(SCR_CKE)); - uart_ra_write_8(dev, SCR, reg_val); - - /* Serial Configuration (8N1) & Clock divider selection */ - reg_val = uart_ra_read_8(dev, SMR); - reg_val &= ~(REG_MASK(SMR_CM) | REG_MASK(SMR_CHR) | REG_MASK(SMR_PE) | REG_MASK(SMR_PM) | - REG_MASK(SMR_STOP) | REG_MASK(SMR_CKS)); - uart_ra_write_8(dev, SMR, reg_val); - - /* Set baudrate */ - uart_ra_set_baudrate(dev, cfg->baudrate); - - /* Enable Transmit & Receive + disable Interrupts */ - reg_val = uart_ra_read_8(dev, SCR); - reg_val |= (REG_MASK(SCR_TE) | REG_MASK(SCR_RE)); - reg_val &= - ~(REG_MASK(SCR_TIE) | REG_MASK(SCR_RIE) | REG_MASK(SCR_MPIE) | REG_MASK(SCR_TEIE)); - uart_ra_write_8(dev, SCR, reg_val); - - data->current_config = *cfg; - - k_spin_unlock(&data->lock, key); - - return 0; -} - -#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE -static int uart_ra_config_get(const struct device *dev, struct uart_config *cfg) -{ - struct uart_ra_data *data = dev->data; - - *cfg = data->current_config; - - return 0; -} -#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */ - -static int uart_ra_init(const struct device *dev) -{ - const struct uart_ra_cfg *config = dev->config; - struct uart_ra_data *data = dev->data; - int ret; - - /* Configure dt provided device signals when available */ - ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); - if (ret < 0) { - return ret; - } - - if (!device_is_ready(config->clock_dev)) { - return -ENODEV; - } - - ret = clock_control_on(config->clock_dev, (clock_control_subsys_t)&config->clock_id); - if (ret < 0) { - return ret; - } - - ret = clock_control_get_rate(config->clock_dev, (clock_control_subsys_t)&config->clock_id, - &data->clk_rate); - if (ret < 0) { - return ret; - } - - ret = uart_ra_configure(dev, &data->current_config); - if (ret != 0) { - return ret; - } - -#ifdef CONFIG_UART_INTERRUPT_DRIVEN - ret = config->irq_config_func(dev); - if (ret != 0) { - return ret; - } -#endif - - return 0; -} - -#ifdef CONFIG_UART_INTERRUPT_DRIVEN - -static bool uart_ra_irq_is_enabled(const struct device *dev, uint32_t irq) -{ - return uart_ra_read_8(dev, SCR) & irq; -} - -static int uart_ra_fifo_fill(const struct device *dev, const uint8_t *tx_data, int len) -{ - struct uart_ra_data *data = dev->data; - uint8_t reg_val; - k_spinlock_key_t key; - - if (len <= 0 || tx_data == NULL) { - return 0; - } - - key = k_spin_lock(&data->lock); - reg_val = uart_ra_read_8(dev, SCR); - reg_val &= ~(REG_MASK(SCR_TIE)); - uart_ra_write_8(dev, SCR, reg_val); - - uart_ra_write_8(dev, TDR, tx_data[0]); - - reg_val |= REG_MASK(SCR_TIE); - uart_ra_write_8(dev, SCR, reg_val); - - k_spin_unlock(&data->lock, key); - - return 1; -} - -static int uart_ra_fifo_read(const struct device *dev, uint8_t *rx_data, const int size) -{ - uint8_t data; - - if (size <= 0) { - return 0; - } - - if ((uart_ra_read_8(dev, SSR) & REG_MASK(SSR_RDRF)) == 0) { - return 0; - } - - data = uart_ra_read_8(dev, RDR); - - if (rx_data) { - rx_data[0] = data; - } - - return 1; -} - -static void uart_ra_irq_tx_enable(const struct device *dev) -{ - struct uart_ra_data *data = dev->data; - k_spinlock_key_t key; - uint16_t reg_val; - - key = k_spin_lock(&data->lock); - - reg_val = uart_ra_read_8(dev, SCR); - reg_val |= (REG_MASK(SCR_TIE)); - uart_ra_write_8(dev, SCR, reg_val); - - irq_enable(data->irqn[UART_RA_INT_TXI]); - - k_spin_unlock(&data->lock, key); -} - -static void uart_ra_irq_tx_disable(const struct device *dev) -{ - struct uart_ra_data *data = dev->data; - k_spinlock_key_t key; - uint16_t reg_val; - - key = k_spin_lock(&data->lock); - - reg_val = uart_ra_read_8(dev, SCR); - reg_val &= ~(REG_MASK(SCR_TIE)); - uart_ra_write_8(dev, SCR, reg_val); - - irq_disable(data->irqn[UART_RA_INT_TXI]); - - k_spin_unlock(&data->lock, key); -} - -static int uart_ra_irq_tx_ready(const struct device *dev) -{ - const uint8_t reg_val = uart_ra_read_8(dev, SSR); - const uint8_t mask = REG_MASK(SSR_TEND) & REG_MASK(SSR_TDRE); - - return (reg_val & mask) == mask; -} - -static void uart_ra_irq_rx_enable(const struct device *dev) -{ - struct uart_ra_data *data = dev->data; - k_spinlock_key_t key; - uint16_t reg_val; - - key = k_spin_lock(&data->lock); - - reg_val = uart_ra_read_8(dev, SCR); - reg_val |= REG_MASK(SCR_RIE); - uart_ra_write_8(dev, SCR, reg_val); - - irq_enable(data->irqn[UART_RA_INT_RXI]); - - k_spin_unlock(&data->lock, key); -} - -static void uart_ra_irq_rx_disable(const struct device *dev) -{ - struct uart_ra_data *data = dev->data; - k_spinlock_key_t key; - uint16_t reg_val; - - key = k_spin_lock(&data->lock); - - reg_val = uart_ra_read_8(dev, SCR); - reg_val &= ~REG_MASK(SCR_RIE); - uart_ra_write_8(dev, SCR, reg_val); - - irq_disable(data->irqn[UART_RA_INT_RXI]); - - k_spin_unlock(&data->lock, key); -} - -static int uart_ra_irq_rx_ready(const struct device *dev) -{ - return !!(uart_ra_read_8(dev, SSR) & REG_MASK(SSR_RDRF)); -} - -static void uart_ra_irq_err_enable(const struct device *dev) -{ - struct uart_ra_data *data = dev->data; - - irq_enable(data->irqn[UART_RA_INT_ERI]); -} - -static void uart_ra_irq_err_disable(const struct device *dev) -{ - struct uart_ra_data *data = dev->data; - - irq_disable(data->irqn[UART_RA_INT_ERI]); -} - -static int uart_ra_irq_is_pending(const struct device *dev) -{ - return (uart_ra_irq_rx_ready(dev) && uart_ra_irq_is_enabled(dev, REG_MASK(SCR_RIE))) || - (uart_ra_irq_tx_ready(dev) && uart_ra_irq_is_enabled(dev, REG_MASK(SCR_TIE))); -} - -static int uart_ra_irq_update(const struct device *dev) -{ - return 1; -} - -static void uart_ra_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb, - void *cb_data) -{ - struct uart_ra_data *data = dev->data; - - data->callback = cb; - data->cb_data = cb_data; -} - -/** - * @brief Interrupt service routine. - * - * This simply calls the callback function, if one exists. - * - * @param arg Argument to ISR. - */ -static inline void uart_ra_isr(const struct device *dev) -{ - struct uart_ra_data *data = dev->data; - - if (data->callback) { - data->callback(dev, data->cb_data); - } -} - -static void uart_ra_isr_rxi(const void *param) -{ - const struct device *dev = param; - struct uart_ra_data *data = dev->data; - - uart_ra_isr(dev); - ra_icu_clear_int_flag(data->irqn[UART_RA_INT_RXI]); -} - -static void uart_ra_isr_txi(const void *param) -{ - const struct device *dev = param; - struct uart_ra_data *data = dev->data; - - uart_ra_isr(dev); - ra_icu_clear_int_flag(data->irqn[UART_RA_INT_TXI]); -} - -static void uart_ra_isr_eri(const void *param) -{ - const struct device *dev = param; - struct uart_ra_data *data = dev->data; - - uart_ra_isr(dev); - ra_icu_clear_int_flag(data->irqn[UART_RA_INT_ERI]); -} - -#endif /* CONFIG_UART_INTERRUPT_DRIVEN */ - -static DEVICE_API(uart, uart_ra_driver_api) = { - .poll_in = uart_ra_poll_in, - .poll_out = uart_ra_poll_out, - .err_check = uart_ra_err_check, -#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE - .configure = uart_ra_configure, - .config_get = uart_ra_config_get, -#endif -#ifdef CONFIG_UART_INTERRUPT_DRIVEN - .fifo_fill = uart_ra_fifo_fill, - .fifo_read = uart_ra_fifo_read, - .irq_tx_enable = uart_ra_irq_tx_enable, - .irq_tx_disable = uart_ra_irq_tx_disable, - .irq_tx_ready = uart_ra_irq_tx_ready, - .irq_rx_enable = uart_ra_irq_rx_enable, - .irq_rx_disable = uart_ra_irq_rx_disable, - .irq_rx_ready = uart_ra_irq_rx_ready, - .irq_err_enable = uart_ra_irq_err_enable, - .irq_err_disable = uart_ra_irq_err_disable, - .irq_is_pending = uart_ra_irq_is_pending, - .irq_update = uart_ra_irq_update, - .irq_callback_set = uart_ra_irq_callback_set, -#endif /* CONFIG_UART_INTERRUPT_DRIVEN */ -}; - -/* Device Instantiation */ -#define UART_RA_INIT_CFG(n) \ - PINCTRL_DT_DEFINE(DT_INST_PARENT(n)); \ - static const struct uart_ra_cfg uart_ra_cfg_##n = { \ - .regs = DT_REG_ADDR(DT_INST_PARENT(n)), \ - .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(n))), \ - .clock_id = \ - { \ - .mstp = DT_CLOCKS_CELL_BY_IDX(DT_INST_PARENT(n), 0, mstp), \ - .stop_bit = DT_CLOCKS_CELL_BY_IDX(DT_INST_PARENT(n), 0, stop_bit), \ - }, \ - .pcfg = PINCTRL_DT_DEV_CONFIG_GET(DT_INST_PARENT(n)), \ - IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, \ - (.irq_config_func = irq_config_func_##n,))} - -#ifdef CONFIG_UART_INTERRUPT_DRIVEN - -#define RA_IRQ_CONNECT_DYNAMIC(n, name, dev, isr) \ - ra_icu_irq_connect_dynamic(DT_IRQ_BY_NAME(DT_INST_PARENT(n), name, irq), \ - DT_IRQ_BY_NAME(DT_INST_PARENT(n), name, priority), isr, dev, \ - DT_IRQ_BY_NAME(DT_INST_PARENT(n), name, flags)); - -#define RA_IRQ_DISCONNECT_DYNAMIC(n, name, dev, isr) \ - ra_icu_irq_disconnect_dynamic(irqn, 0, NULL, NULL, 0) - -#define UART_RA_CONFIG_FUNC(n) \ - static int irq_config_func_##n(const struct device *dev) \ - { \ - struct uart_ra_data *data = dev->data; \ - int irqn; \ - \ - irqn = RA_IRQ_CONNECT_DYNAMIC(n, rxi, dev, uart_ra_isr_rxi); \ - if (irqn < 0) { \ - return irqn; \ - } \ - data->irqn[UART_RA_INT_RXI] = irqn; \ - irqn = RA_IRQ_CONNECT_DYNAMIC(n, txi, dev, uart_ra_isr_txi); \ - if (irqn < 0) { \ - goto err_txi; \ - } \ - data->irqn[UART_RA_INT_TXI] = irqn; \ - irqn = RA_IRQ_CONNECT_DYNAMIC(n, eri, dev, uart_ra_isr_eri); \ - if (irqn < 0) { \ - goto err_eri; \ - } \ - data->irqn[UART_RA_INT_ERI] = irqn; \ - return 0; \ - \ -err_eri: \ - RA_IRQ_DISCONNECT_DYNAMIC(data->irq[UART_RA_INT_TXI], eri, dev, uart_ra_isr_eri); \ -err_txi: \ - RA_IRQ_DISCONNECT_DYNAMIC(data->irq[UART_RA_INT_RXI], txi, dev, uart_ra_isr_txi); \ - \ - return irqn; \ - } -#else -#define UART_RA_CONFIG_FUNC(n) -#endif - -#define UART_RA_INIT(n) \ - UART_RA_CONFIG_FUNC(n) \ - UART_RA_INIT_CFG(n); \ - \ - static struct uart_ra_data uart_ra_data_##n = { \ - .current_config = { \ - .baudrate = DT_INST_PROP(n, current_speed), \ - .parity = UART_CFG_PARITY_NONE, \ - .stop_bits = UART_CFG_STOP_BITS_1, \ - .data_bits = UART_CFG_DATA_BITS_8, \ - .flow_ctrl = UART_CFG_FLOW_CTRL_NONE, \ - }, \ - }; \ - \ - DEVICE_DT_INST_DEFINE(n, uart_ra_init, NULL, &uart_ra_data_##n, &uart_ra_cfg_##n, \ - PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, &uart_ra_driver_api); - -DT_INST_FOREACH_STATUS_OKAY(UART_RA_INIT) diff --git a/dts/arm/renesas/ra/r7fa4m1ab3cfm.dtsi b/dts/arm/renesas/ra/r7fa4m1ab3cfm.dtsi deleted file mode 100644 index 8a1702d785a..00000000000 --- a/dts/arm/renesas/ra/r7fa4m1ab3cfm.dtsi +++ /dev/null @@ -1,11 +0,0 @@ -/* - * Copyright (c) 2023 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define RA_SOC_PINS 64 -#define RA_SOC_HAS_MSTPCRE 1 -#define RA_SOC_MSTPD5_CHANNELS 1 - -#include diff --git a/dts/arm/renesas/ra/ra-cm4-common.dtsi b/dts/arm/renesas/ra/ra-cm4-common.dtsi deleted file mode 100644 index 5930631e5ea..00000000000 --- a/dts/arm/renesas/ra/ra-cm4-common.dtsi +++ /dev/null @@ -1,355 +0,0 @@ -/* - * Copyright (c) 2023 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include - -/ { - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-m4"; - reg = <0>; - }; - }; - - clocks: clocks { - xtal: clock-main-osc { - compatible = "renesas,ra-cgc-external-clock"; - clock-frequency = <1200000>; - status = "disabled"; - #clock-cells = <0>; - }; - - subclk: clock-subclk { - compatible = "renesas,ra-cgc-subclk"; - clock-frequency = <32768>; - status = "disabled"; - #clock-cells = <0>; - }; - - hoco: clock-hoco { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - status = "okay"; - #clock-cells = <0>; - }; - - moco: clock-moco { - compatible = "fixed-clock"; - clock-frequency = <8000000>; - status = "okay"; - #clock-cells = <0>; - }; - - loco: clock-loco { - compatible = "fixed-clock"; - clock-frequency = <32768>; - status = "okay"; - #clock-cells = <0>; - }; - - pll: pll { - compatible = "renesas,ra-cgc-pll"; - #clock-cells = <0>; - - /* PLL */ - clocks = <&xtal>; - div = <2>; - mul = <8 0>; - status = "disabled"; - }; - }; - - sram0: memory0@20000000 { - compatible = "mmio-sram"; - reg = <0x20000000 DT_SIZE_K(32)>; - }; - - soc { - interrupt-parent = <&icu>; - icu: interrupt-controller@40006000 { - compatible = "renesas,ra-interrupt-controller-unit"; - reg = <0x40006000 0x40>; - reg-names = "icu"; - interrupt-controller; - #interrupt-cells = <3>; - }; - - pclkblock: pclkblock@4001e01c { - compatible = "renesas,ra-cgc-pclk-block"; - reg = <0x4001e01c 4>, <0x40047000 4>, <0x40047004 4>, - <0x40047008 4>; - reg-names = "MSTPA", "MSTPB","MSTPC", - "MSTPD"; - compatible = "renesas,ra-cgc-pclk-block"; - #clock-cells = <0>; - clocks = <&moco>; - status = "okay"; - - iclk: iclk { - compatible = "renesas,ra-cgc-pclk"; - div = <16>; - #clock-cells = <2>; - status = "okay"; - }; - - pclka: pclka { - compatible = "renesas,ra-cgc-pclk"; - div = <16>; - #clock-cells = <2>; - status = "okay"; - }; - - pclkb: pclkb { - compatible = "renesas,ra-cgc-pclk"; - div = <16>; - #clock-cells = <2>; - status = "okay"; - }; - - pclkc: pclkc { - compatible = "renesas,ra-cgc-pclk"; - div = <1>; - #clock-cells = <2>; - status = "okay"; - }; - - pclkd: pclkd { - compatible = "renesas,ra-cgc-pclk"; - div = <16>; - #clock-cells = <2>; - status = "okay"; - }; - - fclk: fclk { - compatible = "renesas,ra-cgc-pclk"; - div = <16>; - #clock-cells = <2>; - status = "okay"; - }; - - clkout: clkout { - compatible = "renesas,ra-cgc-pclk"; - #clock-cells = <2>; - status = "disabled"; - }; - }; - - fcu: flash-controller@4001c000 { - compatible = "renesas,ra-flash-controller"; - reg = <0x4001c000 0x44>; - reg-names = "fcache"; - - #address-cells = <1>; - #size-cells = <1>; - - flash0: flash0@0 { - compatible = "soc-nv-flash"; - reg = <0x00000000 DT_SIZE_K(256)>; - }; - - flash1: flash1@40100000 { - compatible = "soc-nv-flash"; - reg = <0x40100000 DT_SIZE_K(8)>; - }; - }; - - ioport0: gpio@40040000 { - compatible = "renesas,ra-gpio"; - reg = <0x40040000 0x20>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <16>; - interrupts = , - , - , - , - , - ; - interrupt-names = "port-irq2", "port-irq3", "port-irq6", - "port-irq7", "port-irq10", "port-irq15"; - port-irq2-pins = <2>; - port-irq3-pins = <4>; - port-irq6-pins = <0>; - port-irq7-pins = <1 15>; - port-irq10-pins = <5>; - port-irq15-pins = <11>; - status = "disabled"; - }; - - ioport1: gpio@40040020 { - compatible = "renesas,ra-gpio"; - reg = <0x40040020 0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupts = , - , - , - , - ; - interrupt-names = "port-irq0", "port-irq1", "port-irq2", - "port-irq3", "port-irq4"; - port-irq0-pins = <5>; - port-irq1-pins = <1>; - port-irq2-pins = <0>; - port-irq3-pins = <10>; - port-irq4-pins = <11>; - ngpios = <16>; - status = "disabled"; - }; - - ioport2: gpio@40040040 { - compatible = "renesas,ra-gpio"; - reg = <0x40040040 0x20>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <16>; - interrupts = , - , - , - ; - interrupt-names = "port-irq0", "port-irq1", "port-irq2", - "port-irq3"; - port-irq0-pins = <6>; - port-irq1-pins = <5>; - port-irq2-pins = <13>; - port-irq3-pins = <12>; - status = "disabled"; - }; - - ioport3: gpio@40040060 { - compatible = "renesas,ra-gpio"; - reg = <0x40040060 0x20>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <16>; - interrupts = , - , - , - ; - interrupt-names = "port-irq5", "port-irq6", "port-irq8", "port-irq9"; - port-irq5-pins = <2>; - port-irq6-pins = <1>; - port-irq8-pins = <5>; - port-irq9-pins = <4>; - status = "disabled"; - }; - - ioport4: gpio@40040080 { - compatible = "renesas,ra-gpio"; - reg = <0x40040080 0x20>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <16>; - interrupts = , - , - , - , - , - , - ; - interrupt-names = "port-irq0", "port-irq4", "port-irq5", "port-irq6", - "port-irq7", "port-irq8", "port-irq9"; - port-irq0-pins = <0>; - port-irq4-pins = <2 11>; - port-irq5-pins = <1 10>; - port-irq6-pins = <9>; - port-irq7-pins = <8>; - port-irq8-pins = <15>; - port-irq9-pins = <14>; - status = "disabled"; - }; - - ioport5: gpio@400400a0 { - compatible = "renesas,ra-gpio"; - reg = <0x400400a0 0x20>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <16>; - interrupts = , - , - ; - interrupt-names = "port-irq11", "port-irq12", "port-irq14"; - port-irq11-pins = <1>; - port-irq12-pins = <2>; - port-irq14-pins = <5>; - status = "disabled"; - }; - - pinctrl: pinctrl@40040800 { - compatible = "renesas,ra-pinctrl-pfs"; - reg = <0x40040800 0x500 0x40040d03 0x1>; - reg-names = "pfs", "pmisc_pwpr"; - status = "okay"; - }; - - sci0: sci@40070000 { - compatible = "renesas,ra-sci"; - reg = <0x40070000 0x20>; - interrupts = , - , - , - , - , - ; - interrupt-names = "rxi", "txi", "tei", "eri", "am", "rxi-or-eri"; - clocks = <&pclka MSTPB 31>; - #clock-cells = <1>; - status = "disabled"; - uart { - compatible = "renesas,ra-uart-sci"; - status = "disabled"; - }; - }; - - sci1: sci@40070020 { - compatible = "renesas,ra-sci"; - reg = <0x40070020 0x20>; - interrupts = , - , - , - , - ; - interrupt-names = "rxi", "txi", "tei", "eri", "am"; - clocks = <&pclka MSTPB 30>; - #clock-cells = <1>; - status = "disabled"; - uart { - compatible = "renesas,ra-uart-sci"; - status = "disabled"; - }; - }; - - sci9: sci@40070120 { - compatible = "renesas,ra-sci"; - reg = <0x40070120 0x20>; - interrupts = , - , - , - , - ; - interrupt-names = "rxi", "txi", "tei", "eri", "am"; - clocks = <&pclka MSTPB 22>; - #clock-cells = <1>; - status = "disabled"; - uart { - compatible = "renesas,ra-uart-sci"; - status = "disabled"; - }; - }; - }; -}; - -&nvic { - arm,num-irq-priority-bits = <4>; -}; diff --git a/dts/arm/renesas/ra/ra4-cm4-common.dtsi b/dts/arm/renesas/ra/ra4-cm4-common.dtsi deleted file mode 100644 index e49b9bc766e..00000000000 --- a/dts/arm/renesas/ra/ra4-cm4-common.dtsi +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) 2023 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -/ { - soc { - ioport6: gpio@400400c0 { - compatible = "renesas,ra-gpio"; - reg = <0x400400c0 0x20>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <16>; - status = "disabled"; - }; - - ioport7: gpio@400400e0 { - compatible = "renesas,ra-gpio"; - reg = <0x400400e0 0x20>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <16>; - status = "disabled"; - }; - - ioport8: gpio@40040100 { - compatible = "renesas,ra-gpio"; - reg = <0x40040100 0x20>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <16>; - status = "disabled"; - }; - - ioport9: gpio@40040120 { - compatible = "renesas,ra-gpio"; - reg = <0x40040120 0x20>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <16>; - status = "disabled"; - }; - - sci2: sci@40070040 { - compatible = "renesas,ra-sci"; - reg = <0x40070040 0x20>; - interrupts = , - , - , - , - ; - interrupt-names = "rxi", "txi", "tei", "eri", "am"; - clocks = <&pclka MSTPB 29>; - #clock-cells = <1>; - status = "disabled"; - uart { - compatible = "renesas,ra-uart-sci"; - status = "disabled"; - }; - }; - }; -}; diff --git a/dts/arm/renesas/ra/ra4/r7fa4m1ab3cfm.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m1ab3cfm.dtsi index 3e4f26cb230..c00d5a9f699 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4m1ab3cfm.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4m1ab3cfm.dtsi @@ -13,12 +13,12 @@ /delete-node/ &ioport8; / { - soc { - flash-controller@407e0000 { - flash0: flash@0 { - compatible = "soc-nv-flash"; - reg = <0x0 DT_SIZE_K(256)>; - }; - }; - }; + soc { + flash-controller@407e0000 { + flash0: flash@0 { + compatible = "soc-nv-flash"; + reg = <0x0 DT_SIZE_K(256)>; + }; + }; + }; }; diff --git a/dts/arm/renesas/ra/ra4/r7fa4m1ab3cfp.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m1ab3cfp.dtsi index 11e06f5438d..16bf28fd8b6 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4m1ab3cfp.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4m1ab3cfp.dtsi @@ -9,12 +9,12 @@ #include / { - soc { - flash-controller@407e0000 { - flash0: flash@0 { - compatible = "soc-nv-flash"; - reg = <0x0 DT_SIZE_K(256)>; - }; - }; - }; + soc { + flash-controller@407e0000 { + flash0: flash@0 { + compatible = "soc-nv-flash"; + reg = <0x0 DT_SIZE_K(256)>; + }; + }; + }; }; diff --git a/dts/bindings/gpio/renesas,ra-gpio.yaml b/dts/bindings/gpio/renesas,ra-gpio.yaml deleted file mode 100644 index ad18a0d45da..00000000000 --- a/dts/bindings/gpio/renesas,ra-gpio.yaml +++ /dev/null @@ -1,83 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -description: Renesas RA series GPIO - -compatible: "renesas,ra-gpio" - -include: [gpio-controller.yaml, base.yaml] - -properties: - reg: - required: true - - port-irq0-pins: - type: array - description: Pins allow to assign port-irq0 - - port-irq1-pins: - type: array - description: Pins allow to assign port-irq1 - - port-irq2-pins: - type: array - description: Pins allow to assign port-irq2 - - port-irq3-pins: - type: array - description: Pins allow to assign port-irq3 - - port-irq4-pins: - type: array - description: Pins allow to assign port-irq4 - - port-irq5-pins: - type: array - description: Pins allow to assign port-irq5 - - port-irq6-pins: - type: array - description: Pins allow to assign port-irq6 - - port-irq7-pins: - type: array - description: Pins allow to assign port-irq7 - - port-irq8-pins: - type: array - description: Pins allow to assign port-irq8 - - port-irq9-pins: - type: array - description: Pins allow to assign port-irq9 - - port-irq10-pins: - type: array - description: Pins allow to assign port-irq10 - - port-irq11-pins: - type: array - description: Pins allow to assign port-irq11 - - port-irq12-pins: - type: array - description: Pins allow to assign port-irq12 - - port-irq13-pins: - type: array - description: Pins allow to assign port-irq13 - - port-irq14-pins: - type: array - description: Pins allow to assign port-irq14 - - port-irq15-pins: - type: array - description: Pins allow to assign port-irq15 - - "#gpio-cells": - const: 2 - -gpio-cells: - - pin - - flags diff --git a/dts/bindings/interrupt-controller/renesas,ra-interrupt-controller-unit.yaml b/dts/bindings/interrupt-controller/renesas,ra-interrupt-controller-unit.yaml deleted file mode 100644 index dd13f876cdc..00000000000 --- a/dts/bindings/interrupt-controller/renesas,ra-interrupt-controller-unit.yaml +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright (c) 2023, TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -description: Renesas RA series interrupt controller unit - -compatible: "renesas,ra-interrupt-controller-unit" - -include: [interrupt-controller.yaml, base.yaml] - -properties: - reg: - required: true - - "#interrupt-cells": - const: 3 - -interrupt-cells: - - irq - - priority - - flags diff --git a/dts/bindings/serial/renesas,ra-uart-sci.yaml b/dts/bindings/serial/renesas,ra-uart-sci.yaml deleted file mode 100644 index 94229b06924..00000000000 --- a/dts/bindings/serial/renesas,ra-uart-sci.yaml +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -description: Renesas RA Series SCI based UART controller - -compatible: "renesas,ra-uart-sci" - -include: [uart-controller.yaml] diff --git a/include/zephyr/drivers/interrupt_controller/intc_ra_icu.h b/include/zephyr/drivers/interrupt_controller/intc_ra_icu.h deleted file mode 100644 index d347d81cad8..00000000000 --- a/include/zephyr/drivers/interrupt_controller/intc_ra_icu.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2023 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_RA_ICU_H_ -#define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_RA_ICU_H_ - -#define RA_ICU_FLAG_EVENT_OFFSET 8 -#define RA_ICU_FLAG_EVENT_MASK (BIT_MASK(8) << RA_ICU_FLAG_EVENT_OFFSET) -#define RA_ICU_FLAG_INTCFG_OFFSET 16 -#define RA_ICU_FLAG_INTCFG_MASK (BIT_MASK(8) << RA_ICU_FLAG_INTCFG_OFFSET) - -enum icu_irq_mode { - ICU_FALLING, - ICU_RISING, - ICU_BOTH_EDGE, - ICU_LOW_LEVEL, -}; - -typedef void (*ra_isr_handler)(const void *); - -extern void ra_icu_clear_int_flag(unsigned int irqn); - -extern int ra_icu_query_available_irq(uint32_t event); -extern int ra_icu_query_exists_irq(uint32_t event); - -extern void ra_icu_query_irq_config(unsigned int irq, uint32_t *intcfg, ra_isr_handler *pisr, - const void **cbarg); - -extern int ra_icu_irq_connect_dynamic(unsigned int irq, unsigned int priority, - void (*routine)(const void *parameter), const void *parameter, - uint32_t flags); - -extern int ra_icu_irq_disconnect_dynamic(unsigned int irq, unsigned int priority, - void (*routine)(const void *parameter), - const void *parameter, uint32_t flags); - -#endif /* ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_RA_ICU_H_ */ diff --git a/include/zephyr/dt-bindings/clock/r7fa4m1xxxxxx-clock.h b/include/zephyr/dt-bindings/clock/r7fa4m1xxxxxx-clock.h deleted file mode 100644 index 355c4982a3d..00000000000 --- a/include/zephyr/dt-bindings/clock/r7fa4m1xxxxxx-clock.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (c) 2023 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_DT_BINDINGS_CLOCK_R7FA4M1XXXXXX_CLOCK_H_ -#define ZEPHYR_DT_BINDINGS_CLOCK_R7FA4M1XXXXXX_CLOCK_H_ - -#include - -#endif /* ZEPHYR_DT_BINDINGS_CLOCK_R7FA4M1XXXXXX_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/interrupt-controller/renesas-ra-icu.h b/include/zephyr/dt-bindings/interrupt-controller/renesas-ra-icu.h deleted file mode 100644 index 4df6bfeae52..00000000000 --- a/include/zephyr/dt-bindings/interrupt-controller/renesas-ra-icu.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (c) 2023 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_DT_BINDINGS_INTERRUPT_CONTROLLER_RENESAS_RA_ICU_H_ -#define ZEPHYR_DT_BINDINGS_INTERRUPT_CONTROLLER_RENESAS_RA_ICU_H_ - -#define RA_ICU_IRQ_UNSPECIFIED (-1) - -#define RA_ICU_PORT_IRQ0 (1 << 8) -#define RA_ICU_PORT_IRQ1 (2 << 8) -#define RA_ICU_PORT_IRQ2 (3 << 8) -#define RA_ICU_PORT_IRQ3 (4 << 8) -#define RA_ICU_PORT_IRQ4 (5 << 8) -#define RA_ICU_PORT_IRQ5 (6 << 8) -#define RA_ICU_PORT_IRQ6 (7 << 8) -#define RA_ICU_PORT_IRQ7 (8 << 8) -#define RA_ICU_PORT_IRQ8 (9 << 8) -#define RA_ICU_PORT_IRQ9 (10 << 8) -#define RA_ICU_PORT_IRQ10 (11 << 8) -#define RA_ICU_PORT_IRQ11 (12 << 8) -#define RA_ICU_PORT_IRQ12 (13 << 8) -#define RA_ICU_PORT_IRQ14 (15 << 8) -#define RA_ICU_PORT_IRQ15 (16 << 8) -#define RA_ICU_DMAC0_INT (17 << 8) -#define RA_ICU_DMAC1_INT (18 << 8) -#define RA_ICU_DMAC2_INT (19 << 8) -#define RA_ICU_DMAC3_INT (20 << 8) -#define RA_ICU_DTC_COMPLETE (21 << 8) -#define RA_ICU_ICU_SNZCANCEL (23 << 8) -#define RA_ICU_FCU_FRDYI (24 << 8) -#define RA_ICU_LVD_LVD1 (25 << 8) -#define RA_ICU_LVD_LVD2 (26 << 8) -#define RA_ICU_VBATT_LVD (27 << 8) -#define RA_ICU_MOSC_STOP (28 << 8) -#define RA_ICU_SYSTEM_SNZREQ (29 << 8) -#define RA_ICU_AGT0_AGTI (30 << 8) -#define RA_ICU_AGT0_AGTCMAI (31 << 8) -#define RA_ICU_AGT0_AGTCMBI (32 << 8) -#define RA_ICU_AGT1_AGTI (33 << 8) -#define RA_ICU_AGT1_AGTCMAI (34 << 8) -#define RA_ICU_AGT1_AGTCMBI (35 << 8) -#define RA_ICU_IWDT_NMIUNDF (36 << 8) -#define RA_ICU_WDT_NMIUNDF (37 << 8) -#define RA_ICU_RTC_ALM (38 << 8) -#define RA_ICU_RTC_PRD (39 << 8) -#define RA_ICU_RTC_CUP (40 << 8) -#define RA_ICU_ADC140_ADI (41 << 8) -#define RA_ICU_ADC140_GBADI (42 << 8) -#define RA_ICU_ADC140_CMPAI (43 << 8) -#define RA_ICU_ADC140_CMPBI (44 << 8) -#define RA_ICU_ADC140_WCMPM (45 << 8) -#define RA_ICU_ADC140_WCMPUM (46 << 8) -#define RA_ICU_ACMP_LP0 (47 << 8) -#define RA_ICU_ACMP_LP1 (48 << 8) -#define RA_ICU_USBFS_D0FIFO (49 << 8) -#define RA_ICU_USBFS_D1FIFO (50 << 8) -#define RA_ICU_USBFS_USBI (51 << 8) -#define RA_ICU_USBFS_USBR (52 << 8) -#define RA_ICU_IIC0_RXI (53 << 8) -#define RA_ICU_IIC0_TXI (54 << 8) -#define RA_ICU_IIC0_TEI (55 << 8) -#define RA_ICU_IIC0_EEI (56 << 8) -#define RA_ICU_IIC0_WUI (57 << 8) -#define RA_ICU_IIC1_RXI (58 << 8) -#define RA_ICU_IIC1_TXI (59 << 8) -#define RA_ICU_IIC1_TEI (60 << 8) -#define RA_ICU_IIC1_EEI (61 << 8) -#define RA_ICU_SSIE0_SSITXI (62 << 8) -#define RA_ICU_SSIE0_SSIRXI (63 << 8) - -#define RA_ICU_SSIE0_SSIF (65 << 8) -#define RA_ICU_CTSU_CTSUWR (66 << 8) -#define RA_ICU_CTSU_CTSURD (67 << 8) -#define RA_ICU_CTSU_CTSUFN (68 << 8) -#define RA_ICU_KEY_INTKR (69 << 8) -#define RA_ICU_DOC_DOPCI (70 << 8) -#define RA_ICU_CAC_FERRI (71 << 8) -#define RA_ICU_CAC_MENDI (72 << 8) -#define RA_ICU_CAC_OVFI (73 << 8) -#define RA_ICU_CAN0_ERS (74 << 8) -#define RA_ICU_CAN0_RXF (75 << 8) -#define RA_ICU_CAN0_TXF (76 << 8) -#define RA_ICU_CAN0_RXM (77 << 8) -#define RA_ICU_CAN0_TXM (78 << 8) -#define RA_ICU_IOPORT_GROUP1 (70 << 8) -#define RA_ICU_IOPORT_GROUP2 (80 << 8) -#define RA_ICU_IOPORT_GROUP3 (81 << 8) -#define RA_ICU_IOPORT_GROUP4 (82 << 8) -#define RA_ICU_ELC_SWEVT0 (83 << 8) -#define RA_ICU_ELC_SWEVT1 (84 << 8) -#define RA_ICU_POEG_GROUP0 (85 << 8) -#define RA_ICU_POEG_GROUP1 (86 << 8) -#define RA_ICU_GPT0_CCMPA (87 << 8) -#define RA_ICU_GPT0_CCMPB (88 << 8) -#define RA_ICU_GPT0_CMPC (89 << 8) -#define RA_ICU_GPT0_CMPD (90 << 8) -#define RA_ICU_GPT0_CMPE (91 << 8) -#define RA_ICU_GPT0_CMPF (92 << 8) -#define RA_ICU_GPT0_OVF (93 << 8) -#define RA_ICU_GPT0_UDF (94 << 8) -#define RA_ICU_GPT1_CCMPA (95 << 8) -#define RA_ICU_GPT1_CCMPB (96 << 8) -#define RA_ICU_GPT1_CMPC (97 << 8) -#define RA_ICU_GPT1_CMPD (98 << 8) -#define RA_ICU_GPT1_CMPE (99 << 8) -#define RA_ICU_GPT1_CMPF (100 << 8) -#define RA_ICU_GPT1_OVF (101 << 8) -#define RA_ICU_GPT1_UDF (102 << 8) -#define RA_ICU_GPT2_CCMPA (103 << 8) -#define RA_ICU_GPT2_CCMPB (104 << 8) -#define RA_ICU_GPT2_CMPC (105 << 8) -#define RA_ICU_GPT2_CMPD (106 << 8) -#define RA_ICU_GPT2_CMPE (107 << 8) -#define RA_ICU_GPT2_CMPF (108 << 8) -#define RA_ICU_GPT2_OVF (109 << 8) -#define RA_ICU_GPT2_UDF (110 << 8) -#define RA_ICU_GPT3_CCMPA (111 << 8) -#define RA_ICU_GPT3_CCMPB (112 << 8) -#define RA_ICU_GPT3_CMPC (113 << 8) -#define RA_ICU_GPT3_CMPD (114 << 8) -#define RA_ICU_GPT3_CMPE (115 << 8) -#define RA_ICU_GPT3_CMPF (116 << 8) -#define RA_ICU_GPT3_OVF (117 << 8) -#define RA_ICU_GPT3_UDF (118 << 8) -#define RA_ICU_GPT4_CCMPA (119 << 8) -#define RA_ICU_GPT4_CCMPB (120 << 8) -#define RA_ICU_GPT4_CMPC (121 << 8) -#define RA_ICU_GPT4_CMPD (122 << 8) -#define RA_ICU_GPT4_CMPE (123 << 8) -#define RA_ICU_GPT4_CMPF (124 << 8) -#define RA_ICU_GPT4_OVF (125 << 8) -#define RA_ICU_GPT4_UDF (126 << 8) -#define RA_ICU_GPT5_CCMPA (127 << 8) -#define RA_ICU_GPT5_CCMPB (128 << 8) -#define RA_ICU_GPT5_CMPC (129 << 8) -#define RA_ICU_GPT5_CMPD (130 << 8) -#define RA_ICU_GPT5_CMPE (131 << 8) -#define RA_ICU_GPT5_CMPF (132 << 8) -#define RA_ICU_GPT5_OVF (133 << 8) -#define RA_ICU_GPT5_UDF (134 << 8) -#define RA_ICU_GPT6_CCMPA (135 << 8) -#define RA_ICU_GPT6_CCMPB (136 << 8) -#define RA_ICU_GPT6_CMPC (137 << 8) -#define RA_ICU_GPT6_CMPD (138 << 8) -#define RA_ICU_GPT6_CMPE (139 << 8) -#define RA_ICU_GPT6_CMPF (140 << 8) -#define RA_ICU_GPT6_OVF (141 << 8) -#define RA_ICU_GPT6_UDF (142 << 8) -#define RA_ICU_GPT7_CCMPA (143 << 8) -#define RA_ICU_GPT7_CCMPB (144 << 8) -#define RA_ICU_GPT7_CMPC (145 << 8) -#define RA_ICU_GPT7_CMPD (146 << 8) -#define RA_ICU_GPT7_CMPE (147 << 8) -#define RA_ICU_GPT7_CMPF (148 << 8) -#define RA_ICU_GPT7_OVF (149 << 8) -#define RA_ICU_GPT7_UDF (150 << 8) -#define RA_ICU_GPT_UVWEDGE (151 << 8) -#define RA_ICU_SCI0_RXI (152 << 8) -#define RA_ICU_SCI0_TXI (153 << 8) -#define RA_ICU_SCI0_TEI (154 << 8) -#define RA_ICU_SCI0_ERI (155 << 8) -#define RA_ICU_SCI0_AM (156 << 8) -#define RA_ICU_SCI0_RXI_OR_ERI (157 << 8) -#define RA_ICU_SCI1_RXI (158 << 8) -#define RA_ICU_SCI1_TXI (159 << 8) -#define RA_ICU_SCI1_TEI (160 << 8) -#define RA_ICU_SCI1_ERI (161 << 8) -#define RA_ICU_SCI1_AM (162 << 8) -#define RA_ICU_SCI2_RXI (163 << 8) -#define RA_ICU_SCI2_TXI (164 << 8) -#define RA_ICU_SCI2_TEI (165 << 8) -#define RA_ICU_SCI2_ERI (166 << 8) -#define RA_ICU_SCI2_AM (167 << 8) -#define RA_ICU_SCI9_RXI (168 << 8) -#define RA_ICU_SCI9_TXI (169 << 8) -#define RA_ICU_SCI9_TEI (170 << 8) -#define RA_ICU_SCI9_ERI (171 << 8) -#define RA_ICU_SCI9_AM (172 << 8) -#define RA_ICU_SPI0_SPRI (173 << 8) -#define RA_ICU_SPI0_SPTI (174 << 8) -#define RA_ICU_SPI0_SPII (175 << 8) -#define RA_ICU_SPI0_SPEI (176 << 8) -#define RA_ICU_SPI0_SPTEND (177 << 8) -#define RA_ICU_SPI1_SPRI (178 << 8) -#define RA_ICU_SPI1_SPTI (179 << 8) -#define RA_ICU_SPI1_SPII (180 << 8) -#define RA_ICU_SPI1_SPEI (181 << 8) -#define RA_ICU_SPI1_SPTEND (182 << 8) - -#endif /* ZEPHYR_DT_BINDINGS_INTERRUPT_CONTROLLER_RENESAS_RA_ICU_H_ */ diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra-common.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra-common.h deleted file mode 100644 index a7969523a93..00000000000 --- a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra-common.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2023 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RA_COMMON_H_ -#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RA_COMMON_H_ - -#define PORT4_POS 29 -#define PORT4_MASK 0x1 -#define PSEL_POS 24 -#define PSEL_MASK 0x5 -#define PORT_POS 21 -#define PORT_MASK 0x7 -#define PIN_POS 17 -#define PIN_MASK 0xF -#define OPT_POS 0 -#define OPT_MASK 0x1B000 - -#define RA_PINCFG_GPIO 0x00000 -#define RA_PINCFG_FUNC 0x10000 -#define RA_PINCFG_ANALOG 0x08000 - -#define RA_PINCFG(port, pin, psel, opt) \ - ((((psel)&PSEL_MASK) << PSEL_POS) | (((pin)&PIN_MASK) << PIN_POS) | \ - (((port)&PORT_MASK) << PORT_POS) | ((((port) >> 3) & PORT4_MASK) << PORT4_POS) | \ - (((opt)&OPT_MASK) << OPT_POS)) - -#if RA_SOC_PINS >= 40 -#define RA_PINCFG__40(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt) -#endif - -#if RA_SOC_PINS >= 48 -#define RA_PINCFG__48(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt) -#endif - -#if RA_SOC_PINS >= 64 -#define RA_PINCFG__64(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt) -#endif - -#if RA_SOC_PINS >= 100 -#define RA_PINCFG_100(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt) -#endif - -#endif diff --git a/soc/renesas/ra/common_fsp/pinctrl_soc.h b/soc/renesas/ra/common_fsp/pinctrl_soc.h index dc08dc3db10..ff345032f80 100644 --- a/soc/renesas/ra/common_fsp/pinctrl_soc.h +++ b/soc/renesas/ra/common_fsp/pinctrl_soc.h @@ -28,8 +28,6 @@ struct ra_pinctrl_soc_pin { typedef struct ra_pinctrl_soc_pin pinctrl_soc_pin_t; -int ra_pinctrl_query_config(uint32_t port, uint32_t pin, pinctrl_soc_pin_t *pincfg); - /** * @brief Utility macro to initialize each pin. *