arch: riscv: imply XIP config pushed to SoC level

'imply XIP' pushed from arch/Kconfig/'config RISCV' to riscv SoCs Kconfig
files to allow riscv SoCs having XIP enabled (or not) at SoC level

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>

arch/Kconfig

@@ -122,7 +122,6 @@ config RISCV
 	select ARCH_HAS_DIRECTED_IPIS
 	select BARRIER_OPERATIONS_BUILTIN
 	select ARCH_HAS_THREAD_PRIV_STACK_SPACE_GET if USERSPACE
-	imply XIP
 	help
 	  RISCV architecture
 

soc/andestech/ae350/Kconfig

@@ -5,6 +5,7 @@ config SOC_SERIES_ANDES_AE350
 	select RISCV
 	select RISCV_PRIVILEGED
 	select RISCV_HAS_PLIC
+	imply XIP
 
 config SOC_ANDES_AE350
 	select ATOMIC_OPERATIONS_BUILTIN

soc/efinix/sapphire/Kconfig

@@ -12,3 +12,4 @@ config SOC_EFINIX_SAPPHIRE
 	select RISCV
 	select RISCV_PRIVILEGED
 	select RISCV_HAS_PLIC
+	imply XIP

soc/intel/intel_niosv/niosv/Kconfig

@@ -11,6 +11,7 @@ config SOC_SERIES_NIOSV
 	select RISCV_ISA_EXT_A
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
+	imply XIP
 
 config SOC_NIOSV_M
 	help

soc/ite/ec/it8xxx2/Kconfig

@@ -20,6 +20,7 @@ config SOC_IT8XXX2
 	select RISCV_ISA_EXT_M if !(SOC_IT81302BX || SOC_IT81202BX)
 	select RISCV_ISA_EXT_A
 	select RISCV_ISA_EXT_C
+	imply XIP
 
 config SOC_IT8XXX2_REG_SET_V1
 	bool

soc/litex/litex_vexriscv/Kconfig

@@ -9,6 +9,7 @@ config SOC_LITEX_VEXRISCV
 	select RISCV_ISA_EXT_M
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
+	imply XIP
 
 if SOC_LITEX_VEXRISCV
 

soc/lowrisc/opentitan/Kconfig

@@ -19,3 +19,4 @@ config SOC_OPENTITAN
 	# OpenTitan Ibex core mtvec mode is read-only / forced to vectored mode.
 	select RISCV_VECTORED_MODE
 	select GEN_IRQ_VECTOR_TABLE
+	imply XIP

soc/microchip/miv/miv/Kconfig

@@ -7,6 +7,7 @@ config SOC_SERIES_MIV
 	select RISCV
 	select RISCV_PRIVILEGED
 	select RISCV_HAS_PLIC
+	imply XIP
 
 config SOC_MIV
 	select ATOMIC_OPERATIONS_BUILTIN

soc/microchip/miv/polarfire/Kconfig

@@ -7,6 +7,7 @@ config SOC_SERIES_POLARFIRE
 	select RISCV
 	select RISCV_PRIVILEGED
 	select RISCV_HAS_PLIC
+	imply XIP
 
 config SOC_POLARFIRE
 	select 64BIT

soc/neorv32/Kconfig

@@ -9,6 +9,7 @@ config SOC_NEORV32
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
 	select RISCV_PRIVILEGED
+	imply XIP
 
 if SOC_NEORV32
 

soc/nordic/common/vpr/Kconfig

@@ -20,5 +20,6 @@ config RISCV_CORE_NORDIC_VPR
 	select ARCH_HAS_CUSTOM_CPU_IDLE
 	select ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE
 	select INCLUDE_RESET_VECTOR
+	imply XIP
 	help
 	  Enable support for the RISC-V Nordic VPR core.

soc/qemu/virt_riscv/Kconfig

@@ -10,6 +10,7 @@ config SOC_FAMILY_QEMU_VIRT_RISCV
 	select RISCV
 	select RISCV_PRIVILEGED
 	select RISCV_HAS_PLIC
+	imply XIP
 
 if SOC_FAMILY_QEMU_VIRT_RISCV
 

soc/renode/riscv_virtual/Kconfig

@@ -13,3 +13,4 @@ config SOC_RISCV_VIRTUAL_RENODE
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
 	select RISCV_HAS_PLIC
+	imply XIP

soc/sifive/sifive_freedom/fe300/Kconfig

@@ -20,3 +20,5 @@ config SOC_SERIES_SIFIVE_FREEDOM_FE300
 
 	select ATOMIC_OPERATIONS_C
 	select INCLUDE_RESET_VECTOR
+
+	imply XIP

soc/sifive/sifive_freedom/fu500/Kconfig

@@ -15,6 +15,7 @@ config SOC_SERIES_SIFIVE_FREEDOM_FU500
 	select RISCV_ISA_EXT_C
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
+	imply XIP
 
 	select 64BIT
 	select INCLUDE_RESET_VECTOR

soc/sifive/sifive_freedom/fu700/Kconfig

@@ -14,6 +14,7 @@ config SOC_SERIES_SIFIVE_FREEDOM_FU700
 	select RISCV_ISA_EXT_C
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
+	imply XIP
 
 	select INCLUDE_RESET_VECTOR
 	select 64BIT

soc/snps/nsim/arc_v/rmx/Kconfig

@@ -14,3 +14,4 @@ config SOC_SERIES_RMX
 	select RISCV_ISA_EXT_ZIFENCEI
 	select INCLUDE_RESET_VECTOR
 	select ATOMIC_OPERATIONS_BUILTIN
+	imply XIP

soc/starfive/jh71xx/Kconfig

@@ -5,6 +5,7 @@ config SOC_SERIES_STARFIVE_JH71XX
 	select RISCV
 	select RISCV_PRIVILEGED
 	select RISCV_HAS_PLIC
+	imply XIP
 
 config SOC_JH7100
 	select ATOMIC_OPERATIONS_BUILTIN

soc/telink/tlsr/tlsr951x/Kconfig

@@ -16,6 +16,7 @@ config SOC_SERIES_TLSR951X
 	select ATOMIC_OPERATIONS_BUILTIN
 	select CPU_HAS_FPU
 	select INCLUDE_RESET_VECTOR
+	imply XIP
 
 if SOC_SERIES_TLSR951X