arch: riscv: imply XIP config pushed to SoC level
'imply XIP' pushed from arch/Kconfig/'config RISCV' to riscv SoCs Kconfig files to allow riscv SoCs having XIP enabled (or not) at SoC level Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
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41cc12c79c
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19 changed files with 19 additions and 1 deletions
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@ -122,7 +122,6 @@ config RISCV
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select ARCH_HAS_DIRECTED_IPIS
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select ARCH_HAS_DIRECTED_IPIS
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select BARRIER_OPERATIONS_BUILTIN
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select BARRIER_OPERATIONS_BUILTIN
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select ARCH_HAS_THREAD_PRIV_STACK_SPACE_GET if USERSPACE
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select ARCH_HAS_THREAD_PRIV_STACK_SPACE_GET if USERSPACE
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imply XIP
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help
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help
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RISCV architecture
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RISCV architecture
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@ -5,6 +5,7 @@ config SOC_SERIES_ANDES_AE350
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select RISCV
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select RISCV
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select RISCV_PRIVILEGED
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select RISCV_PRIVILEGED
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select RISCV_HAS_PLIC
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select RISCV_HAS_PLIC
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imply XIP
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config SOC_ANDES_AE350
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config SOC_ANDES_AE350
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select ATOMIC_OPERATIONS_BUILTIN
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select ATOMIC_OPERATIONS_BUILTIN
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@ -12,3 +12,4 @@ config SOC_EFINIX_SAPPHIRE
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select RISCV
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select RISCV
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select RISCV_PRIVILEGED
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select RISCV_PRIVILEGED
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select RISCV_HAS_PLIC
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select RISCV_HAS_PLIC
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imply XIP
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@ -11,6 +11,7 @@ config SOC_SERIES_NIOSV
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select RISCV_ISA_EXT_A
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select RISCV_ISA_EXT_A
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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select RISCV_ISA_EXT_ZIFENCEI
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imply XIP
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config SOC_NIOSV_M
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config SOC_NIOSV_M
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help
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help
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@ -20,6 +20,7 @@ config SOC_IT8XXX2
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select RISCV_ISA_EXT_M if !(SOC_IT81302BX || SOC_IT81202BX)
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select RISCV_ISA_EXT_M if !(SOC_IT81302BX || SOC_IT81202BX)
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select RISCV_ISA_EXT_A
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select RISCV_ISA_EXT_A
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select RISCV_ISA_EXT_C
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select RISCV_ISA_EXT_C
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imply XIP
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config SOC_IT8XXX2_REG_SET_V1
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config SOC_IT8XXX2_REG_SET_V1
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bool
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bool
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@ -9,6 +9,7 @@ config SOC_LITEX_VEXRISCV
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select RISCV_ISA_EXT_M
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select RISCV_ISA_EXT_M
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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select RISCV_ISA_EXT_ZIFENCEI
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imply XIP
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if SOC_LITEX_VEXRISCV
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if SOC_LITEX_VEXRISCV
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@ -19,3 +19,4 @@ config SOC_OPENTITAN
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# OpenTitan Ibex core mtvec mode is read-only / forced to vectored mode.
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# OpenTitan Ibex core mtvec mode is read-only / forced to vectored mode.
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select RISCV_VECTORED_MODE
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select RISCV_VECTORED_MODE
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select GEN_IRQ_VECTOR_TABLE
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select GEN_IRQ_VECTOR_TABLE
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imply XIP
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@ -7,6 +7,7 @@ config SOC_SERIES_MIV
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select RISCV
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select RISCV
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select RISCV_PRIVILEGED
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select RISCV_PRIVILEGED
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select RISCV_HAS_PLIC
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select RISCV_HAS_PLIC
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imply XIP
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config SOC_MIV
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config SOC_MIV
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select ATOMIC_OPERATIONS_BUILTIN
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select ATOMIC_OPERATIONS_BUILTIN
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@ -7,6 +7,7 @@ config SOC_SERIES_POLARFIRE
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select RISCV
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select RISCV
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select RISCV_PRIVILEGED
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select RISCV_PRIVILEGED
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select RISCV_HAS_PLIC
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select RISCV_HAS_PLIC
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imply XIP
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config SOC_POLARFIRE
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config SOC_POLARFIRE
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select 64BIT
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select 64BIT
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@ -9,6 +9,7 @@ config SOC_NEORV32
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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select RISCV_ISA_EXT_ZIFENCEI
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select RISCV_PRIVILEGED
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select RISCV_PRIVILEGED
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imply XIP
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if SOC_NEORV32
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if SOC_NEORV32
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@ -20,5 +20,6 @@ config RISCV_CORE_NORDIC_VPR
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select ARCH_HAS_CUSTOM_CPU_IDLE
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select ARCH_HAS_CUSTOM_CPU_IDLE
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select ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE
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select ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE
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select INCLUDE_RESET_VECTOR
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select INCLUDE_RESET_VECTOR
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imply XIP
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help
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help
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Enable support for the RISC-V Nordic VPR core.
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Enable support for the RISC-V Nordic VPR core.
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@ -10,6 +10,7 @@ config SOC_FAMILY_QEMU_VIRT_RISCV
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select RISCV
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select RISCV
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select RISCV_PRIVILEGED
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select RISCV_PRIVILEGED
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select RISCV_HAS_PLIC
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select RISCV_HAS_PLIC
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imply XIP
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if SOC_FAMILY_QEMU_VIRT_RISCV
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if SOC_FAMILY_QEMU_VIRT_RISCV
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@ -13,3 +13,4 @@ config SOC_RISCV_VIRTUAL_RENODE
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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select RISCV_ISA_EXT_ZIFENCEI
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select RISCV_HAS_PLIC
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select RISCV_HAS_PLIC
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imply XIP
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@ -20,3 +20,5 @@ config SOC_SERIES_SIFIVE_FREEDOM_FE300
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select ATOMIC_OPERATIONS_C
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select ATOMIC_OPERATIONS_C
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select INCLUDE_RESET_VECTOR
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select INCLUDE_RESET_VECTOR
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imply XIP
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@ -15,6 +15,7 @@ config SOC_SERIES_SIFIVE_FREEDOM_FU500
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select RISCV_ISA_EXT_C
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select RISCV_ISA_EXT_C
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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select RISCV_ISA_EXT_ZIFENCEI
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imply XIP
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select 64BIT
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select 64BIT
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select INCLUDE_RESET_VECTOR
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select INCLUDE_RESET_VECTOR
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@ -14,6 +14,7 @@ config SOC_SERIES_SIFIVE_FREEDOM_FU700
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select RISCV_ISA_EXT_C
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select RISCV_ISA_EXT_C
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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select RISCV_ISA_EXT_ZIFENCEI
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imply XIP
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select INCLUDE_RESET_VECTOR
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select INCLUDE_RESET_VECTOR
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select 64BIT
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select 64BIT
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@ -14,3 +14,4 @@ config SOC_SERIES_RMX
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select RISCV_ISA_EXT_ZIFENCEI
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select RISCV_ISA_EXT_ZIFENCEI
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select INCLUDE_RESET_VECTOR
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select INCLUDE_RESET_VECTOR
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select ATOMIC_OPERATIONS_BUILTIN
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select ATOMIC_OPERATIONS_BUILTIN
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imply XIP
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@ -5,6 +5,7 @@ config SOC_SERIES_STARFIVE_JH71XX
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select RISCV
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select RISCV
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select RISCV_PRIVILEGED
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select RISCV_PRIVILEGED
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select RISCV_HAS_PLIC
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select RISCV_HAS_PLIC
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imply XIP
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config SOC_JH7100
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config SOC_JH7100
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select ATOMIC_OPERATIONS_BUILTIN
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select ATOMIC_OPERATIONS_BUILTIN
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@ -16,6 +16,7 @@ config SOC_SERIES_TLSR951X
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select ATOMIC_OPERATIONS_BUILTIN
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select ATOMIC_OPERATIONS_BUILTIN
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select CPU_HAS_FPU
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select CPU_HAS_FPU
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select INCLUDE_RESET_VECTOR
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select INCLUDE_RESET_VECTOR
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imply XIP
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if SOC_SERIES_TLSR951X
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if SOC_SERIES_TLSR951X
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