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boards: nordic: Remove nRF54L15 PDK

Browse source 
The nRF54L15 Development Kit is now available, so remove the Preview
Development Kit (PDK).

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
This commit is contained in:
Carles Cufi 2024-10-16 21:47:51 +02:00 • committed by David Leach
commit cb47c62259
75 changed files with 3 additions and 1598 deletions
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3
boards/deprecated.cmake
View file

@ -508,9 +508,6 @@ set(nrf5340dk_nrf5340_cpuapp_ns_DEPRECATED
set(nrf5340dk_nrf5340_cpunet_DEPRECATED
nrf5340dk/nrf5340/cpunet
)
set(nrf54l15pdk_nrf54l15_cpuapp_DEPRECATED
nrf54l15pdk/nrf54l15/cpuapp
)
set(nrf9131ek_nrf9131_DEPRECATED
nrf9131ek
)

12
boards/nordic/nrf54l15pdk/Kconfig.defconfig
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@ -1,12 +0,0 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
if BOARD_NRF54L15PDK_NRF54L15_CPUAPP
config BT_CTLR
default BT
config ROM_START_OFFSET
default 0x800 if BOOTLOADER_MCUBOOT
endif # BOARD_NRF54L15PDK_NRF54L15_CPUAPP

7
boards/nordic/nrf54l15pdk/Kconfig.nrf54l15pdk
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@ -1,7 +0,0 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
config BOARD_NRF54L15PDK
select SOC_NRF54L15_ENGA_CPUAPP if BOARD_NRF54L15PDK_NRF54L15_CPUAPP
select SOC_NRF54L15_ENGA_CPUFLPR if BOARD_NRF54L15PDK_NRF54L15_CPUFLPR || \
BOARD_NRF54L15PDK_NRF54L15_CPUFLPR_XIP

12
boards/nordic/nrf54l15pdk/board.cmake
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@ -1,12 +0,0 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
if (CONFIG_SOC_NRF54L15_ENGA_CPUAPP)
board_runner_args(jlink "--device=cortex-m33" "--speed=4000")
elseif (CONFIG_SOC_NRF54L15_ENGA_CPUFLPR)
board_runner_args(jlink "--speed=4000")
endif()
include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

15
boards/nordic/nrf54l15pdk/board.yml
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@ -1,15 +0,0 @@
board:
name: nrf54l15pdk
full_name: nRF54L15 PDK
vendor: nordic
socs:
- name: nrf54l15
variants:
- name: xip
cpucluster: cpuflpr
revision:
format: major.minor.patch
default: "0.3.0"
revisions:
- name: "0.2.1"
- name: "0.3.0"

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boards/nordic/nrf54l15pdk/doc/img/nrf54l15pdk_nrf54l15.webp
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142
boards/nordic/nrf54l15pdk/doc/index.rst
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@ -1,142 +0,0 @@
.. _nrf54l15pdk_nrf54l15:
nRF54L15 PDK
############
Overview
********
.. note::
All software for the nRF54L15 SoC is experimental and hardware availability
is restricted to the participants in the limited sampling program.
The nRF54L15 Preview Development Kit hardware provides
support for the Nordic Semiconductor nRF54L15 Arm Cortex-M33 CPU and
the following devices:
* :abbr:`SAADC (Successive Approximation Analog to Digital Converter)`
* CLOCK
* RRAM
* :abbr:`GPIO (General Purpose Input Output)`
* :abbr:`TWIM (I2C-compatible two-wire interface master with EasyDMA)`
* MEMCONF
* :abbr:`MPU (Memory Protection Unit)`
* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
* :abbr:`PWM (Pulse Width Modulation)`
* :abbr:`GRTC (Global real-time counter)`
* Segger RTT (RTT Console)
* :abbr:`SPI (Serial Peripheral Interface)`
* :abbr:`UARTE (Universal asynchronous receiver-transmitter)`
* :abbr:`WDT (Watchdog Timer)`
.. figure:: img/nrf54l15pdk_nrf54l15.webp
:align: center
:alt: nRF54L15 PDK
nRF54L15 PDK (Credit: Nordic Semiconductor)
Hardware
********
nRF54L15 PDK has two crystal oscillators:
* High-frequency 32 MHz crystal oscillator (HFXO)
* Low-frequency 32.768 kHz crystal oscillator (LFXO)
The crystal oscillators can be configured to use either
internal or external capacitors.
Supported Features
==================
The ``nrf54l15pdk/nrf54l15/cpuapp`` board configuration supports the following
hardware features:
+-----------+------------+----------------------+
| Interface | Controller | Driver/Component |
+===========+============+======================+
| SAADC | on-chip | adc |
+-----------+------------+----------------------+
| CLOCK | on-chip | clock_control |
+-----------+------------+----------------------+
| RRAM | on-chip | flash |
+-----------+------------+----------------------+
| GPIO | on-chip | gpio |
+-----------+------------+----------------------+
| TWIM | on-chip | i2c |
+-----------+------------+----------------------+
| MEMCONF | on-chip | retained_mem |
+-----------+------------+----------------------+
| MPU | on-chip | arch/arm |
+-----------+------------+----------------------+
| NVIC | on-chip | arch/arm |
+-----------+------------+----------------------+
| PWM | on-chip | pwm |
+-----------+------------+----------------------+
| GRTC | on-chip | counter |
+-----------+------------+----------------------+
| RTT | Segger | console |
+-----------+------------+----------------------+
| SPI(M/S) | on-chip | spi |
+-----------+------------+----------------------+
| SPU | on-chip | system protection |
+-----------+------------+----------------------+
| UARTE | on-chip | serial |
+-----------+------------+----------------------+
| WDT | on-chip | watchdog |
+-----------+------------+----------------------+
Other hardware features have not been enabled yet for this board.
Programming and Debugging
*************************
Applications for the ``nrf54l15pdk/nrf54l15/cpuapp`` board can be
built, flashed, and debugged in the usual way. See
:ref:`build_an_application` and :ref:`application_run` for more details on
building and running.
Flashing
========
As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world`
application.
.. warning::
When programming the device, you might get an error similar to the following message::
ERROR: The operation attempted is unavailable due to readback protection in
ERROR: your device. Please use --recover to unlock the device.
This error occurs when readback protection is enabled.
To disable the readback protection, you must *recover* your device.
Enter the following command to recover the core::
west flash --recover
The ``--recover`` command erases the flash memory and then writes a small binary into
the recovered flash memory.
This binary prevents the readback protection from enabling itself again after a pin
reset or power cycle.
Follow the instructions in the :ref:`nordic_segger` page to install
and configure all the necessary software. Further information can be
found in :ref:`nordic_segger_flashing`.
To build and program the sample to the nRF54L15 PDK, complete the following steps:
First, connect the nRF54L15 PDK to you computer using the IMCU USB port on the PDK.
Next, build the sample by running the following command:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nrf54l15pdk/nrf54l15/cpuapp
:goals: build flash
Testing the LEDs and buttons in the nRF54L15 PDK
************************************************
Test the nRF54L15 PDK with a :zephyr:code-sample:`blinky` sample.

156
boards/nordic/nrf54l15pdk/nrf54l15_cpuapp_common.dtsi
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@ -1,156 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/* This file is common to the secure and non-secure domain */
#include <nordic/nrf54l15_enga_cpuapp.dtsi>
#include "nrf54l15pdk_nrf54l15-common.dtsi"
/ {
chosen {
zephyr,console = &uart20;
zephyr,shell-uart = &uart20;
zephyr,uart-mcumgr = &uart20;
zephyr,bt-mon-uart = &uart20;
zephyr,bt-c2h-uart = &uart20;
zephyr,flash-controller = &rram_controller;
zephyr,flash = &cpuapp_rram;
zephyr,ieee802154 = &ieee802154;
};
};
&cpuapp_sram {
status = "okay";
};
&lfxo {
load-capacitors = "internal";
load-capacitance-femtofarad = <15500>;
};
&hfxo {
load-capacitors = "internal";
load-capacitance-femtofarad = <15000>;
};
&regulators {
status = "okay";
};
&vregmain {
status = "okay";
regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
};
&grtc {
owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;
/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
child-owned-channels = <3 4 7 8 9 10 11>;
status = "okay";
};
&cpuapp_rram {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x0 DT_SIZE_K(64)>;
};
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x10000 DT_SIZE_K(324)>;
};
slot0_ns_partition: partition@61000 {
label = "image-0-nonsecure";
reg = <0x61000 DT_SIZE_K(324)>;
};
slot1_partition: partition@b2000 {
label = "image-1";
reg = <0xb2000 DT_SIZE_K(324)>;
};
slot1_ns_partition: partition@103000 {
label = "image-1-nonsecure";
reg = <0x103000 DT_SIZE_K(324)>;
};
/* 32k from 0x154000 to 0x15bfff reserved for TF-M partitions */
storage_partition: partition@15c000 {
label = "storage";
reg = <0x15c000 DT_SIZE_K(36)>;
};
};
};
&uart20 {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&gpiote20 {
status = "okay";
};
&gpiote30 {
status = "okay";
};
&radio {
status = "okay";
};
&ieee802154 {
status = "okay";
};
&temp {
status = "okay";
};
&clock {
status = "okay";
};
&spi00 {
status = "okay";
cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&spi00_default>;
pinctrl-1 = <&spi00_sleep>;
pinctrl-names = "default", "sleep";
mx25r64: mx25r6435f@0 {
compatible = "jedec,spi-nor";
status = "disabled";
reg = <0>;
spi-max-frequency = <8000000>;
jedec-id = [c2 28 17];
sfdp-bfp = [
e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb
ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52
10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 48 44
30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff
];
size = <67108864>;
has-dpd;
t-enter-dpd = <10000>;
t-exit-dpd = <35000>;
};
};
&adc {
status = "okay";
};

100
boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15-common.dtsi
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@ -1,100 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "nrf54l15pdk_nrf54l15-pinctrl.dtsi"
/ {
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
label = "Green LED 0";
};
led1: led_1 {
gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
label = "Green LED 1";
};
led2: led_2 {
gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
label = "Green LED 2";
};
led3: led_3 {
gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
label = "Green LED 3";
};
};
pwmleds {
compatible = "pwm-leds";
/*
* PWM signal can be exposed on GPIO pin only within same domain.
* There is only one domain which contains both PWM and GPIO:
* PWM20/21/22 and GPIO Port P1.
* Only LEDs connected to P1 can work with PWM, for example LED1.
*/
pwm_led1: pwm_led_1 {
pwms = <&pwm20 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
};
};
buttons {
compatible = "gpio-keys";
button0: button_0 {
gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 0";
zephyr,code = <INPUT_KEY_0>;
};
button1: button_1 {
gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 1";
zephyr,code = <INPUT_KEY_1>;
};
button2: button_2 {
gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 2";
zephyr,code = <INPUT_KEY_2>;
};
button3: button_3 {
gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 3";
zephyr,code = <INPUT_KEY_3>;
};
};
aliases {
led0 = &led0;
led1 = &led1;
led2 = &led2;
led3 = &led3;
pwm-led0 = &pwm_led1;
sw0 = &button0;
sw1 = &button1;
sw2 = &button2;
sw3 = &button3;
watchdog0 = &wdt31;
};
};
&uart20 {
current-speed = <115200>;
pinctrl-0 = <&uart20_default>;
pinctrl-1 = <&uart20_sleep>;
pinctrl-names = "default", "sleep";
};
&uart30 {
current-speed = <115200>;
pinctrl-0 = <&uart30_default>;
pinctrl-1 = <&uart30_sleep>;
pinctrl-names = "default", "sleep";
};
&pwm20 {
status = "okay";
pinctrl-0 = <&pwm20_default>;
pinctrl-1 = <&pwm20_sleep>;
pinctrl-names = "default", "sleep";
};

80
boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15-pinctrl.dtsi
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@ -1,80 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor
* SPDX-License-Identifier: Apache-2.0
*/
&pinctrl {
/omit-if-no-ref/ uart20_default: uart20_default {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 4)>,
<NRF_PSEL(UART_RTS, 1, 6)>;
};
group2 {
psels = <NRF_PSEL(UART_RX, 1, 5)>,
<NRF_PSEL(UART_CTS, 1, 7)>;
bias-pull-up;
};
};
/omit-if-no-ref/ uart20_sleep: uart20_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 4)>,
<NRF_PSEL(UART_RX, 1, 5)>,
<NRF_PSEL(UART_RTS, 1, 6)>,
<NRF_PSEL(UART_CTS, 1, 7)>;
low-power-enable;
};
};
/omit-if-no-ref/ uart30_default: uart30_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 0)>,
<NRF_PSEL(UART_RTS, 0, 2)>;
};
group2 {
psels = <NRF_PSEL(UART_RX, 0, 1)>,
<NRF_PSEL(UART_CTS, 0, 3)>;
bias-pull-up;
};
};
/omit-if-no-ref/ uart30_sleep: uart30_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 0)>,
<NRF_PSEL(UART_RX, 0, 1)>,
<NRF_PSEL(UART_RTS, 0, 2)>,
<NRF_PSEL(UART_CTS, 0, 3)>;
low-power-enable;
};
};
/omit-if-no-ref/ spi00_default: spi00_default {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 2, 1)>,
<NRF_PSEL(SPIM_MOSI, 2, 2)>,
<NRF_PSEL(SPIM_MISO, 2, 4)>;
};
};
/omit-if-no-ref/ spi00_sleep: spi00_sleep {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 2, 1)>,
<NRF_PSEL(SPIM_MOSI, 2, 2)>,
<NRF_PSEL(SPIM_MISO, 2, 4)>;
low-power-enable;
};
};
/omit-if-no-ref/ pwm20_default: pwm20_default {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 1, 10)>;
};
};
/omit-if-no-ref/ pwm20_sleep: pwm20_sleep {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 1, 10)>;
low-power-enable;
};
};
};

52
boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_common_0_2_1.dtsi
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@ -1,52 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
&led0 {
gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
};
&led1 {
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
};
&led2 {
gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
};
&led3 {
gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
};
&button0 {
gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
};
&button1 {
gpios = <&gpio1 10 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
};
&button2 {
gpios = <&gpio2 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
};
&button3 {
gpios = <&gpio2 10 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
};
&pinctrl {
/omit-if-no-ref/ pwm20_default: pwm20_default {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 1, 8)>;
};
};
/omit-if-no-ref/ pwm20_sleep: pwm20_sleep {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 1, 8)>;
low-power-enable;
};
};
};

19
boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts
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@ -1,19 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include "nrf54l15_cpuapp_common.dtsi"
/ {
compatible = "nordic,nrf54l15pdk_nrf54l15-cpuapp";
model = "Nordic nRF54L15 PDK nRF54L15 Application MCU";
chosen {
zephyr,code-partition = &slot0_partition;
zephyr,sram = &cpuapp_sram;
};
};

24
boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.yaml
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@ -1,24 +0,0 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
identifier: nrf54l15pdk/nrf54l15/cpuapp
name: nRF54l15-PDK-nRF54l15-Application
type: mcu
arch: arm
toolchain:
- gnuarmemb
- xtools
- zephyr
sysbuild: true
ram: 188
flash: 324
supported:
- adc
- counter
- gpio
- i2c
- pwm
- retained_mem
- spi
- watchdog
- i2s

7
boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_0_2_1.overlay
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@ -1,7 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "nrf54l15pdk_nrf54l15_common_0_2_1.dtsi"

31
boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_defconfig
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@ -1,31 +0,0 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable GPIO
CONFIG_GPIO=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# MPU-based null-pointer dereferencing detection cannot
# be applied as the (0x0 - 0x400) is unmapped for this target.
CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
# Enable Cache
CONFIG_CACHE_MANAGEMENT=y
CONFIG_EXTERNAL_CACHE=y
CONFIG_SOC_NRF_FORCE_CONSTLAT=y
# Start SYSCOUNTER on driver init
CONFIG_NRF_GRTC_START_SYSCOUNTER=y

71
boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuflpr.dts
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@ -1,71 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <nordic/nrf54l15_enga_cpuflpr.dtsi>
#include "nrf54l15pdk_nrf54l15-common.dtsi"
/ {
model = "Nordic nRF54L15 PDK nRF54L15 FLPR MCU";
compatible = "nordic,nrf54l15pdk_nrf54l15-cpuflpr";
chosen {
zephyr,console = &uart30;
zephyr,shell-uart = &uart30;
zephyr,code-partition = &cpuflpr_code_partition;
zephyr,flash = &cpuflpr_rram;
zephyr,sram = &cpuflpr_sram;
};
};
&cpuflpr_sram {
status = "okay";
/* size must be increased due to booting from SRAM */
reg = <0x20028000 DT_SIZE_K(96)>;
ranges = <0x0 0x20028000 0x18000>;
};
&cpuflpr_rram {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
cpuflpr_code_partition: partition@0 {
label = "image-0";
reg = <0x0 DT_SIZE_K(96)>;
};
};
};
&grtc {
owned-channels = <3 4>;
status = "okay";
};
&uart30 {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&gpiote20 {
status = "okay";
};
&gpiote30 {
status = "okay";
};

18
boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuflpr.yaml
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@ -1,18 +0,0 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
identifier: nrf54l15pdk/nrf54l15/cpuflpr
name: nRF54L15-PDK-nRF54L15-Fast-Lightweight-Peripheral-Processor
type: mcu
arch: riscv
toolchain:
- zephyr
sysbuild: true
ram: 96
flash: 96
supported:
- counter
- gpio
- i2c
- spi
- watchdog

7
boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuflpr_0_2_1.overlay
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@ -1,7 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "nrf54l15pdk_nrf54l15_common_0_2_1.dtsi"

17
boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuflpr_defconfig
View file

@ -1,17 +0,0 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable GPIO
CONFIG_GPIO=y
CONFIG_USE_DT_CODE_PARTITION=y
# Execute from SRAM
CONFIG_XIP=n

12
boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuflpr_xip.dts
View file

@ -1,12 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "nrf54l15pdk_nrf54l15_cpuflpr.dts"
&cpuflpr_sram {
reg = <0x2002f000 DT_SIZE_K(68)>;
ranges = <0x0 0x2002f000 0x11000>;
};

18
boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuflpr_xip.yaml
View file

@ -1,18 +0,0 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
identifier: nrf54l15pdk/nrf54l15/cpuflpr/xip
name: nRF54L15-PDK-nRF54L15-Fast-Lightweight-Peripheral-Processor (RRAM XIP)
type: mcu
arch: riscv
toolchain:
- zephyr
sysbuild: true
ram: 68
flash: 96
supported:
- counter
- gpio
- i2c
- spi
- watchdog

7
boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuflpr_xip_0_2_1.overlay
View file

@ -1,7 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "nrf54l15pdk_nrf54l15_common_0_2_1.dtsi"

15
boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuflpr_xip_defconfig
View file

@ -1,15 +0,0 @@
# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable GPIO
CONFIG_GPIO=y
# Execute from RRAM
CONFIG_XIP=y

1
doc/releases/release-notes-4.0.rst
View file

@ -151,6 +151,7 @@ Boards & SoC Support
* Support for Google Kukui EC board (``google_kukui``) has been dropped.
* STM32: Deprecated MCO configuration via Kconfig in favour of setting it through devicetree.
See ``samples/boards/stm32/mco`` sample.
* Removed the ``nrf54l15pdk`` board, use :ref:`nrf54l15dk_nrf54l15` instead.
* Added support for the following shields:

1
samples/bluetooth/beacon/sample.yaml
View file

@ -9,7 +9,6 @@ tests:
- nrf51dk/nrf51822
- nrf52dk/nrf52832
- nrf54l15dk/nrf54l15/cpuapp
- nrf54l15pdk/nrf54l15/cpuapp
tags: bluetooth
integration_platforms:
- qemu_cortex_m3

12
samples/bluetooth/hci_uart/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
View file

@ -1,12 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
&uart20 {
compatible = "nordic,nrf-uarte";
current-speed = <1000000>;
status = "okay";
hw-flow-control;
};

33
samples/bluetooth/hci_uart/boards/nrf54l15pdk_nrf54l15_cpuapp_df.overlay
View file

@ -1,33 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
&uart20 {
compatible = "nordic,nrf-uarte";
current-speed = <1000000>;
status = "okay";
hw-flow-control;
};
&radio {
status = "okay";
/* This is an example number of antennas that may be available
* on antenna matrix board.
*/
dfe-antenna-num = <10>;
/* This is an example switch pattern that will be used to set an
* antenna for Tx PDU (period before start of Tx CTE).
*/
dfe-pdu-antenna = <0x0>;
/* These are example GPIO pin numbers that are provided to
* Radio peripheral. The pins will be acquired by Radio to
* drive antenna switching when AoD is enabled.
*/
dfegpio0-gpios = <&gpio1 4 0>;
dfegpio1-gpios = <&gpio1 5 0>;
dfegpio2-gpios = <&gpio1 6 0>;
dfegpio3-gpios = <&gpio1 7 0>;
};

11
samples/bluetooth/hci_uart/sample.yaml
View file

@ -98,14 +98,3 @@ tests:
tags:
- uart
- bluetooth
sample.bluetooth.hci_uart.nrf54l15pdk.all:
harness: bluetooth
platform_allow: nrf54l15pdk/nrf54l15/cpuapp
integration_platforms:
- nrf54l15pdk/nrf54l15/cpuapp
extra_args:
- OVERLAY_CONFIG=overlay-all-bt_ll_sw_split.conf
- DTC_OVERLAY_FILE=./boards/nrf54l15pdk_nrf54l15_cpuapp_df.overlay
tags:
- uart
- bluetooth

1
samples/bluetooth/peripheral_hr/sample.yaml
View file

@ -14,7 +14,6 @@ tests:
- nrf52840dk/nrf52840
- nrf5340dk/nrf5340/cpuapp
- nrf54l15dk/nrf54l15/cpuapp
- nrf54l15pdk/nrf54l15/cpuapp
integration_platforms:
- qemu_cortex_m3
- nrf52_bsim

9
samples/drivers/jesd216/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
View file

@ -1,9 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
&mx25r64 {
status = "okay";
};

1
samples/drivers/mbox/CMakeLists.txt
View file

@ -21,7 +21,6 @@ if(CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP OR
CONFIG_BOARD_ESP32S3_DEVKITM_ESP32S3_PROCPU OR
CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR
CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD OR
CONFIG_BOARD_NRF54L15PDK_NRF54L15_CPUAPP OR
CONFIG_BOARD_NRF54L15DK_NRF54L15_CPUAPP OR
CONFIG_BOARD_STM32H747I_DISCO_STM32H747XX_M7)
message(STATUS "${BOARD}${BOARD_QUALIFIERS} compile as Main in this sample")

1
samples/drivers/mbox/Kconfig.sysbuild
View file

@ -15,7 +15,6 @@ config REMOTE_BOARD
default "mimxrt1160_evk/mimxrt1166/cm4" if $(BOARD) = "mimxrt1160_evk"
default "lpcxpresso55s69/lpc55s69/cpu1" if $(BOARD) = "lpcxpresso55s69"
default "nrf54h20dk/nrf54h20/cpuapp" if "$(BOARD)${BOARD_QUALIFIERS}" = "nrf54h20dk/nrf54h20/cpurad"
default "nrf54l15pdk/nrf54l15/cpuflpr" if $(BOARD) = "nrf54l15pdk"
default "nrf54l15dk/nrf54l15/cpuflpr" if $(BOARD) = "nrf54l15dk"
default "stm32h747i_disco/stm32h747xx/m4" if $(BOARD) = "stm32h747i_disco"
default "esp32_devkitc_wroom/esp32/appcpu" if "$(BOARD)${BOARD_QUALIFIERS}" = "esp32_devkitc_wroom/esp32/procpu"

20
samples/drivers/mbox/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
View file

@ -1,20 +0,0 @@
/*
* Copyright 2024 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
/ {
mbox-consumer {
compatible = "vnd,mbox-consumer";
mboxes = <&cpuapp_vevif_rx 15>, <&cpuapp_vevif_tx 16>;
mbox-names = "rx", "tx";
};
};
&cpuapp_vevif_rx {
status = "okay";
};
&cpuapp_vevif_tx {
status = "okay";
};

2
samples/drivers/mbox/remote/CMakeLists.txt
View file

@ -20,8 +20,6 @@ if(CONFIG_BOARD_NRF5340DK_NRF5340_CPUNET OR
CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUPPR OR
CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUFLPR OR
CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR
CONFIG_BOARD_NRF54L15PDK_NRF54L15_CPUFLPR OR
CONFIG_BOARD_NRF54L15PDK_NRF54L15_CPUFLPR_XIP OR
CONFIG_BOARD_NRF54L15DK_NRF54L15_CPUFLPR OR
CONFIG_BOARD_STM32H747I_DISCO_STM32H747XX_M4)
message(STATUS "${BOARD}${BOARD_QUALIFIERS} compile as remote in this sample")

24
samples/drivers/mbox/remote/boards/nrf54l15pdk_nrf54l15_cpuflpr.overlay
View file

@ -1,24 +0,0 @@
/*
* Copyright 2024 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
/ {
mbox-consumer {
compatible = "vnd,mbox-consumer";
mboxes = <&cpuflpr_vevif_rx 16>, <&cpuflpr_vevif_tx 15>;
mbox-names = "rx", "tx";
};
};
&cpuflpr_vevif_rx {
status = "okay";
};
&cpuflpr_vevif_tx {
status = "okay";
};
&uart30 {
/delete-property/ hw-flow-control;
};

24
samples/drivers/mbox/remote/boards/nrf54l15pdk_nrf54l15_cpuflpr_xip.overlay
View file

@ -1,24 +0,0 @@
/*
* Copyright 2024 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
/ {
mbox-consumer {
compatible = "vnd,mbox-consumer";
mboxes = <&cpuflpr_vevif_rx 16>, <&cpuflpr_vevif_tx 15>;
mbox-names = "rx", "tx";
};
};
&cpuflpr_vevif_rx {
status = "okay";
};
&cpuflpr_vevif_tx {
status = "okay";
};
&uart30 {
/delete-property/ hw-flow-control;
};

9
samples/drivers/spi_flash/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
View file

@ -1,9 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
&mx25r64 {
status = "okay";
};

8
samples/drivers/watchdog/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
View file

@ -1,8 +0,0 @@
/*
* Copyright 2024 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
&wdt31 {
status = "okay";
};

8
samples/drivers/watchdog/boards/nrf54l15pdk_nrf54l15_cpuflpr.overlay
View file

@ -1,8 +0,0 @@
/*
* Copyright 2024 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
&wdt31 {
status = "okay";
};

8
samples/drivers/watchdog/boards/nrf54l15pdk_nrf54l15_cpuflpr_xip.overlay
View file

@ -1,8 +0,0 @@
/*
* Copyright 2024 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
&wdt31 {
status = "okay";
};

12
samples/subsys/fs/fs_sample/boards/nrf54l15pdk_nrf54l15_cpuapp.conf
View file

@ -1,12 +0,0 @@
#
# Copyright (c) 2024 Nordic Semiconductor ASA
#
# SPDX-License-Identifier: Apache-2.0
#
CONFIG_DISK_DRIVERS=y
CONFIG_DISK_DRIVER_FLASH=y
# There may be no files on internal SoC flash, so this Kconfig
# options has ben enabled to create some if listing does not
# find in the first place.
CONFIG_FS_SAMPLE_CREATE_SOME_ENTRIES=y

45
samples/subsys/fs/fs_sample/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
View file

@ -1,45 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Because FAT FS needs at least 64kiB partition and default
* storage_partition is 36kiB for this board, we need to reorganize
* partitions to get at least 64KiB.
*/
/delete-node/ &slot0_partition;
/delete-node/ &slot1_partition;
/delete-node/ &slot0_ns_partition;
/delete-node/ &slot1_ns_partition;
/delete-node/ &storage_partition;
&cpuapp_rram {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
slot0_partition: parition@10000 {
reg = <0x00010000 DT_SIZE_K(300)>;
};
slot1_partition: partition@5b000 {
reg = <0x0005b000 DT_SIZE_K(300)>;
};
storage_partition: partition@a6000 {
label = "storage";
reg = <0x000a6000 DT_SIZE_K(128)>;
};
};
};
/ {
msc_disk0 {
status="okay";
compatible = "zephyr,flash-disk";
partition = <&storage_partition>;
disk-name = "SD";
cache-size = <512>;
};
};

3
samples/subsys/fs/fs_sample/sample.yaml
View file

@ -55,9 +55,6 @@ tests:
extra_args:
- EXTRA_CONF_FILE=boards/nrf52840dk_nrf52840_ram_disk.conf
- DTC_OVERLAY_FILE=boards/nrf52840dk_nrf52840_ram_disk_region.overlay
sample.filesystem.fat_fs.nrf54l15pdk:
build_only: true
platform_allow: nrf54l15pdk/nrf54l15/cpuapp
sample.filesystem.fat_fs.nrf54l15dk:
build_only: true
platform_allow: nrf54l15dk/nrf54l15/cpuapp

1
samples/subsys/fs/littlefs/sample.yaml
View file

@ -24,7 +24,6 @@ tests:
- stm32h747i_disco/stm32h747xx/m7
- stm32h750b_dk
- nrf54l15dk/nrf54l15/cpuapp
- nrf54l15pdk/nrf54l15/cpuapp
- frdm_ke17z
- frdm_ke17z512
integration_platforms:

3
samples/subsys/ipc/ipc_service/icmsg/CMakeLists.txt
View file

@ -11,8 +11,7 @@ find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
if(NOT CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP AND
NOT CONFIG_BOARD_NRF5340BSIM_NRF5340_CPUAPP AND
NOT CONFIG_BOARD_STM32H747I_DISCO AND
NOT CONFIG_BOARD_NRF54L15DK_NRF54L15_CPUAPP AND
NOT CONFIG_BOARD_NRF54L15PDK_NRF54L15_CPUAPP)
NOT CONFIG_BOARD_NRF54L15DK_NRF54L15_CPUAPP)
message(FATAL_ERROR "${BOARD} is not supported for this sample")
endif()

1
samples/subsys/ipc/ipc_service/icmsg/Kconfig.sysbuild
View file

@ -8,6 +8,5 @@ config REMOTE_BOARD
string
default "nrf5340dk/nrf5340/cpunet" if $(BOARD) = "nrf5340dk"
default "nrf5340bsim/nrf5340/cpunet" if $(BOARD) = "nrf5340bsim"
default "nrf54l15pdk/nrf54l15/cpuflpr" if $(BOARD) = "nrf54l15pdk"
default "nrf54l15dk/nrf54l15/cpuflpr" if $(BOARD) = "nrf54l15dk"
default "stm32h747i_disco/stm32h747xx/m4" if $(BOARD) = "stm32h747i_disco"

41
samples/subsys/ipc/ipc_service/icmsg/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
View file

@ -1,41 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/ {
soc {
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
sram_rx: memory@20018000 {
reg = <0x20018000 0x0800>;
};
sram_tx: memory@20020000 {
reg = <0x20020000 0x0800>;
};
};
};
ipc {
ipc0: ipc0 {
compatible = "zephyr,ipc-icmsg";
tx-region = <&sram_tx>;
rx-region = <&sram_rx>;
mboxes = <&cpuapp_vevif_rx 15>, <&cpuapp_vevif_tx 16>;
mbox-names = "rx", "tx";
status = "okay";
};
};
};
&cpuapp_vevif_rx {
status = "okay";
};
&cpuapp_vevif_tx {
status = "okay";
};

45
samples/subsys/ipc/ipc_service/icmsg/remote/boards/nrf54l15pdk_nrf54l15_cpuflpr.overlay
View file

@ -1,45 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/ {
soc {
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
sram_tx: memory@20018000 {
reg = <0x20018000 0x0800>;
};
sram_rx: memory@20020000 {
reg = <0x20020000 0x0800>;
};
};
};
ipc {
ipc0: ipc0 {
compatible = "zephyr,ipc-icmsg";
tx-region = <&sram_tx>;
rx-region = <&sram_rx>;
mboxes = <&cpuflpr_vevif_rx 16>, <&cpuflpr_vevif_tx 15>;
mbox-names = "rx", "tx";
status = "okay";
};
};
};
&cpuflpr_vevif_rx {
status = "okay";
};
&cpuflpr_vevif_tx {
status = "okay";
};
&uart30 {
/delete-property/ hw-flow-control;
};

2
samples/subsys/settings/boards/nrf54l15pdk_nrf54l15_cpuapp.conf
View file

@ -1,2 +0,0 @@
CONFIG_NVS=y
CONFIG_SETTINGS_NVS=y

1
samples/subsys/settings/sample.yaml
View file

@ -11,7 +11,6 @@ tests:
- native_sim/native/64
- mr_canhubk3
- nrf54l15dk/nrf54l15/cpuapp
- nrf54l15pdk/nrf54l15/cpuapp
- nrf54h20dk/nrf54h20/cpuapp
integration_platforms:
- native_sim

9
samples/sysbuild/hello_world/sample.yaml
View file

@ -47,15 +47,6 @@ tests:
SB_CONF_FILE=sysbuild/nrf54h20dk_nrf54h20_cpuppr_xip.conf
hello_world_SNIPPET=nordic-ppr-xip
sample.sysbuild.hello_world.nrf54l15pdk_nrf54l15_cpuflpr:
platform_allow:
- nrf54l15pdk/nrf54l15/cpuapp
integration_platforms:
- nrf54l15pdk/nrf54l15/cpuapp
extra_args:
SB_CONF_FILE=sysbuild/nrf54l15pdk_nrf54l15_cpuflpr.conf
hello_world_SNIPPET=nordic-flpr
sample.sysbuild.hello_world.nrf54l15dk_nrf54l15_cpuflpr:
platform_allow:
- nrf54l15dk/nrf54l15/cpuapp

1
samples/sysbuild/hello_world/sysbuild/nrf54l15pdk_nrf54l15_cpuflpr.conf
View file

@ -1 +0,0 @@
SB_CONFIG_REMOTE_BOARD="nrf54l15pdk/nrf54l15/cpuflpr"

29
snippets/nordic-flpr-xip/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
View file

@ -1,29 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor
* SPDX-License-Identifier: Apache-2.0
*/
/ {
soc {
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
cpuflpr_code_partition: image@165000 {
/* FLPR core code partition */
reg = <0x165000 DT_SIZE_K(96)>;
};
};
};
};
&uart30 {
status = "reserved";
};
&cpuflpr_vpr {
execution-memory = <&cpuflpr_code_partition>;
};
&cpuapp_vevif_tx {
status = "okay";
};

3
snippets/nordic-flpr-xip/snippet.yml
View file

@ -3,9 +3,6 @@ append:
EXTRA_DTC_OVERLAY_FILE: nordic-flpr-xip.overlay
boards:
nrf54l15pdk/nrf54l15/cpuapp:
append:
EXTRA_DTC_OVERLAY_FILE: boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
nrf54l15dk/nrf54l15/cpuapp:
append:
EXTRA_DTC_OVERLAY_FILE: boards/nrf54l15dk_nrf54l15_cpuapp.overlay

43
snippets/nordic-flpr/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
View file

@ -1,43 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor
* SPDX-License-Identifier: Apache-2.0
*/
/ {
soc {
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
cpuflpr_code_partition: image@165000 {
/* FLPR core code partition */
reg = <0x165000 DT_SIZE_K(96)>;
};
};
cpuflpr_sram_code_data: memory@20028000 {
compatible = "mmio-sram";
reg = <0x20028000 DT_SIZE_K(96)>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x20028000 0x18000>;
};
};
};
&uart30 {
status = "reserved";
};
&cpuapp_sram {
reg = <0x20000000 DT_SIZE_K(160)>;
ranges = <0x0 0x20000000 0x28000>;
};
&cpuflpr_vpr {
execution-memory = <&cpuflpr_sram_code_data>;
source-memory = <&cpuflpr_code_partition>;
};
&cpuapp_vevif_tx {
status = "okay";
};

3
snippets/nordic-flpr/snippet.yml
View file

@ -3,9 +3,6 @@ append:
EXTRA_DTC_OVERLAY_FILE: nordic-flpr.overlay
boards:
nrf54l15pdk/nrf54l15/cpuapp:
append:
EXTRA_DTC_OVERLAY_FILE: boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
nrf54l15dk/nrf54l15/cpuapp:
append:
EXTRA_DTC_OVERLAY_FILE: boards/nrf54l15dk_nrf54l15_cpuapp.overlay

1
tests/boot/with_mcumgr/testcase.yaml
View file

@ -4,7 +4,6 @@ common:
- nrf52840dk/nrf52840
- nrf5340dk/nrf5340/cpuapp
- nrf54l15dk/nrf54l15/cpuapp
- nrf54l15pdk/nrf54l15/cpuapp
- nrf9160dk/nrf9160
- nucleo_wba55cg
integration_platforms:

43
tests/drivers/adc/adc_api/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
View file

@ -1,43 +0,0 @@
/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (c) 2024 Nordic Semiconductor ASA
*/
/ {
zephyr,user {
io-channels = <&adc 0>, <&adc 1> , <&adc 2>;
};
};
&adc {
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_INTERNAL";
zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 10)>;
zephyr,input-positive = <NRF_SAADC_AIN1>;
zephyr,resolution = <10>;
};
channel@1 {
reg = <1>;
zephyr,gain = "ADC_GAIN_1_4";
zephyr,reference = "ADC_REF_EXTERNAL0";
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
zephyr,input-positive = <NRF_SAADC_AIN4>;
zephyr,resolution = <12>;
};
channel@2 {
reg = <2>;
zephyr,gain = "ADC_GAIN_2_5";
zephyr,reference = "ADC_REF_INTERNAL";
zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 10)>;
zephyr,input-positive = <NRF_SAADC_AIN2>;
zephyr,resolution = <10>;
};
};

21
tests/drivers/gpio/gpio_basic_api/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
View file

@ -1,21 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/ {
resources {
compatible = "test-gpio-basic-api";
out-gpios = <&gpio1 10 0>;
in-gpios = <&gpio1 11 0>;
};
};
&gpiote20 {
status = "okay";
};
&gpio1 {
status = "okay";
};

21
tests/drivers/gpio/gpio_basic_api/boards/nrf54l15pdk_nrf54l15_cpuflpr.overlay
View file

@ -1,21 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/ {
resources {
compatible = "test-gpio-basic-api";
out-gpios = <&gpio1 10 0>;
in-gpios = <&gpio1 11 0>;
};
};
&gpiote20 {
status = "okay";
};
&gpio1 {
status = "okay";
};

21
tests/drivers/gpio/gpio_basic_api/boards/nrf54l15pdk_nrf54l15_cpuflpr_xip.overlay
View file

@ -1,21 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/ {
resources {
compatible = "test-gpio-basic-api";
out-gpios = <&gpio1 10 0>;
in-gpios = <&gpio1 11 0>;
};
};
&gpiote20 {
status = "okay";
};
&gpio1 {
status = "okay";
};

30
tests/drivers/i2s/i2s_api/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
View file

@ -1,30 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/* i2s-node0 is the transmitter/receiver */
/ {
aliases {
i2s-node0 = &i2s20;
};
};
&pinctrl {
i2s20_default_alt: i2s20_default_alt {
group1 {
psels = <NRF_PSEL(I2S_SCK_M, 1, 11)>,
<NRF_PSEL(I2S_LRCK_M, 1, 12)>,
<NRF_PSEL(I2S_SDOUT, 1, 8)>,
<NRF_PSEL(I2S_SDIN, 1, 9)>;
};
};
};
&i2s20 {
status = "okay";
pinctrl-0 = <&i2s20_default_alt>;
pinctrl-names = "default";
};

30
tests/drivers/i2s/i2s_speed/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
View file

@ -1,30 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/* i2s-node0 is the transmitter/receiver */
/ {
aliases {
i2s-node0 = &i2s20;
};
};
&pinctrl {
i2s20_default_alt: i2s20_default_alt {
group1 {
psels = <NRF_PSEL(I2S_SCK_M, 1, 11)>,
<NRF_PSEL(I2S_LRCK_M, 1, 12)>,
<NRF_PSEL(I2S_SDOUT, 1, 8)>,
<NRF_PSEL(I2S_SDIN, 1, 9)>;
};
};
};
&i2s20 {
status = "okay";
pinctrl-0 = <&i2s20_default_alt>;
pinctrl-names = "default";
};

23
tests/drivers/mbox/mbox_error_cases/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
View file

@ -1,23 +0,0 @@
/*
* Copyright 2024 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
/ {
mbox-consumer {
compatible = "vnd,mbox-consumer";
mboxes = <&cpuapp_vevif_tx 16>, <&cpuapp_vevif_tx 32>,
<&cpuapp_vevif_rx 15>, <&cpuapp_vevif_rx 32>;
mbox-names = "remote_valid", "remote_incorrect",
"local_valid", "local_incorrect";
};
};
&cpuapp_vevif_rx {
status = "okay";
};
&cpuapp_vevif_tx {
status = "okay";
};

1
tests/drivers/mbox/mbox_error_cases/sample.yaml
View file

@ -15,7 +15,6 @@ tests:
tests.drivers.mbox_error_cases.nrf54l:
platform_allow:
- nrf54l15dk/nrf54l15/cpuapp
- nrf54l15pdk/nrf54l15/cpuapp
integration_platforms:
- nrf54l15dk/nrf54l15/cpuapp
extra_args: SNIPPET=nordic-flpr

20
tests/drivers/pwm/pwm_api/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
View file

@ -1,20 +0,0 @@
&pinctrl {
pwm_default: pwm_default {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 1, 8)>;
};
};
pwm_sleep: pwm_sleep {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 1, 8)>;
low-power-enable;
};
};
};
&pwm20 {
status = "okay";
pinctrl-0 = <&pwm_default>;
pinctrl-1 = <&pwm_sleep>;
pinctrl-names = "default", "sleep";
};

3
tests/drivers/sensor/temp_sensor/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
View file

@ -1,3 +0,0 @@
temp_sensor: &temp {
status = "okay";
};

36
tests/drivers/uart/uart_async_api/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
View file

@ -1,36 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
&pinctrl {
uart21_default: uart21_default {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 10)>,
<NRF_PSEL(UART_RX, 1, 11)>;
};
};
uart21_sleep: uart21_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 10)>,
<NRF_PSEL(UART_RX, 1, 11)>;
low-power-enable;
};
};
};
/ {
chosen {
zephyr,console = &uart20;
};
};
dut: &uart21 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart21_default>;
pinctrl-1 = <&uart21_sleep>;
pinctrl-names = "default", "sleep";
};

30
tests/drivers/uart/uart_async_api/boards/nrf54l15pdk_nrf54l15_cpuflpr.overlay
View file

@ -1,30 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
&pinctrl {
uart21_default: uart21_default {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 10)>,
<NRF_PSEL(UART_RX, 1, 11)>;
};
};
uart21_sleep: uart21_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 10)>,
<NRF_PSEL(UART_RX, 1, 11)>;
low-power-enable;
};
};
};
dut: &uart21 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart21_default>;
pinctrl-1 = <&uart21_sleep>;
pinctrl-names = "default", "sleep";
};

54
tests/drivers/uart/uart_errors/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
View file

@ -1,54 +0,0 @@
/* SPDX-License-Identifier: Apache-2.0 */
&pinctrl {
uart21_default: uart21_default {
group1 {
psels = <NRF_PSEL(UART_RX, 1, 8)>,
<NRF_PSEL(UART_RTS, 1, 10)>;
};
};
uart21_sleep: uart21_sleep {
group1 {
psels = <NRF_PSEL(UART_RX, 1, 8)>,
<NRF_PSEL(UART_RTS, 1, 10)>;
low-power-enable;
};
};
uart22_default: uart22_default {
group1 {
psels =
<NRF_PSEL(UART_CTS, 1, 11)>;
bias-pull-up;
};
group2 {
psels = <NRF_PSEL(UART_TX, 1, 9)>;
};
};
uart22_sleep: uart22_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 9)>,
<NRF_PSEL(UART_CTS, 1, 11)>;
low-power-enable;
};
};
};
dut: &uart21 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart21_default>;
pinctrl-1 = <&uart21_sleep>;
pinctrl-names = "default", "sleep";
};
dut_aux: &uart22 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart22_default>;
pinctrl-1 = <&uart22_sleep>;
pinctrl-names = "default", "sleep";
disable-rx;
};

1
tests/lib/cpp/cxx/testcase.yaml
View file

@ -37,7 +37,6 @@ tests:
# Exclude nRF54L15, nRF54H20 and nRF9280 as Nordic HAL is not compatible with C++98.
# Exclude CONFIG_HAS_RENESAS_RA_FSP as Renesas RA HAL is not compatible with C++98.
platform_exclude:
- nrf54l15pdk/nrf54l15/cpuapp
- nrf54l15dk/nrf54l15/cpuapp
- nrf54l20pdk/nrf54l20/cpuapp
- nrf54h20dk/nrf54h20/cpuapp

1
tests/subsys/fs/fcb/testcase.yaml
View file

@ -13,7 +13,6 @@ tests:
filesystem.fcb.no_erase:
platform_allow:
- nrf54l15dk/nrf54l15/cpuapp
- nrf54l15pdk/nrf54l15/cpuapp
filesystem.fcb.native_sim.no_erase:
extra_args: CONFIG_FLASH_SIMULATOR_EXPLICIT_ERASE=n
platform_allow: native_sim

22
tests/subsys/fs/littlefs/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
View file

@ -1,22 +0,0 @@
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/delete-node/ &slot0_ns_partition;
/delete-node/ &slot1_partition;
/delete-node/ &slot1_ns_partition;
&cpuapp_rram {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
small_partition: partition@67000 {
label = "small";
reg = <0x00067000 0x00010000>;
};
};
};

2
tests/subsys/fs/littlefs/testcase.yaml
View file

@ -15,7 +15,7 @@ common:
tests:
filesystem.littlefs.default:
timeout: 60
platform_allow: nrf54l15dk/nrf54l15/cpuapp nrf54l15pdk/nrf54l15/cpuapp
platform_allow: nrf54l15dk/nrf54l15/cpuapp
filesystem.littlefs.custom:
timeout: 180
extra_configs:

1
tests/subsys/storage/stream/stream_flash/testcase.yaml
View file

@ -15,7 +15,6 @@ tests:
storage.stream_flash.no_explicit_erase:
platform_allow:
- nrf54l15dk/nrf54l15/cpuapp
- nrf54l15pdk/nrf54l15/cpuapp
storage.stream_flash.dword_wbs:
extra_args: DTC_OVERLAY_FILE=unaligned_flush.overlay
tags: stream_flash