soc/arm/silabs_exx32: fix PM implementation - wake up using BURTC timer
- Add Gecko BURTC sys_clock driver to handle wake up from EM2,3 states - Remove custom PM policy and dependency on HAL sl_power_manager service - EM1 supported in all configurations - EM2,3 supported only if SysTick is replaced by BURTC Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
This commit is contained in:
Roman Dobrodii
Carles Cufí
parent
bdb8024df3
commit
cb14d8b099
21 changed files with 491 additions and 136 deletions
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@ -21,6 +21,18 @@ config SOC_PART_NUMBER
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that you should not set directly. The part number selection choice defines
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the default value for this string.
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config SOC_GECKO_SERIES2
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bool
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help
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Set if we're building for Gecko Series 2 SoC.
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This is equivalent of _SILICON_LABS_32B_SERIES_2 definition in HAL
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code.
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config SOC_GECKO_BURTC
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bool
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help
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Set if the Back-Up Real Time Counter (BURTC) HAL module is used.
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config SOC_GECKO_CORE
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bool
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default y
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@ -163,6 +175,12 @@ config SOC_GECKO_CMU
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if SOC_GECKO_CMU
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config CMU_NEED_LFXO
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bool
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help
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Set if LFXO oscillator should be configured and enabled, potentially
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in on-demand mode, after SoC is initialized.
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choice
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prompt "High Frequency Clock Selection"
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default CMU_HFCLK_HFXO
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@ -175,6 +193,7 @@ config CMU_HFCLK_HFXO
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config CMU_HFCLK_LFXO
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bool "External low frequency crystal oscillator"
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select CMU_NEED_LFXO
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help
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Set this option to use the external low frequency crystal oscillator
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as high frequency clock.
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@ -186,6 +205,37 @@ config CMU_HFCLK_HFRCO
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endchoice
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choice
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prompt "BURTC Clock Selection"
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depends on SOC_GECKO_BURTC
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default CMU_BURTCCLK_LFRCO
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config CMU_BURTCCLK_LFXO
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bool "LFXO - external low frequency crystal oscillator"
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select CMU_NEED_LFXO
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help
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Set this option to use LFXO - the external low freqency crystal oscillator
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as BURTC clock.
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Frequency is set by external crystal, typically 32.768 kHz.
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config CMU_BURTCCLK_LFRCO
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bool "LFRCO - internal low frequency RC oscillator"
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help
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Set this option to use LFRCO - the internal low freqency RC oscillator
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as BURTC clock.
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Frequency is approximately 32.768 kHz.
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config CMU_BURTCCLK_ULFRCO
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bool "ULFRCO - internal ultra low frequency RC oscillator"
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help
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Set this option to use ULFRCO - the external low freqency crystal oscillator
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as BURTC clock.
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Frequency is approximately 1 kHz.
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endchoice
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config CMU_HFXO_FREQ
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int "External high frequency oscillator frequency"
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help
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@ -9,4 +9,7 @@ config SOC_GECKO_EMU
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select SOC_GECKO_CORE
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depends on PM
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config CORTEX_M_SYSTICK
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default n if GECKO_BURTC_TIMER
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endif
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@ -41,12 +41,44 @@ LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
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* @brief Initialization parameters for the external high frequency oscillator
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*/
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static CMU_HFXOInit_TypeDef hfxoInit = CMU_HFXOINIT_DEFAULT;
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#elif (defined CONFIG_CMU_HFCLK_LFXO)
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#endif
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#ifdef CONFIG_CMU_NEED_LFXO
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/**
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* @brief Initialization parameters for the external low frequency oscillator
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*/
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static CMU_LFXOInit_TypeDef lfxoInit = CMU_LFXOINIT_DEFAULT;
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#endif
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static void init_lfxo(void)
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{
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/*
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* Configuring LFXO disables it, so we can do that only if it's not
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* used as a SYSCLK/HFCLK source.
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*/
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#if defined(_SILICON_LABS_32B_SERIES_2)
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if (CMU_ClockSelectGet(cmuClock_SYSCLK) != cmuSelect_LFXO) {
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/*
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* Check if device has LFXO configuration info in DEVINFO
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* See AN0016.2
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*/
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if ((DEVINFO->MODULEINFO & DEVINFO_MODULEINFO_LFXOCALVAL) ==
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DEVINFO_MODULEINFO_LFXOCALVAL_VALID) {
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lfxoInit.capTune =
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(DEVINFO->MODXOCAL & _DEVINFO_MODXOCAL_LFXOCAPTUNE_MASK) >>
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_DEVINFO_MODXOCAL_LFXOCAPTUNE_SHIFT;
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}
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CMU_LFXOInit(&lfxoInit);
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}
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#else
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if (CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_LFXO) {
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CMU_LFXOInit(&lfxoInit);
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CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
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}
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#endif /* _SILICON_LABS_32B_SERIES_2 */
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SystemLFXOClockSet(CONFIG_CMU_LFXO_FREQ);
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}
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#endif /* CONFIG_CMU_NEED_LFXO */
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/**
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* @brief Initialize the system clock
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@ -85,29 +117,11 @@ static ALWAYS_INLINE void clock_init(void)
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CMU_OscillatorEnable(cmuOsc_HFRCO, false, false);
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#endif /* _SILICON_LABS_32B_SERIES_2 */
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#elif (defined CONFIG_CMU_HFCLK_LFXO)
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/* LFXO should've been already brought up by init_lfxo() */
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#if defined(_SILICON_LABS_32B_SERIES_2)
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if (CMU_ClockSelectGet(cmuClock_SYSCLK) != cmuSelect_LFXO) {
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/*
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* Start the LFXO Oscillator as well (use by RTCC)
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* Check if device has HFXO configuration info in DEVINFO
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* See AN0016.2
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*/
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if ((DEVINFO->MODULEINFO & DEVINFO_MODULEINFO_LFXOCALVAL) ==
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DEVINFO_MODULEINFO_LFXOCALVAL_VALID) {
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lfxoInit.capTune =
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(DEVINFO->MODXOCAL & _DEVINFO_MODXOCAL_LFXOCAPTUNE_MASK) >>
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_DEVINFO_MODXOCAL_LFXOCAPTUNE_SHIFT;
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}
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}
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SystemLFXOClockSet(CONFIG_CMU_LFXO_FREQ);
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CMU_ClockSelectSet(cmuClock_SYSCLK, cmuSelect_LFXO);
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#else
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if (CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_LFXO) {
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CMU_LFXOInit(&lfxoInit);
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CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
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CMU_ClockSelectSet(cmuClock_HF, cmuSelect_LFXO);
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}
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SystemLFXOClockSet(CONFIG_CMU_LFXO_FREQ);
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CMU_ClockSelectSet(cmuClock_HF, cmuSelect_LFXO);
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CMU_OscillatorEnable(cmuOsc_HFRCO, false, false);
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#endif /* _SILICON_LABS_32B_SERIES_2 */
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#elif (defined CONFIG_CMU_HFCLK_HFRCO)
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@ -204,6 +218,10 @@ static int silabs_exx32_init(void)
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/* handle chip errata */
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CHIP_Init();
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#ifdef CONFIG_CMU_NEED_LFXO
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init_lfxo();
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#endif
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#ifdef CONFIG_SOC_GECKO_DEV_INIT
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sl_device_init_dcdc();
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sl_device_init_hfxo();
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@ -215,7 +233,7 @@ static int silabs_exx32_init(void)
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sl_hfxo_manager_init();
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#endif
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#else
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#else /* !CONFIG_SOC_GECKO_DEV_INIT */
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#ifdef CONFIG_SOC_GECKO_EMU_DCDC
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dcdc_init();
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@ -234,7 +252,8 @@ static int silabs_exx32_init(void)
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/* Configure SWO debug output */
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swo_init();
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#endif
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#endif
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#endif /* !CONFIG_SOC_GECKO_DEV_INIT */
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/* restore interrupt state */
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irq_unlock(oldLevel);
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return 0;
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@ -9,25 +9,14 @@
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#include <zephyr/pm/pm.h>
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#include <em_emu.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/counter.h>
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LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
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#ifdef CONFIG_SOC_GECKO_DEV_INIT
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#include <sl_power_manager.h>
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static const struct device *const counter_dev = DEVICE_DT_GET(DT_NODELABEL(stimer0));
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static struct counter_alarm_cfg wakeup_cfg = {
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.callback = NULL
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};
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#endif
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/*
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* Power state map:
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* PM_STATE_RUNTIME_IDLE: EM1 Sleep
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* PM_STATE_SUSPEND_TO_IDLE: EM2 Deep Sleep
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* PM_STATE_STANDBY: EM3 Stop
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* PM_STATE_SOFT_OFF: EM4
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*/
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/* Invoke Low Power/System Off specific Tasks */
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@ -37,52 +26,6 @@ __weak void pm_state_set(enum pm_state state, uint8_t substate_id)
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LOG_DBG("SoC entering power state %d", state);
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#ifdef CONFIG_SOC_GECKO_DEV_INIT
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sl_power_manager_em_t energy_mode;
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/* Save RTCC IRQ priority */
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uint32_t rtcc_prio = NVIC_GetPriority(RTCC_IRQn);
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/*
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* When this function is entered the Kernel has disabled handling interrupts
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* with priority other than 0. The Interrupt for the timer used to wake up
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* the cpu has priority equal to 1. Manually set this priority to 0 so that
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* cpu could exit sleep state.
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*
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* Note on priority value: set priority to -1 because z_arm_irq_priority_set
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* offsets the priorities by 1.
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* This function call will effectively set the priority to 0.
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*/
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z_arm_irq_priority_set(RTCC_IRQn, -1, 0);
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switch (state) {
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case PM_STATE_STANDBY:
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energy_mode = SL_POWER_MANAGER_EM3;
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/* Limit sleep level to given state */
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sl_power_manager_add_em_requirement(energy_mode);
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counter_start(counter_dev);
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counter_set_channel_alarm(counter_dev, 0, &wakeup_cfg);
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sl_power_manager_sleep();
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k_cpu_idle();
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counter_stop(counter_dev);
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/* Remove sleep level limit */
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sl_power_manager_remove_em_requirement(energy_mode);
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break;
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default:
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LOG_DBG("Unsupported power state %u", state);
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break;
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}
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LOG_DBG("SoC leaving power state %d", state);
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/* Restore RTCC IRQ priority */
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z_arm_irq_priority_set(RTCC_IRQn, (rtcc_prio - 1), 0);
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#else
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/* FIXME: When this function is entered the Kernel has disabled
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* interrupts using BASEPRI register. This is incorrect as it prevents
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* waking up from any interrupt which priority is not 0. Work around the
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@ -105,6 +48,9 @@ __weak void pm_state_set(enum pm_state state, uint8_t substate_id)
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case PM_STATE_STANDBY:
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EMU_EnterEM3(true);
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break;
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case PM_STATE_SOFT_OFF:
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EMU_EnterEM4();
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break;
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default:
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LOG_DBG("Unsupported power state %u", state);
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break;
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@ -114,8 +60,6 @@ __weak void pm_state_set(enum pm_state state, uint8_t substate_id)
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/* Clear PRIMASK */
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__enable_irq();
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#endif
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}
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/* Handle SOC specific activity after Low Power Mode Exit */
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@ -124,37 +68,3 @@ __weak void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
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ARG_UNUSED(state);
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ARG_UNUSED(substate_id);
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}
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#if defined(CONFIG_SOC_GECKO_DEV_INIT) && defined(CONFIG_PM_POLICY_CUSTOM)
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/* CONFIG_PM_POLICY_CUSTOM allows us to set the next alarm to a specific number
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* of ticks in the future. This is needed for the Gecko SleepTimer to wake up
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* the device properly.
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*/
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static const struct pm_state_info pm_min_residency[] =
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PM_STATE_INFO_LIST_FROM_DT_CPU(DT_NODELABEL(cpu0));
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struct pm_state_info pm_state_active = {PM_STATE_ACTIVE, 0, 0, 0};
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__weak struct pm_state_info *pm_policy_next_state(uint8_t cpu, int32_t ticks)
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{
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int i;
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for (i = ARRAY_SIZE(pm_min_residency) - 1; i >= 0; i--) {
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if ((ticks == K_TICKS_FOREVER) ||
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(ticks >= k_us_to_ticks_ceil32(
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pm_min_residency[i].min_residency_us))) {
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LOG_DBG("Selected power state %d "
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"(ticks: %d, min_residency: %u)",
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pm_min_residency[i].state, ticks,
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pm_min_residency[i].min_residency_us);
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/* Busy waiting for 1 tick to flush UART buffer */
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k_busy_wait(k_ticks_to_us_floor32(1));
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wakeup_cfg.ticks = ticks;
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return ((struct pm_state_info *) &pm_min_residency[i]);
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}
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}
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return (struct pm_state_info *)(&pm_state_active);
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}
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#endif
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@ -19,11 +19,6 @@ config PM
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select COUNTER
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select UART_INTERRUPT_DRIVEN
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choice PM_POLICY
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default PM_POLICY_CUSTOM
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depends on PM
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endchoice
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source "soc/arm/silabs_exx32/efr32bg22/Kconfig.defconfig.efr32bg22"
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endif # SOC_SERIES_EFR32BG22
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@ -15,6 +15,7 @@ config SOC_SERIES_EFR32BG22
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select HAS_SILABS_GECKO
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select HAS_SWO
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select SOC_FAMILY_EXX32
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select SOC_GECKO_SERIES2
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select SOC_GECKO_CMU
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select SOC_GECKO_CORE
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select SOC_GECKO_DEV_INIT
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@ -15,6 +15,7 @@ config SOC_SERIES_EFR32BG27
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select HAS_SILABS_GECKO
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select HAS_SWO
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select SOC_FAMILY_EXX32
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select SOC_GECKO_SERIES2
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select SOC_GECKO_CMU
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select SOC_GECKO_CORE
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select SOC_GECKO_DEV_INIT
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@ -12,6 +12,7 @@ config SOC_SERIES_EFR32MG21
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select CPU_HAS_FPU
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select CPU_HAS_ARM_MPU
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select SOC_FAMILY_EXX32
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select SOC_GECKO_SERIES2
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select HAS_SILABS_GECKO
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select HAS_SWO
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select SOC_GECKO_CMU
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@ -14,6 +14,7 @@ config SOC_SERIES_EFR32MG24
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select ARMV8_M_DSP
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select ARM_TRUSTZONE_M
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select SOC_FAMILY_EXX32
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select SOC_GECKO_SERIES2
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select HAS_SILABS_GECKO
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select HAS_SWO
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select SOC_GECKO_CMU
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