barriers: Move __DSB() to the new API

Remove the arch-specific ARM-centric __DSB() macro and use the new
barrier API instead.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>

arch/arm/core/aarch32/cortex_a_r/cache.c

@@ -15,6 +15,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/cache.h>
 #include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+#include <zephyr/sys/barrier.h>
 
 /* Cache Type Register */
 #define	CTR_DMINLINE_SHIFT	16
@@ -51,7 +52,7 @@ void arch_dcache_enable(void)
 
 	val = __get_SCTLR();
 	val |= SCTLR_C_Msk;
-	__DSB();
+	barrier_dsync_fence_full();
 	__set_SCTLR(val);
 	__ISB();
 }
@@ -62,7 +63,7 @@ void arch_dcache_disable(void)
 
 	val = __get_SCTLR();
 	val &= ~SCTLR_C_Msk;
-	__DSB();
+	barrier_dsync_fence_full();
 	__set_SCTLR(val);
 	__ISB();
 

arch/arm/core/aarch32/cortex_m/fault.c

@@ -17,6 +17,7 @@
 #include <inttypes.h>
 #include <zephyr/exc_handle.h>
 #include <zephyr/logging/log.h>
+#include <zephyr/sys/barrier.h>
 LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
 
 #if defined(CONFIG_PRINTK) || defined(CONFIG_LOG)
@@ -710,13 +711,13 @@ static inline bool z_arm_is_synchronous_svc(z_arch_esf_t *esf)
 	uint16_t fault_insn = *(ret_addr - 1);
 #else
 	SCB->CCR |= SCB_CCR_BFHFNMIGN_Msk;
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 
 	uint16_t fault_insn = *(ret_addr - 1);
 
 	SCB->CCR &= ~SCB_CCR_BFHFNMIGN_Msk;
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 #endif /* ARMV6_M_ARMV8_M_BASELINE && !ARMV8_M_BASELINE */
 

arch/arm/core/aarch32/cortex_m/scb.c

@@ -17,6 +17,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/arch/cpu.h>
 #include <zephyr/sys/util.h>
+#include <zephyr/sys/barrier.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/linker/linker-defs.h>
 #include <zephyr/cache.h>
@@ -132,7 +133,7 @@ void z_arm_init_arch_hw_at_boot(void)
 	/* Restore Interrupts */
 	__enable_irq();
 
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 }
 #endif /* CONFIG_INIT_ARCH_HW_AT_BOOT */

arch/arm/core/aarch32/irq_manage.c

@@ -23,6 +23,7 @@
 #include <zephyr/drivers/interrupt_controller/gic.h>
 #endif
 #include <zephyr/sys/__assert.h>
+#include <zephyr/sys/barrier.h>
 #include <zephyr/toolchain.h>
 #include <zephyr/linker/sections.h>
 #include <zephyr/sw_isr_table.h>
@@ -281,7 +282,7 @@ void irq_target_state_set_all_non_secure(void)
 		NVIC->ICER[i] = 0xFFFFFFFF;
 	}
 
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 
 	/* Set all NVIC interrupt lines to target Non-Secure */

arch/arm/core/aarch32/mmu/arm_mmu.c

@@ -27,6 +27,7 @@
 #include <zephyr/sys/__assert.h>
 #include <zephyr/sys/util.h>
 #include <zephyr/sys/mem_manage.h>
+#include <zephyr/sys/barrier.h>
 
 #include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
 
@@ -115,7 +116,7 @@ static void arm_mmu_l2_map_page(uint32_t va, uint32_t pa,
 static void invalidate_tlb_all(void)
 {
 	__set_TLBIALL(0); /* 0 = opc2 = invalidate entire TLB */
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 }
 

arch/arm/core/aarch32/mpu/arm_mpu.c

@@ -152,7 +152,7 @@ void arm_core_mpu_enable(void)
 	__set_SCTLR(val);
 
 	/* Make sure that all the registers are set before proceeding */
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 }
 
@@ -164,14 +164,14 @@ void arm_core_mpu_disable(void)
 	uint32_t val;
 
 	/* Force any outstanding transfers to complete before disabling MPU */
-	__DSB();
+	barrier_dsync_fence_full();
 
 	val = __get_SCTLR();
 	val &= ~SCTLR_MPU_ENABLE;
 	__set_SCTLR(val);
 
 	/* Make sure that all the registers are set before proceeding */
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 }
 #else
@@ -190,7 +190,7 @@ void arm_core_mpu_enable(void)
 #endif
 
 	/* Make sure that all the registers are set before proceeding */
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 }
 

arch/arm/core/aarch32/mpu/arm_mpu_v8_internal.h

@@ -12,6 +12,7 @@
 #define LOG_LEVEL CONFIG_MPU_LOG_LEVEL
 #include <zephyr/logging/log.h>
 #include <zephyr/sys/math_extras.h>
+#include <zephyr/sys/barrier.h>
 
 /**
  * @brief internal structure holding information of
@@ -79,20 +80,20 @@ static inline void mpu_clear_region(uint32_t rnr)
 static inline void mpu_set_mair0(uint32_t mair0)
 {
 	write_mair0(mair0);
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 }
 
 static inline void mpu_set_rnr(uint32_t rnr)
 {
 	write_prselr(rnr);
-	__DSB();
+	barrier_dsync_fence_full();
 }
 
 static inline void mpu_set_rbar(uint32_t rbar)
 {
 	write_prbar(rbar);
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 }
 
@@ -104,7 +105,7 @@ static inline uint32_t mpu_get_rbar(void)
 static inline void mpu_set_rlar(uint32_t rlar)
 {
 	write_prlar(rlar);
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 }
 

arch/arm/core/aarch32/mpu/nxp_mpu.c

@@ -399,7 +399,7 @@ void arm_core_mpu_enable(void)
 	SYSMPU->CESR |= SYSMPU_CESR_VLD_MASK;
 
 	/* Make sure that all the registers are set before proceeding */
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 }
 

arch/arm/core/aarch32/prep_c.c

@@ -19,6 +19,7 @@
 #include <zephyr/kernel.h>
 #include <kernel_internal.h>
 #include <zephyr/linker/linker-defs.h>
+#include <zephyr/sys/barrier.h>
 
 #if !defined(CONFIG_CPU_CORTEX_M)
 #include <zephyr/arch/arm/aarch32/cortex_a_r/lib_helpers.h>
@@ -53,7 +54,7 @@ void *_vector_table_pointer;
 static inline void relocate_vector_table(void)
 {
 	SCB->VTOR = VECTOR_ADDRESS & SCB_VTOR_TBLOFF_Msk;
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 }
 
@@ -149,7 +150,7 @@ static inline void z_arm_floating_point_init(void)
 	/* Make the side-effects of modifying the FPCCR be realized
 	 * immediately.
 	 */
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 
 	/* Initialize the Floating Point Status and Control Register. */

arch/arm64/core/cortex_r/arm_mpu.c

@@ -76,7 +76,7 @@ void arm_core_mpu_enable(void)
 	val = read_sctlr_el1();
 	val |= SCTLR_M_BIT;
 	write_sctlr_el1(val);
-	dsb();
+	barrier_dsync_fence_full();
 	isb();
 }
 
@@ -93,7 +93,7 @@ void arm_core_mpu_disable(void)
 	val = read_sctlr_el1();
 	val &= ~SCTLR_M_BIT;
 	write_sctlr_el1(val);
-	dsb();
+	barrier_dsync_fence_full();
 	isb();
 }
 
@@ -112,7 +112,7 @@ static void mpu_init(void)
 	uint64_t mair = MPU_MAIR_ATTRS;
 
 	write_mair_el1(mair);
-	dsb();
+	barrier_dsync_fence_full();
 	isb();
 }
 
@@ -120,10 +120,10 @@ static inline void mpu_set_region(uint32_t rnr, uint64_t rbar,
 				  uint64_t rlar)
 {
 	write_prselr_el1(rnr);
-	dsb();
+	barrier_dsync_fence_full();
 	write_prbar_el1(rbar);
 	write_prlar_el1(rlar);
-	dsb();
+	barrier_dsync_fence_full();
 	isb();
 }
 

arch/arm64/core/fpu.c

@@ -9,6 +9,7 @@
 #include <zephyr/kernel_structs.h>
 #include <kernel_arch_interface.h>
 #include <zephyr/arch/cpu.h>
+#include <zephyr/sys/barrier.h>
 
 /* to be found in fpu.S */
 extern void z_arm64_fpu_save(struct z_arm64_fp_context *saved_fp_context);
@@ -78,7 +79,7 @@ void z_arm64_flush_local_fpu(void)
 		/* save current owner's content */
 		z_arm64_fpu_save(&owner->arch.saved_fp_context);
 		/* make sure content made it to memory before releasing */
-		dsb();
+		barrier_dsync_fence_full();
 		/* release ownership */
 		_current_cpu->arch.fpu_owner = NULL;
 		DBG("disable", owner);
@@ -125,7 +126,7 @@ static void flush_owned_fpu(struct k_thread *thread)
 			if (thread == _current) {
 				z_arm64_flush_local_fpu();
 				while (_kernel.cpus[i].arch.fpu_owner == thread) {
-					dsb();
+					barrier_dsync_fence_full();
 				}
 			}
 		}
@@ -236,7 +237,7 @@ void z_arm64_fpu_trap(z_arch_esf_t *esf)
 
 	if (owner) {
 		z_arm64_fpu_save(&owner->arch.saved_fp_context);
-		dsb();
+		barrier_dsync_fence_full();
 		_current_cpu->arch.fpu_owner = NULL;
 		DBG("save", owner);
 	}

arch/arm64/core/smp.c

@@ -22,6 +22,7 @@
 #include <zephyr/drivers/interrupt_controller/gic.h>
 #include <zephyr/drivers/pm_cpu_ops.h>
 #include <zephyr/sys/arch_interface.h>
+#include <zephyr/sys/barrier.h>
 #include <zephyr/irq.h>
 #include "boot.h"
 
@@ -87,7 +88,7 @@ void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
 	arm64_cpu_boot_params.arg = arg;
 	arm64_cpu_boot_params.cpu_num = cpu_num;
 
-	dsb();
+	barrier_dsync_fence_full();
 
 	/* store mpid last as this is our synchronization point */
 	arm64_cpu_boot_params.mpid = cpu_mpid;
@@ -139,7 +140,7 @@ void z_arm64_secondary_start(void)
 
 	fn = arm64_cpu_boot_params.fn;
 	arg = arm64_cpu_boot_params.arg;
-	dsb();
+	barrier_dsync_fence_full();
 
 	/*
 	 * Secondary core clears .fn to announce its presence.
@@ -147,7 +148,7 @@ void z_arm64_secondary_start(void)
 	 * arm64_cpu_boot_params afterwards.
 	 */
 	arm64_cpu_boot_params.fn = NULL;
-	dsb();
+	barrier_dsync_fence_full();
 	sev();
 
 	fn(arg);

drivers/cache/cache_aspeed.c

@@ -7,6 +7,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/drivers/syscon.h>
+#include <zephyr/sys/barrier.h>
 
 /*
  * cache area control: each bit controls 32KB cache area
@@ -145,10 +146,10 @@ int cache_data_invd_all(void)
 	ctrl &= ~DCACHE_CLEAN;
 	syscon_write_reg(dev, CACHE_FUNC_CTRL_REG, ctrl);
 
-	__DSB();
+	barrier_dsync_fence_full();
 	ctrl |= DCACHE_CLEAN;
 	syscon_write_reg(dev, CACHE_FUNC_CTRL_REG, ctrl);
-	__DSB();
+	barrier_dsync_fence_full();
 
 	/* exit critical section */
 	if (!k_is_in_isr()) {
@@ -181,7 +182,7 @@ int cache_data_invd_range(void *addr, size_t size)
 		syscon_write_reg(dev, CACHE_INVALID_REG, DCACHE_INVALID(aligned_addr));
 		aligned_addr += CACHE_LINE_SIZE;
 	}
-	__DSB();
+	barrier_dsync_fence_full();
 
 	/* exit critical section */
 	if (!k_is_in_isr()) {
@@ -242,7 +243,7 @@ int cache_instr_invd_range(void *addr, size_t size)
 		syscon_write_reg(dev, CACHE_INVALID_REG, ICACHE_INVALID(aligned_addr));
 		aligned_addr += CACHE_LINE_SIZE;
 	}
-	__DSB();
+	barrier_dsync_fence_full();
 
 	/* exit critical section */
 	if (!k_is_in_isr()) {

drivers/clock_control/clock_control_mchp_xec.c

@@ -15,6 +15,7 @@
 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
 #include <zephyr/irq.h>
 #include <zephyr/logging/log.h>
+#include <zephyr/sys/barrier.h>
 LOG_MODULE_REGISTER(clock_control_xec, LOG_LEVEL_ERR);
 
 #define CLK32K_SIL_OSC_DELAY		256
@@ -765,7 +766,7 @@ static void xec_clock_control_core_clock_divider_set(uint8_t clkdiv)
 	arch_nop();
 	arch_nop();
 	arch_nop();
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 }
 

drivers/counter/counter_mcux_gpt.c

@@ -11,6 +11,7 @@
 #include <zephyr/irq.h>
 #include <fsl_gpt.h>
 #include <zephyr/logging/log.h>
+#include <zephyr/sys/barrier.h>
 
 LOG_MODULE_REGISTER(mcux_gpt, CONFIG_COUNTER_LOG_LEVEL);
 
@@ -114,7 +115,7 @@ void mcux_gpt_isr(const struct device *dev)
 	status =  GPT_GetStatusFlags(config->base, kGPT_OutputCompare1Flag |
 				     kGPT_RollOverFlag);
 	GPT_ClearStatusFlags(config->base, status);
-	__DSB();
+	barrier_dsync_fence_full();
 
 	if ((status & kGPT_OutputCompare1Flag) && data->alarm_callback) {
 		GPT_DisableInterrupts(config->base,

drivers/counter/counter_mcux_qtmr.c

@@ -18,6 +18,7 @@
 #include <zephyr/irq.h>
 #include <fsl_qtmr.h>
 #include <zephyr/logging/log.h>
+#include <zephyr/sys/barrier.h>
 
 LOG_MODULE_REGISTER(mcux_qtmr, CONFIG_COUNTER_LOG_LEVEL);
 
@@ -57,7 +58,7 @@ void mcux_qtmr_timer_handler(const struct device *dev, uint32_t status)
 	uint32_t current = QTMR_GetCurrentTimerCount(config->base, config->channel);
 
 	QTMR_ClearStatusFlags(config->base, config->channel, status);
-	__DSB();
+	barrier_dsync_fence_full();
 
 	if ((status & kQTMR_Compare1Flag) && data->alarm_callback) {
 		QTMR_DisableInterrupts(config->base, config->channel,

drivers/display/display_stm32_ltdc.c

@@ -17,6 +17,7 @@
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
 #include <zephyr/drivers/clock_control.h>
 #include <zephyr/pm/device.h>
+#include <zephyr/sys/barrier.h>
 
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(display_stm32_ltdc, CONFIG_DISPLAY_LOG_LEVEL);
@@ -61,7 +62,7 @@ LOG_MODULE_REGISTER(display_stm32_ltdc, CONFIG_DISPLAY_LOG_LEVEL);
 #define CACHE_CLEAN(addr, size)		SCB_CleanDCache_by_Addr((addr), (size))
 #else
 #define CACHE_INVALIDATE(addr, size)
-#define CACHE_CLEAN(addr, size)		__DSB()
+#define CACHE_CLEAN(addr, size)		barrier_dsync_fence_full();
 #endif /* __DCACHE_PRESENT == 1 */
 
 #else

drivers/dma/dma_mcux_edma.c

@@ -17,6 +17,7 @@
 #include <zephyr/sys/atomic.h>
 #include <zephyr/drivers/dma.h>
 #include <zephyr/drivers/clock_control.h>
+#include <zephyr/sys/barrier.h>
 
 #include "dma_mcux_edma.h"
 
@@ -147,7 +148,7 @@ static void dma_mcux_edma_irq_handler(const struct device *dev)
 			EDMA_HandleIRQ(DEV_EDMA_HANDLE(dev, i));
 			LOG_DBG("IRQ DONE");
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
-			__DSB();
+			barrier_dsync_fence_full();
 #endif
 		}
 	}
@@ -170,7 +171,7 @@ static void dma_mcux_edma_error_irq_handler(const struct device *dev)
 	}
 
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
-	__DSB();
+	barrier_dsync_fence_full();
 #endif
 }
 

drivers/dma/dma_mcux_lpc.c

@@ -15,6 +15,7 @@
 #include <fsl_inputmux.h>
 #include <zephyr/logging/log.h>
 #include <zephyr/irq.h>
+#include <zephyr/sys/barrier.h>
 
 #define DT_DRV_COMPAT nxp_lpc_dma
 
@@ -85,7 +86,7 @@ static void dma_mcux_lpc_irq_handler(const struct device *dev)
  * to incorrect interrupt
  */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
-	__DSB();
+	barrier_dsync_fence_full();
 #endif
 }
 

drivers/entropy/entropy_smartbond.c

@@ -8,6 +8,7 @@
 #include <zephyr/kernel.h>
 #include <soc.h>
 #include <zephyr/irq.h>
+#include <zephyr/sys/barrier.h>
 #include <DA1469xAB.h>
 
 #define DT_DRV_COMPAT renesas_smartbond_trng
@@ -309,7 +310,7 @@ static int entropy_smartbond_get_entropy_isr(const struct device *dev, uint8_t *
 				 * DSB is recommended by spec before WFE (to
 				 * guarantee completion of memory transactions)
 				 */
-				__DSB();
+				barrier_dsync_fence_full();
 				__WFE();
 				__SEV();
 				__WFE();

drivers/entropy/entropy_stm32.c

@@ -27,6 +27,7 @@
 #include <zephyr/drivers/clock_control.h>
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
 #include <zephyr/irq.h>
+#include <zephyr/sys/barrier.h>
 #include "stm32_hsem.h"
 
 #define IRQN		DT_INST_IRQN(0)
@@ -313,7 +314,7 @@ static uint16_t generate_from_isr(uint8_t *buf, uint16_t len)
 			 * DSB is recommended by spec before WFE (to
 			 * guarantee completion of memory transactions)
 			 */
-			__DSB();
+			barrier_dsync_fence_full();
 			__WFE();
 			__SEV();
 			__WFE();

drivers/flash/flash_sam.c

@@ -14,6 +14,7 @@
 #include <zephyr/drivers/flash.h>
 #include <zephyr/init.h>
 #include <zephyr/kernel.h>
+#include <zephyr/sys/barrier.h>
 #include <soc.h>
 #include <string.h>
 
@@ -150,14 +151,14 @@ static int flash_sam_write_page(const struct device *dev, off_t offset,
 	for (; len > 0; len -= sizeof(*src)) {
 		*dst++ = *src++;
 		/* Assure data are written to the latch buffer consecutively */
-		__DSB();
+		barrier_dsync_fence_full();
 	}
 
 	/* Trigger the flash write */
 	efc->EEFC_FCR = EEFC_FCR_FKEY_PASSWD |
 			EEFC_FCR_FARG(flash_sam_get_page(offset)) |
 			EEFC_FCR_FCMD_WP;
-	__DSB();
+	barrier_dsync_fence_full();
 
 	/* Wait for the flash write to finish */
 	return flash_sam_wait_ready(dev);
@@ -256,7 +257,7 @@ static int flash_sam_erase_block(const struct device *dev, off_t offset)
 	efc->EEFC_FCR = EEFC_FCR_FKEY_PASSWD |
 			EEFC_FCR_FARG(flash_sam_get_page(offset) | 2) |
 			EEFC_FCR_FCMD_EPA;
-	__DSB();
+	barrier_dsync_fence_full();
 
 	return flash_sam_wait_ready(dev);
 }

drivers/flash/flash_stm32f1x.c

@@ -14,6 +14,7 @@ LOG_MODULE_REGISTER(flash_stm32generic, CONFIG_FLASH_LOG_LEVEL);
 #include <string.h>
 #include <zephyr/drivers/flash.h>
 #include <zephyr/init.h>
+#include <zephyr/sys/barrier.h>
 #include <soc.h>
 
 #include "flash_stm32.h"
@@ -63,7 +64,7 @@ static void erase_page_begin(FLASH_TypeDef *regs, unsigned int page)
 	regs->CR |= FLASH_CR_PER;
 	regs->AR = CONFIG_FLASH_BASE_ADDRESS + page * FLASH_PAGE_SIZE;
 
-	__DSB();
+	barrier_dsync_fence_full();
 
 	/* Set the STRT bit */
 	regs->CR |= FLASH_CR_STRT;
@@ -105,7 +106,7 @@ static void erase_page_begin(FLASH_TypeDef *regs, unsigned int page)
 	regs->PECR |= FLASH_PECR_ERASE;
 	regs->PECR |= FLASH_PECR_PROG;
 
-	__DSB();
+	barrier_dsync_fence_full();
 
 	*page_base = 0;
 }
@@ -148,7 +149,7 @@ static int write_value(const struct device *dev, off_t offset,
 	write_enable(regs);
 
 	/* Make sure the register write has taken effect */
-	__DSB();
+	barrier_dsync_fence_full();
 
 	/* Perform the data write operation at the desired memory address */
 	*flash = val;
@@ -194,7 +195,7 @@ int flash_stm32_block_erase_loop(const struct device *dev,
 
 	for (i = get_page(offset); i <= get_page(offset + len - 1); ++i) {
 		erase_page_begin(regs, i);
-		__DSB();
+		barrier_dsync_fence_full();
 		rc = flash_stm32_wait_flash_idle(dev);
 		erase_page_end(regs);
 

drivers/flash/flash_stm32f4x.c

@@ -12,6 +12,7 @@
 #include <zephyr/init.h>
 #include <zephyr/kernel.h>
 #include <zephyr/logging/log.h>
+#include <zephyr/sys/barrier.h>
 
 #include <soc.h>
 
@@ -232,7 +233,7 @@ static __unused int write_optb(const struct device *dev, uint32_t mask,
 	regs->OPTCR |= FLASH_OPTCR_OPTSTRT;
 
 	/* Make sure previous write is completed. */
-	__DSB();
+	barrier_dsync_fence_full();
 
 	rc = flash_stm32_wait_flash_idle(dev);
 	if (rc < 0) {

drivers/flash/flash_stm32f7x.c

@@ -10,6 +10,7 @@
 #include <string.h>
 #include <zephyr/drivers/flash.h>
 #include <zephyr/init.h>
+#include <zephyr/sys/barrier.h>
 #include <soc.h>
 
 #include "flash_stm32.h"
@@ -56,12 +57,12 @@ static int write_byte(const struct device *dev, off_t offset, uint8_t val)
 	regs->CR = (regs->CR & CR_PSIZE_MASK) |
 		   FLASH_PSIZE_BYTE | FLASH_CR_PG;
 	/* flush the register write */
-	__DSB();
+	barrier_dsync_fence_full();
 
 	/* write the data */
 	*((uint8_t *) offset + CONFIG_FLASH_BASE_ADDRESS) = val;
 	/* flush the register write */
-	__DSB();
+	barrier_dsync_fence_full();
 
 	rc = flash_stm32_wait_flash_idle(dev);
 	regs->CR &= (~FLASH_CR_PG);
@@ -105,7 +106,7 @@ static int erase_sector(const struct device *dev, uint32_t sector)
 		   (sector << FLASH_CR_SNB_Pos) |
 		   FLASH_CR_STRT;
 	/* flush the register write */
-	__DSB();
+	barrier_dsync_fence_full();
 
 	rc = flash_stm32_wait_flash_idle(dev);
 	regs->CR &= ~(FLASH_CR_SER | FLASH_CR_SNB);

drivers/flash/flash_stm32h7x.c

@@ -12,6 +12,7 @@
 #include <string.h>
 #include <zephyr/drivers/flash.h>
 #include <zephyr/init.h>
+#include <zephyr/sys/barrier.h>
 #include <soc.h>
 #include <stm32h7xx_ll_bus.h>
 #include <stm32h7xx_ll_utils.h>
@@ -262,7 +263,7 @@ static int erase_sector(const struct device *dev, int offset)
 		| ((sector.sector_index << FLASH_CR_SNB_Pos) & FLASH_CR_SNB));
 	*(sector.cr) |= FLASH_CR_START;
 	/* flush the register write */
-	__DSB();
+	barrier_dsync_fence_full();
 
 	rc = flash_stm32_wait_flash_idle(dev);
 	*(sector.cr) &= ~(FLASH_CR_SER | FLASH_CR_SNB);
@@ -338,14 +339,14 @@ static int write_ndwords(const struct device *dev,
 	*(sector.cr) |= FLASH_CR_PG;
 
 	/* Flush the register write */
-	__DSB();
+	barrier_dsync_fence_full();
 
 	/* Perform the data write operation at the desired memory address */
 	for (i = 0; i < n; ++i) {
 		flash[i] = data[i];
 
 		/* Flush the data write */
-		__DSB();
+		barrier_dsync_fence_full();
 
 		wait_write_queue(&sector);
 	}
@@ -569,14 +570,14 @@ static int flash_stm32h7_read(const struct device *dev, off_t offset,
 
 	__set_FAULTMASK(1);
 	SCB->CCR |= SCB_CCR_BFHFNMIGN_Msk;
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 
 	memcpy(data, (uint8_t *) CONFIG_FLASH_BASE_ADDRESS + offset, len);
 
 	__set_FAULTMASK(0);
 	SCB->CCR &= ~SCB_CCR_BFHFNMIGN_Msk;
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 	irq_unlock(irq_lock_key);
 

drivers/flash/soc_flash_mcux.c

@@ -11,6 +11,7 @@
 #include <errno.h>
 #include <zephyr/init.h>
 #include <soc.h>
+#include <zephyr/sys/barrier.h>
 #include "flash_priv.h"
 
 #include "fsl_common.h"
@@ -68,7 +69,7 @@ static uint32_t get_cmd_status(uint32_t cmd, uint32_t addr, size_t len)
 	p_fmc->STARTA = (addr>>4) & 0x3FFFF;
 	p_fmc->STOPA = ((addr+len-1)>>4) & 0x3FFFF;
 	p_fmc->CMD = cmd;
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 
 	/* wait for command to be done */

drivers/i2s/i2s_mcux_sai.c

@@ -20,6 +20,7 @@
 #include <zephyr/drivers/pinctrl.h>
 #include <zephyr/drivers/clock_control.h>
 #include <zephyr/dt-bindings/clock/imx_ccm.h>
+#include <zephyr/sys/barrier.h>
 #include <soc.h>
 
 #include "i2s_mcux_sai.h"
@@ -1114,7 +1115,7 @@ static void i2s_mcux_isr(void *arg)
 	 *  might vector to incorrect interrupt
 	 */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
-	__DSB();
+	barrier_dsync_fence_full();
 #endif
 }
 

drivers/interrupt_controller/intc_gic.c

@@ -15,6 +15,7 @@
 #include <zephyr/sw_isr_table.h>
 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
 #include <zephyr/drivers/interrupt_controller/gic.h>
+#include <zephyr/sys/barrier.h>
 
 static const uint64_t cpu_mpid_list[] = {
 	DT_FOREACH_CHILD_STATUS_OKAY_SEP(DT_PATH(cpus), DT_REG_ADDR, (,))
@@ -96,7 +97,7 @@ void arm_gic_eoi(unsigned int irq)
 	 * and the barrier is the best core can do by which execution of further
 	 * instructions waits till the barrier is alive.
 	 */
-	__DSB();
+	barrier_dsync_fence_full();
 
 	/* set to inactive */
 	sys_write32(irq, GICC_EOIR);
@@ -113,7 +114,7 @@ void gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
 		GICD_SGIR_CPULIST(target_list & GICD_SGIR_CPULIST_MASK) |
 		sgi_id;
 
-	__DSB();
+	barrier_dsync_fence_full();
 	sys_write32(sgi_val, GICD_SGIR);
 	__ISB();
 }

drivers/interrupt_controller/intc_gicv3.c

@@ -10,6 +10,7 @@
 #include <zephyr/sw_isr_table.h>
 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
 #include <zephyr/drivers/interrupt_controller/gic.h>
+#include <zephyr/sys/barrier.h>
 #include "intc_gic_common_priv.h"
 #include "intc_gicv3_priv.h"
 
@@ -80,7 +81,7 @@ static void arm_gic_lpi_setup(unsigned int intid, bool enable)
 		*cfg &= ~BIT(0);
 	}
 
-	dsb();
+	barrier_dsync_fence_full();
 
 	its_rdist_invall();
 }
@@ -92,7 +93,7 @@ static void arm_gic_lpi_set_priority(unsigned int intid, unsigned int prio)
 	*cfg &= 0xfc;
 	*cfg |= prio & 0xfc;
 
-	dsb();
+	barrier_dsync_fence_full();
 
 	its_rdist_invall();
 }
@@ -235,7 +236,7 @@ void arm_gic_eoi(unsigned int intid)
 	 * The dsb will also ensure *completion* of previous writes with
 	 * DEVICE nGnRnE attribute.
 	 */
-	__DSB();
+	barrier_dsync_fence_full();
 
 	/* (AP -> Pending) Or (Active -> Inactive) or (AP to AP) nested case */
 	write_sysreg(intid, ICC_EOIR1_EL1);
@@ -261,7 +262,7 @@ void gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
 	sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_id,
 				   SGIR_IRM_TO_AFF, target_list);
 
-	__DSB();
+	barrier_dsync_fence_full();
 	write_sysreg(sgi_val, ICC_SGI1R);
 	__ISB();
 }
@@ -332,7 +333,7 @@ static void gicv3_rdist_setup_lpis(mem_addr_t rdist)
 	ctlr |= GICR_CTLR_ENABLE_LPIS;
 	sys_write32(ctlr, rdist + GICR_CTLR);
 
-	dsb();
+	barrier_dsync_fence_full();
 }
 #endif
 

drivers/interrupt_controller/intc_gicv3_its.c

@@ -10,6 +10,7 @@ LOG_MODULE_REGISTER(intc_gicv3_its, LOG_LEVEL_ERR);
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
 #include <zephyr/drivers/interrupt_controller/gicv3_its.h>
+#include <zephyr/sys/barrier.h>
 
 #include "intc_gic_common_priv.h"
 #include "intc_gicv3_priv.h"
@@ -302,7 +303,7 @@ static int its_post_command(struct gicv3_its_data *data, struct its_cmd_block *c
 	wr_idx = (data->cmd_write - data->cmd_base) * sizeof(*cmd);
 	rd_idx = sys_read32(data->base + GITS_CREADR);
 
-	dsb();
+	barrier_dsync_fence_full();
 
 	sys_write32(wr_idx, data->base + GITS_CWRITER);
 
@@ -531,7 +532,7 @@ static int gicv3_its_init_device_id(const struct device *dev, uint32_t device_id
 			data->indirect_dev_lvl1_table[offset] = (uintptr_t)alloc_addr |
 								MASK_SET(1, GITS_BASER_VALID);
 
-			dsb();
+			barrier_dsync_fence_full();
 		}
 	}
 

drivers/ipm/ipm_imx.c

@@ -11,6 +11,7 @@
 #include <soc.h>
 #include <zephyr/drivers/ipm.h>
 #include <zephyr/irq.h>
+#include <zephyr/sys/barrier.h>
 #if defined(CONFIG_IPM_IMX_REV2)
 #define DT_DRV_COMPAT nxp_imx_mu_rev2
 #include "fsl_mu.h"
@@ -155,7 +156,7 @@ static void imx_mu_isr(const struct device *dev)
 	 * with errata 838869.
 	 */
 #if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U))
-	__DSB();
+	barrier_dsync_fence_full();
 #endif
 }
 

drivers/ipm/ipm_mcux.c

@@ -13,6 +13,7 @@
 #include <fsl_clock.h>
 #include <soc.h>
 #include <zephyr/irq.h>
+#include <zephyr/sys/barrier.h>
 
 #define MCUX_IPM_DATA_REGS 1
 #define MCUX_IPM_MAX_ID_VAL 0
@@ -69,7 +70,7 @@ static void mcux_mailbox_isr(const struct device *dev)
 	 * might vector to incorrect interrupt
 	 */
 #if defined __CORTEX_M && (__CORTEX_M == 4U)
-	__DSB();
+	barrier_dsync_fence_full();
 #endif
 }
 

drivers/usb/device/usb_dc_sam_usbc.c

@@ -1187,7 +1187,7 @@ static int usb_dc_ep_write_stp(uint8_t ep_bank, const uint8_t *data,
 		if (data) {
 			memcpy(dev_desc[ep_bank].ep_pipe_addr,
 			       data, packet_len);
-			__DSB();
+			barrier_dsync_fence_full();
 		}
 		dev_desc[ep_bank].sizes = packet_len;
 
@@ -1269,7 +1269,7 @@ int usb_dc_ep_write(uint8_t ep, const uint8_t *data,
 	} else {
 		if (data && packet_len > 0) {
 			memcpy(dev_desc[ep_bank].ep_pipe_addr, data, packet_len);
-			__DSB();
+			barrier_dsync_fence_full();
 		}
 		dev_desc[ep_bank].sizes = packet_len;
 
@@ -1385,7 +1385,7 @@ int usb_dc_ep_read_ex(uint8_t ep, uint8_t *data, uint32_t max_data_len,
 		       (uint8_t *) dev_desc[ep_bank].ep_pipe_addr +
 		       dev_data.ep_data[ep_idx].out_at,
 		       take);
-		__DSB();
+		barrier_dsync_fence_full();
 	}
 
 	if (read_bytes) {

drivers/usb/device/usb_dc_sam_usbhs.c

@@ -10,6 +10,7 @@
 #include <zephyr/drivers/clock_control/atmel_sam_pmc.h>
 #include <zephyr/irq.h>
 #include <zephyr/kernel.h>
+#include <zephyr/sys/barrier.h>
 #include <soc.h>
 #include <string.h>
 
@@ -123,7 +124,7 @@ static void usb_dc_ep_reset(uint8_t ep_idx)
 {
 	USBHS->USBHS_DEVEPT |= BIT(USBHS_DEVEPT_EPRST0_Pos + ep_idx);
 	USBHS->USBHS_DEVEPT &= ~BIT(USBHS_DEVEPT_EPRST0_Pos + ep_idx);
-	__DSB();
+	barrier_dsync_fence_full();
 }
 
 /* Enable endpoint interrupts, depending of the type and direction */
@@ -320,7 +321,7 @@ int usb_dc_attach(void)
 	/* Enable the USB controller in device mode with the clock frozen */
 	USBHS->USBHS_CTRL = USBHS_CTRL_UIMOD | USBHS_CTRL_USBE |
 			    USBHS_CTRL_FRZCLK;
-	__DSB();
+	barrier_dsync_fence_full();
 
 	/* Select the speed */
 	regval = USBHS_DEVCTRL_DETACH;
@@ -699,7 +700,7 @@ int usb_dc_ep_flush(uint8_t ep)
 	/* Kill the last written bank if needed */
 	if (USBHS->USBHS_DEVEPTISR[ep_idx] & USBHS_DEVEPTISR_NBUSYBK_Msk) {
 		USBHS->USBHS_DEVEPTIER[ep_idx] = USBHS_DEVEPTIER_KILLBKS;
-		__DSB();
+		barrier_dsync_fence_full();
 		while (USBHS->USBHS_DEVEPTIMR[ep_idx] &
 		       USBHS_DEVEPTIMR_KILLBK) {
 			k_yield();
@@ -748,7 +749,7 @@ int usb_dc_ep_write(uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t
 	for (int i = 0; i < packet_len; i++) {
 		usb_dc_ep_fifo_put(ep_idx, data[i]);
 	}
-	__DSB();
+	barrier_dsync_fence_full();
 
 	if (ep_idx == 0U) {
 		/*

include/zephyr/arch/arm64/cache.h

@@ -10,6 +10,7 @@
 
 #include <zephyr/types.h>
 #include <zephyr/sys/util.h>
+#include <zephyr/sys/barrier.h>
 #include <zephyr/arch/cpu.h>
 #include <errno.h>
 
@@ -133,7 +134,7 @@ static ALWAYS_INLINE int arm64_dcache_range(void *addr, size_t size, int op)
 	}
 
 done:
-	dsb();
+	barrier_dsync_fence_full();
 
 	return 0;
 }
@@ -155,7 +156,7 @@ static ALWAYS_INLINE int arm64_dcache_all(int op)
 	}
 
 	/* Data barrier before start */
-	dsb();
+	barrier_dsync_fence_full();
 
 	clidr_el1 = read_clidr_el1();
 
@@ -209,7 +210,7 @@ static ALWAYS_INLINE int arm64_dcache_all(int op)
 
 	/* Restore csselr_el1 to level 0 */
 	write_csselr_el1(0);
-	dsb();
+	barrier_dsync_fence_full();
 	isb();
 
 	return 0;

include/zephyr/arch/arm64/lib_helpers.h

@@ -154,12 +154,10 @@ static ALWAYS_INLINE void disable_fiq(void)
 #define wfe()	__asm__ volatile("wfe" : : : "memory")
 #define wfi()	__asm__ volatile("wfi" : : : "memory")
 
-#define dsb()	__asm__ volatile ("dsb sy" ::: "memory")
 #define isb()	__asm__ volatile ("isb" ::: "memory")
 
 /* Zephyr needs these as well */
 #define __ISB() isb()
-#define __DSB() dsb()
 
 static inline bool is_el_implemented(unsigned int el)
 {

soc/arm/arm/fvp_aemv8r_aarch32/soc.c

@@ -6,6 +6,7 @@
 
 #include <zephyr/kernel.h>
 #include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+#include <zephyr/sys/barrier.h>
 
 void z_arm_platform_init(void)
 {
@@ -21,7 +22,7 @@ void z_arm_platform_init(void)
 		if (!(__get_SCTLR() & SCTLR_C_Msk)) {
 			L1C_InvalidateDCacheAll();
 			__set_SCTLR(__get_SCTLR() | SCTLR_C_Msk);
-			__DSB();
+			barrier_dsync_fence_full();
 		}
 	}
 }

soc/arm/microchip_mec/mec1501/power.c

@@ -8,6 +8,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/sys/sys_io.h>
 #include <zephyr/sys/__assert.h>
+#include <zephyr/sys/barrier.h>
 #include <zephyr/pm/pm.h>
 #include <soc.h>
 #include "device_power.h"
@@ -53,7 +54,7 @@ static void z_power_soc_deep_sleep(void)
 	 * prevent entering an ISR after unmasking in BASEPRI.
 	 */
 	__set_BASEPRI(0);
-	__DSB();
+	barrier_dsync_fence_full();
 	__WFI();	/* triggers sleep hardware */
 	__NOP();
 	__NOP();
@@ -90,7 +91,7 @@ static void z_power_soc_sleep(void)
 	soc_lite_sleep_enable();
 
 	__set_BASEPRI(0); /* Make sure wake interrupts are not masked! */
-	__DSB();
+	barrier_dsync_fence_full();
 	__WFI();	/* triggers sleep hardware */
 	__NOP();
 	__NOP();

soc/arm/nxp_imx/mcimx6x_m4/soc.c

@@ -6,6 +6,7 @@
 
 #include <zephyr/init.h>
 #include <zephyr/irq.h>
+#include <zephyr/sys/barrier.h>
 #include <soc.h>
 #include <zephyr/dt-bindings/rdc/imx_rdc.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
@@ -177,7 +178,7 @@ static void SOC_CacheInit(void)
 	/* Enable code bus cache, enable write buffer */
 	LMEM_PCCCR = (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK);
 	__ISB();
-	__DSB();
+	barrier_dsync_fence_full();
 }
 
 /* Initialize clock. */

soc/arm/nxp_imx/rt/power_rt10xx.c

@@ -14,6 +14,7 @@
 #include <fsl_gpc.h>
 #include <fsl_clock.h>
 #include <zephyr/logging/log.h>
+#include <zephyr/sys/barrier.h>
 
 #include "power_rt10xx.h"
 
@@ -97,7 +98,7 @@ static void lpm_enter_sleep_mode(clock_mode_t mode)
 	__disable_irq();
 	/* Set BASEPRI to 0 */
 	irq_unlock(0);
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 
 	if (mode == kCLOCK_ModeWait) {

soc/arm/nxp_s32/s32ze/soc.c

@@ -8,6 +8,7 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+#include <zephyr/sys/barrier.h>
 
 #include <OsIf.h>
 
@@ -22,7 +23,7 @@ void z_arm_platform_init(void)
 	__asm__ volatile("mrc p15, 0, r0, c15, c0, 0\n");
 	__asm__ volatile("orr r0, #1\n");
 	__asm__ volatile("mcr p15, 0, r0, c15, c0, 0\n");
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 
 	if (IS_ENABLED(CONFIG_ICACHE)) {
@@ -37,7 +38,7 @@ void z_arm_platform_init(void)
 		if (!(__get_SCTLR() & SCTLR_C_Msk)) {
 			L1C_InvalidateDCacheAll();
 			__set_SCTLR(__get_SCTLR() | SCTLR_C_Msk);
-			__DSB();
+			barrier_dsync_fence_full();
 		}
 	}
 }

soc/arm/renesas_rcar/gen3/soc.c

@@ -8,6 +8,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
 #include <zephyr/init.h>
+#include <zephyr/sys/barrier.h>
 
 /**
  *
@@ -33,7 +34,7 @@ void z_arm_platform_init(void)
 
 	/* Invalidate instruction cache and flush branch target cache */
 	__set_ICIALLU(0);
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 
 	L1C_EnableCaches();

soc/arm64/bcm_vk/viper/plat_core.c

@@ -7,6 +7,7 @@
 #include <zephyr/toolchain.h>
 #include <zephyr/linker/sections.h>
 #include <zephyr/arch/cpu.h>
+#include <zephyr/sys/barrier.h>
 
 void z_arm64_el3_plat_init(void)
 {
@@ -47,6 +48,6 @@ void z_arm64_el3_plat_init(void)
 
 	write_sysreg(reg, CORTEX_A72_L2CTLR_EL1);
 
-	dsb();
+	barrier_dsync_fence_full();
 	isb();
 }

tests/arch/arm/arm_interrupt/src/arm_interrupt.c

@@ -7,6 +7,7 @@
 #include <zephyr/ztest.h>
 #include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <zephyr/sys/barrier.h>
 
 static volatile int test_flag;
 static volatile int expected_reason = -1;
@@ -292,7 +293,7 @@ ZTEST(arm_interrupt, test_arm_interrupt)
 	NVIC_ClearPendingIRQ(i);
 	NVIC_EnableIRQ(i);
 	NVIC_SetPendingIRQ(i);
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 
 	/* Verify that the spurious ISR has led to the fault and the
@@ -320,7 +321,7 @@ ZTEST(arm_interrupt, test_arm_interrupt)
 		 * Instruction barriers to make sure the NVIC IRQ is
 		 * set to pending state before 'test_flag' is checked.
 		 */
-		__DSB();
+		barrier_dsync_fence_full();
 		__ISB();
 
 		/* Returning here implies the thread was not aborted. */
@@ -367,7 +368,7 @@ ZTEST(arm_interrupt, test_arm_interrupt)
 #endif
 
 	__enable_irq();
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 
 	/* No stack variable access below this point.

tests/arch/arm/arm_irq_advanced_features/src/arm_dynamic_direct_interrupts.c

@@ -7,6 +7,7 @@
 #include <zephyr/ztest.h>
 #include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <zephyr/sys/barrier.h>
 
 /* Offset for the Direct interrupt used in this test. */
 #define DIRECT_ISR_OFFSET (CONFIG_NUM_IRQS - 1)
@@ -53,7 +54,7 @@ ZTEST(arm_irq_advanced_features, test_arm_dynamic_direct_interrupts)
 	 * Instruction barriers to make sure the NVIC IRQ is
 	 * set to pending state before 'test_flag' is checked.
 	 */
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 
 	/* Confirm test flag is set by the dynamic direct ISR handler. */
@@ -77,7 +78,7 @@ ZTEST(arm_irq_advanced_features, test_arm_dynamic_direct_interrupts)
 	 * Instruction barriers to make sure the NVIC IRQ is
 	 * set to pending state before 'test_flag' is checked.
 	 */
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 
 	/* Confirm test flag is set by the dynamic direct ISR handler. */

tests/arch/arm/arm_irq_advanced_features/src/arm_zero_latency_irqs.c

@@ -7,6 +7,7 @@
 #include <zephyr/ztest.h>
 #include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <zephyr/sys/barrier.h>
 
 static volatile int test_flag;
 
@@ -94,7 +95,7 @@ ZTEST(arm_irq_advanced_features, test_arm_zero_latency_irqs)
 	 * Instruction barriers to make sure the NVIC IRQ is
 	 * set to pending state before 'test_flag' is checked.
 	 */
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 
 	/* Confirm test flag is set by the zero-latency ISR handler. */

tests/arch/arm/arm_irq_zero_latency_levels/src/main.c

@@ -7,6 +7,7 @@
 #include <zephyr/ztest.h>
 #include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <zephyr/sys/barrier.h>
 
 
 #define EXECUTION_TRACE_LENGTH 6
@@ -86,7 +87,7 @@ void isr_a_handler(const void *args)
 
 	/* Set higher prior irq b pending */
 	NVIC_SetPendingIRQ(irq_b);
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 
 	execution_trace_add(STEP_ISR_A_END);
@@ -182,7 +183,7 @@ ZTEST(arm_irq_zero_latency_levels, test_arm_zero_latency_levels)
 
 	/* Trigger irq_a */
 	NVIC_SetPendingIRQ(irq_a);
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 
 	execution_trace_add(STEP_MAIN_END);

tests/arch/arm/arm_no_multithreading/src/main.c

@@ -8,6 +8,7 @@
 #include <zephyr/sys/printk.h>
 #include <zephyr/sys/__assert.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <zephyr/sys/barrier.h>
 
 #if !defined(CONFIG_CPU_CORTEX_M)
   #error test can only run on Cortex-M MCUs
@@ -89,7 +90,7 @@ void test_main(void)
 	/* Verify activating the PendSV IRQ triggers a K_ERR_SPURIOUS_IRQ */
 	expected_reason = K_ERR_CPU_EXCEPTION;
 	SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 
 	/* Determine an NVIC IRQ line that is not currently in use. */
@@ -142,7 +143,7 @@ void test_main(void)
 
 		NVIC_EnableIRQ(i);
 
-		__DSB();
+		barrier_dsync_fence_full();
 		__ISB();
 
 		flag = test_flag;

tests/arch/arm/arm_thread_swap/src/arm_syscalls.c

@@ -8,6 +8,7 @@
 #include <zephyr/arch/cpu.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/kernel_structs.h>
+#include <zephyr/sys/barrier.h>
 #include <offsets_short_arch.h>
 #include <ksched.h>
 
@@ -138,7 +139,7 @@ static void user_thread_entry(uint32_t irq_line)
 	TC_PRINT("USR Thread: IRQ Line: %u\n", (uint32_t)irq_line);
 
 	NVIC->STIR = irq_line;
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 
 	/* ISR is set to cause thread to context-switch -out and -in again.
@@ -146,7 +147,7 @@ static void user_thread_entry(uint32_t irq_line)
 	 * the user thread is switch back in.
 	 */
 	NVIC->STIR = irq_line;
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 #endif
 }

tests/arch/arm/arm_thread_swap/src/arm_thread_arch.c

@@ -92,7 +92,7 @@ static void load_callee_saved_regs(const _callee_saved_t *regs)
 		: "memory", "r1"
 	);
 #endif
-	__DSB();
+	barrier_dsync_fence_full();
 }
 
 static void verify_callee_saved(const _callee_saved_t *src,
@@ -154,7 +154,7 @@ static void load_fp_callee_saved_regs(
 		: "r" (regs)
 		: "memory"
 		);
-	__DSB();
+	barrier_dsync_fence_full();
 }
 
 static void verify_fp_callee_saved(const struct _preempt_float *src,

tests/kernel/fpu_sharing/float_disable/src/k_float_disable.c

@@ -5,6 +5,7 @@
  */
 
 #include <zephyr/ztest.h>
+#include <zephyr/sys/barrier.h>
 
 #define STACKSIZE 1024
 
@@ -226,7 +227,7 @@ static void sup_fp_thread_entry(void)
 	 * Instruction barriers to make sure the NVIC IRQ is
 	 * set to pending state before program proceeds.
 	 */
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 
 	/* Verify K_FP_REGS flag is still set */

tests/kernel/gen_isr_table/src/main.c

@@ -10,6 +10,7 @@
 #include <zephyr/tc_util.h>
 #include <zephyr/sw_isr_table.h>
 #include <zephyr/interrupt_util.h>
+#include <zephyr/sys/barrier.h>
 
 extern uint32_t _irq_vector_table[];
 
@@ -159,7 +160,7 @@ int test_irq(int offset)
 	TC_PRINT("triggering irq %d\n", IRQ_LINE(offset));
 	trigger_irq(IRQ_LINE(offset));
 #ifdef CONFIG_CPU_CORTEX_M
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 #endif
 	if (trigger_check[offset] != 1) {

tests/kernel/mem_protect/protection/src/main.c

@@ -10,6 +10,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/ztest.h>
 #include <zephyr/kernel_structs.h>
+#include <zephyr/sys/barrier.h>
 #include <string.h>
 #include <stdlib.h>
 
@@ -40,7 +41,7 @@ void k_sys_fatal_error_handler(unsigned int reason, const z_arch_esf_t *pEsf)
 /* Must set LSB of function address to call in Thumb mode. */
 #define PTR_TO_FUNC(x) (int (*)(int))((uintptr_t)(x) | 0x1)
 /* Flush preceding data writes and instruction fetches. */
-#define DO_BARRIERS() do { __DSB(); __ISB(); } while (0)
+#define DO_BARRIERS() do { barrier_dsync_fence_full(); __ISB(); } while (0)
 #else
 #define FUNC_TO_PTR(x) (void *)(x)
 #define PTR_TO_FUNC(x) (int (*)(int))(x)

tests/kernel/mem_protect/userspace/src/main.c

@@ -14,6 +14,7 @@
 #include <stdlib.h>
 #include <zephyr/app_memory/app_memdomain.h>
 #include <zephyr/sys/util.h>
+#include <zephyr/sys/barrier.h>
 #include <zephyr/debug/stack.h>
 #include <zephyr/syscall_handler.h>
 #include "test_syscall.h"
@@ -145,7 +146,7 @@ ZTEST_USER(userspace, test_write_control)
 	msr_value = __get_CONTROL();
 	msr_value &= ~(CONTROL_nPRIV_Msk);
 	__set_CONTROL(msr_value);
-	__DSB();
+	barrier_dsync_fence_full();
 	__ISB();
 	msr_value = __get_CONTROL();
 	zassert_true((msr_value & (CONTROL_nPRIV_Msk)),