ite: drivers/pinmux: modify pinmux driver
Modify the pinmux control method and add support the fun3 & fun4 alternation function. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
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9 changed files with 412 additions and 78 deletions
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@ -1,4 +1,4 @@
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/*
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/*
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* Copyright (c) 2020 ITE Corporation. All Rights Reserved.
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -689,6 +689,11 @@
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#define GPDMRJ ECREG(EC_REG_BASE_ADDR + 0x166A)
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#define GPDMRM ECREG(EC_REG_BASE_ADDR + 0x166D)
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#define GPCR_PORT_PIN_MODE_INPUT BIT(7)
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#define GPCR_PORT_PIN_MODE_OUTPUT BIT(6)
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#define GPCR_PORT_PIN_MODE_PULLUP BIT(2)
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#define GPCR_PORT_PIN_MODE_PULLDOWN BIT(1)
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/**
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*
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* (17XXh) PS/2 Interface Register
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@ -1610,6 +1615,14 @@
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#define CE_RNG ECREG(EC_REG_BASE_ADDR + 0x3C20)
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/* --- GPIO --- */
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#define IT8XXX2_GPIO_BASE 0x00F01600
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#define IT8XXX2_GPIO2_BASE 0x00F03E00
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#define IT8XXX2_GPIO_GCR ECREG(IT8XXX2_GPIO_BASE + 0x00)
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#define IT8XXX2_GPIO_GRC1 ECREG(IT8XXX2_GPIO_BASE + 0xF0)
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#define IT8XXX2_GPIO_GRC21 ECREG(IT8XXX2_GPIO_BASE + 0xE6)
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/* Analog to Digital Converter (ADC) */
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#define IT83XX_ADC_BASE 0x00f01900
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@ -1676,6 +1689,16 @@
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#define CGC_OFFSET_SMBB ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x08)
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#define CGC_OFFSET_SMBA ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x04)
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#define IT8XXX2_ECPM_AUTOCG ECREG(IT83XX_ECPM_BASE + 0x04)
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#define IT8XXX2_ECPM_CGCTRL3R ECREG(IT83XX_ECPM_BASE + 0x05)
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#define IT8XXX2_ECPM_PLLFREQR ECREG(IT83XX_ECPM_BASE + 0x06)
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#define IT8XXX2_ECPM_PLLCSS ECREG(IT83XX_ECPM_BASE + 0x08)
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#define IT8XXX2_ECPM_SCDCR0 ECREG(IT83XX_ECPM_BASE + 0x0c)
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#define IT8XXX2_ECPM_SCDCR1 ECREG(IT83XX_ECPM_BASE + 0x0d)
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#define IT8XXX2_ECPM_SCDCR2 ECREG(IT83XX_ECPM_BASE + 0x0e)
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#define IT8XXX2_ECPM_SCDCR3 ECREG(IT83XX_ECPM_BASE + 0x0f)
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#define IT8XXX2_ECPM_SCDCR4 ECREG(IT83XX_ECPM_BASE + 0x10)
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/*
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* The count number of the counter for 25 ms register.
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* The 25 ms register is calculated by (count number *1.024 kHz).
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