ite: drivers/pinmux: modify pinmux driver

Modify the pinmux control method and add support the fun3
& fun4 alternation function.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit is contained in:
Tim Lin 2021-05-03 08:46:56 +08:00 committed by Anas Nashif
commit caa3328cc7
9 changed files with 412 additions and 78 deletions

View file

@ -1,4 +1,4 @@
/*
/*
* Copyright (c) 2020 ITE Corporation. All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*/
@ -689,6 +689,11 @@
#define GPDMRJ ECREG(EC_REG_BASE_ADDR + 0x166A)
#define GPDMRM ECREG(EC_REG_BASE_ADDR + 0x166D)
#define GPCR_PORT_PIN_MODE_INPUT BIT(7)
#define GPCR_PORT_PIN_MODE_OUTPUT BIT(6)
#define GPCR_PORT_PIN_MODE_PULLUP BIT(2)
#define GPCR_PORT_PIN_MODE_PULLDOWN BIT(1)
/**
*
* (17XXh) PS/2 Interface Register
@ -1610,6 +1615,14 @@
#define CE_RNG ECREG(EC_REG_BASE_ADDR + 0x3C20)
/* --- GPIO --- */
#define IT8XXX2_GPIO_BASE 0x00F01600
#define IT8XXX2_GPIO2_BASE 0x00F03E00
#define IT8XXX2_GPIO_GCR ECREG(IT8XXX2_GPIO_BASE + 0x00)
#define IT8XXX2_GPIO_GRC1 ECREG(IT8XXX2_GPIO_BASE + 0xF0)
#define IT8XXX2_GPIO_GRC21 ECREG(IT8XXX2_GPIO_BASE + 0xE6)
/* Analog to Digital Converter (ADC) */
#define IT83XX_ADC_BASE 0x00f01900
@ -1676,6 +1689,16 @@
#define CGC_OFFSET_SMBB ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x08)
#define CGC_OFFSET_SMBA ((IT83XX_ECPM_CGCTRL4R_OFF << 8) | 0x04)
#define IT8XXX2_ECPM_AUTOCG ECREG(IT83XX_ECPM_BASE + 0x04)
#define IT8XXX2_ECPM_CGCTRL3R ECREG(IT83XX_ECPM_BASE + 0x05)
#define IT8XXX2_ECPM_PLLFREQR ECREG(IT83XX_ECPM_BASE + 0x06)
#define IT8XXX2_ECPM_PLLCSS ECREG(IT83XX_ECPM_BASE + 0x08)
#define IT8XXX2_ECPM_SCDCR0 ECREG(IT83XX_ECPM_BASE + 0x0c)
#define IT8XXX2_ECPM_SCDCR1 ECREG(IT83XX_ECPM_BASE + 0x0d)
#define IT8XXX2_ECPM_SCDCR2 ECREG(IT83XX_ECPM_BASE + 0x0e)
#define IT8XXX2_ECPM_SCDCR3 ECREG(IT83XX_ECPM_BASE + 0x0f)
#define IT8XXX2_ECPM_SCDCR4 ECREG(IT83XX_ECPM_BASE + 0x10)
/*
* The count number of the counter for 25 ms register.
* The 25 ms register is calculated by (count number *1.024 kHz).