soc: riscv: add initial support for SiFive Freedom U740
This patch adds support for SiFive Freedom U740 SoC. First version is minimum only using UART, SPI and L2-LIM area. Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
This commit is contained in:
Katsuhiro Suzuki
Christopher Friedt
parent
ae355cce56
commit
ca853af0b9
6 changed files with 276 additions and 1 deletions
143
dts/riscv/riscv64-fu740.dtsi
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143
dts/riscv/riscv64-fu740.dtsi
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@ -0,0 +1,143 @@
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/*
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* Copyright (c) 2021 Katsuhiro Suzuki
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <dt-bindings/gpio/gpio.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "sifive,FU740-C000", "fu740-dev", "sifive-dev";
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model = "sifive,FU740";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu: cpu@0 {
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compatible = "sifive,s7", "riscv";
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device_type = "cpu";
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reg = <0>;
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riscv,isa = "rv64imac";
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status = "okay";
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hlic: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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modeselect: rom@1000 {
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compatible = "sifive,modeselect0";
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reg = <0x1000 0x1000>;
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reg-names = "mem";
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};
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maskrom: rom@10000 {
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compatible = "sifive,maskrom0";
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reg = <0x10000 0x8000>;
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reg-names = "mem";
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};
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dtim: dtim@1000000 {
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compatible = "sifive,dtim0";
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reg = <0x1000000 0x2000>;
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reg-names = "mem";
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};
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clint: clint@2000000 {
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#interrupt-cells = <1>;
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compatible = "riscv,clint0";
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interrupt-controller;
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interrupts-extended = <&hlic 3 &hlic 7>;
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reg = <0x2000000 0x10000>;
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reg-names = "control";
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};
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l2lim: l2lim@8000000 {
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compatible = "sifive,l2lim0";
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reg = <0x8000000 0x200000>;
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reg-names = "mem";
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};
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plic: interrupt-controller@c000000 {
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#interrupt-cells = <2>;
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compatible = "sifive,plic-1.0.0";
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interrupt-controller;
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interrupts-extended = <&hlic 11>;
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reg = <0x0c000000 0x00002000
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0x0c002000 0x001fe000
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0x0c200000 0x03e00000>;
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reg-names = "prio", "irq_en", "reg";
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riscv,max-priority = <7>;
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riscv,ndev = <52>;
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};
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uart0: serial@10010000 {
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compatible = "sifive,uart0";
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interrupt-parent = <&plic>;
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interrupts = <4 1>;
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reg = <0x10010000 0x1000>;
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reg-names = "control";
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label = "uart_0";
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status = "disabled";
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};
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uart1: serial@10011000 {
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compatible = "sifive,uart0";
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interrupt-parent = <&plic>;
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interrupts = <5 1>;
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reg = <0x10011000 0x1000>;
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reg-names = "control";
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label = "uart_1";
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status = "disabled";
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};
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spi0: spi@10040000 {
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compatible = "sifive,spi0";
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interrupt-parent = <&plic>;
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interrupts = <51 1>;
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reg = <0x10040000 0x1000 0x20000000 0x10000000>;
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reg-names = "control", "mem";
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label = "spi_0";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi1: spi@10041000 {
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compatible = "sifive,spi0";
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interrupt-parent = <&plic>;
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interrupts = <52 1>;
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reg = <0x10041000 0x1000>;
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reg-names = "control";
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label = "spi_1";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi2: spi@10050000 {
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compatible = "sifive,spi0";
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interrupt-parent = <&plic>;
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interrupts = <6 1>;
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reg = <0x10050000 0x1000>;
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reg-names = "control";
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label = "spi_2";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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@ -3,3 +3,4 @@
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zephyr_sources()
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zephyr_sources_ifdef(CONFIG_SOC_RISCV_SIFIVE_FREEDOM fe310_clock.c)
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zephyr_sources_ifdef(CONFIG_SOC_RISCV_SIFIVE_FU540 fu540_clock.c)
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zephyr_sources_ifdef(CONFIG_SOC_RISCV_SIFIVE_FU740 fu740_clock.c)
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@ -16,4 +16,9 @@ config SOC_RISCV_SIFIVE_FU540
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select ATOMIC_OPERATIONS_C
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select 64BIT
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config SOC_RISCV_SIFIVE_FU740
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bool "SiFive Freedom U740 SOC implementation"
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select ATOMIC_OPERATIONS_C
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select 64BIT
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endchoice
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53
soc/riscv/riscv-privilege/sifive-freedom/fu740_clock.c
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53
soc/riscv/riscv-privilege/sifive-freedom/fu740_clock.c
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@ -0,0 +1,53 @@
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/*
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* Copyright (c) 2021 Katsuhiro Suzuki
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <init.h>
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#include "fu740_prci.h"
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/*
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* Switch the clock source
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* - core: to 1GHz PLL (CORE_PLL) from 26MHz oscilator (HFCLK)
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* - peri: to 250MHz PLL (HFPCLKPLL) from HFCLK
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* on the HiFive Unmatched board.
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*
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* Note: Valid PLL VCO range is 2400MHz to 4800MHz
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*/
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static int fu740_clock_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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PRCI_REG(PRCI_COREPLLCFG) =
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PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */
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PLL_F(76) | /* VCO: 2 x (76 + 1) = 154 = 4004MHz */
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PLL_Q(2) | /* output divider: VCO / 2^2 = 1001MHz */
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PLL_RANGE(PLL_RANGE_18MHZ) | /* 18MHz <= post divr(= 26MHz) < 30MHz */
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PLL_BYPASS(PLL_BYPASS_DISABLE) |
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PLL_FSE(PLL_FSE_INTERNAL);
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while ((PRCI_REG(PRCI_COREPLLCFG) & PLL_LOCK(1)) == 0)
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;
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/* Switch CORE_CLK to CORE_PLL from HFCLK */
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PRCI_REG(PRCI_COREPLLSEL) = COREPLLSEL_SEL(COREPLLSEL_COREPLL);
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PRCI_REG(PRCI_CORECLKSEL) = CLKSEL_SEL(CLKSEL_PLL);
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PRCI_REG(PRCI_HFPCLKPLLCFG) =
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PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */
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PLL_F(76) | /* VCO: 2 x (76 + 1) = 154 = 4004MHz */
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PLL_Q(4) | /* output divider: VCO / 2^4 = 250.25MHz */
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PLL_RANGE(PLL_RANGE_18MHZ) | /* 18MHz <= post divr(= 26MHz) < 30MHz */
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PLL_BYPASS(PLL_BYPASS_DISABLE) |
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PLL_FSE(PLL_FSE_INTERNAL);
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while ((PRCI_REG(PRCI_HFPCLKPLLCFG) & PLL_LOCK(1)) == 0)
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;
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/* Switch PCLK to HFPCLKPLL/2 from HFCLK/2 */
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PRCI_REG(PRCI_HFPCLKPLLOUTDIV) = OUTDIV_PLLCKE(OUTDIV_PLLCKE_ENA);
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PRCI_REG(PRCI_HFPCLKPLLSEL) = CLKSEL_SEL(CLKSEL_PLL);
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return 0;
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}
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SYS_INIT(fu740_clock_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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73
soc/riscv/riscv-privilege/sifive-freedom/fu740_prci.h
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73
soc/riscv/riscv-privilege/sifive-freedom/fu740_prci.h
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@ -0,0 +1,73 @@
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/*
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* Copyright (c) 2021 Katsuhiro Suzuki
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SIFIVE_FU740_PRCI_H
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#define _SIFIVE_FU740_PRCI_H
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#define Z_REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
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#define PRCI_REG(offset) Z_REG32(PRCI_BASE_ADDR, offset)
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/* Register offsets */
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#define PRCI_HFXOSCCFG (0x0000)
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#define PRCI_COREPLLCFG (0x0004)
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#define PRCI_COREPLLOUTDIV (0x0008)
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#define PRCI_DDRPLLCFG (0x000c)
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#define PRCI_DDRPLLOUTDIV (0x0010)
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#define PRCI_GEMGXLPLLCFG (0x001c)
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#define PRCI_GEMGXLPLLOUTDIV (0x0020)
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#define PRCI_CORECLKSEL (0x0024)
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#define PRCI_DEVICESRESETN (0x0028)
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#define PRCI_CLKMUXSTATUS (0x002c)
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#define PRCI_COREPLLSEL (0x0040)
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#define PRCI_HFPCLKPLLCFG (0x0050)
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#define PRCI_HFPCLKPLLOUTDIV (0x0054)
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#define PRCI_HFPCLKPLLSEL (0x0058)
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#define PLL_R(x) (((x) & 0x3f) << 0)
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#define PLL_F(x) (((x) & 0x1ff) << 6)
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#define PLL_Q(x) (((x) & 0x7) << 15)
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#define PLL_RANGE(x) (((x) & 0x7) << 18)
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#define PLL_BYPASS(x) (((x) & 0x1) << 24)
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#define PLL_FSE(x) (((x) & 0x1) << 25)
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#define PLL_LOCK(x) (((x) & 0x1) << 31)
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#define PLL_RANGE_RESET 0
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#define PLL_RANGE_0MHZ 1
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#define PLL_RANGE_11MHZ 2
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#define PLL_RANGE_18MHZ 3
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#define PLL_RANGE_30MHZ 4
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#define PLL_RANGE_50MHZ 5
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#define PLL_RANGE_80MHZ 6
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#define PLL_RANGE_130MHZ 7
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#define PLL_BYPASS_DISABLE 0
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#define PLL_BYPASS_ENABLE 1
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#define PLL_FSE_INTERNAL 1
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#define OUTDIV_PLLCKE(x) (((x) & 0x1) << 31)
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#define OUTDIV_PLLCKE_DIS 0
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#define OUTDIV_PLLCKE_ENA 1
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#define CLKSEL_SEL(x) (((x) & 0x1) << 0)
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#define CLKSEL_PLL 0
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#define CLKSEL_HFCLK 1
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#define CLKMUXSTATUS_CORECLKPLLSEL_OFF 0
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#define CLKMUXSTATUS_TLCLKSEL_OFF 1
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#define CLKMUXSTATUS_RTCXSEL_OFF 2
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#define CLKMUXSTATUS_DDRCTRLCLKSEL_OFF 3
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#define CLKMUXSTATUS_DDRPHYCLKSEL_OFF 4
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#define CLKMUXSTATUS_GEMGXLCLKSEL_OFF 6
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#define CLKMUXSTATUS_MAINMEMCLKSEL_OFF 7
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#define COREPLLSEL_SEL(x) (((x) & 0x1) << 0)
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#define COREPLLSEL_COREPLL 0
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#define COREPLLSEL_DVFSCOREPLL 1
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#endif /* _SIFIVE_FU740_PRCI_H */
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@ -35,7 +35,7 @@
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#define SIFIVE_BACKUP_REG_BASE 0x10000080
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#elif defined(CONFIG_SOC_RISCV_SIFIVE_FU540)
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#elif defined(CONFIG_SOC_RISCV_SIFIVE_FU540) || defined(CONFIG_SOC_RISCV_SIFIVE_FU740)
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/* Clock controller. */
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#define PRCI_BASE_ADDR 0x10000000
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