ITE: soc: chip_chipregs: Cleanup it8xxx2 chip registers
1. Distinguish the registers of V1 and V2. 2. Remove unused chip variant configuration. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
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17081222e2
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ca66e7d5e1
1 changed files with 21 additions and 10 deletions
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@ -55,10 +55,6 @@
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#define IT8XXX2_GCTRL_JTAGSEL BIT(0)
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#define IT8XXX2_GCTRL_JTAGSEL BIT(0)
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#define IT8XXX2_GCTRL_JTAG (IT8XXX2_GCTRL_JTAGEN | IT8XXX2_GCTRL_JTAGSEL)
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#define IT8XXX2_GCTRL_JTAG (IT8XXX2_GCTRL_JTAGEN | IT8XXX2_GCTRL_JTAGSEL)
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/* --- External GPIO Control (EGPIO) --- */
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#define IT8XXX2_EGPIO_BASE 0x00F02100
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#define IT8XXX2_EGPIO_EGCR ECREG(IT8XXX2_EGPIO_BASE + 0x04)
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#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V2
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#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V2
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#define IT8XXX2_JTAG_PINS_BASE ECREG(0xF01660)
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#define IT8XXX2_JTAG_PINS_BASE ECREG(0xF01660)
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#define IT8XXX2_JTAG_VOLT_SET ECREG(0xF01648)
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#define IT8XXX2_JTAG_VOLT_SET ECREG(0xF01648)
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@ -67,18 +63,25 @@
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#define IT8XXX2_JTAG_VOLT_SET ECREG(0xF016e9)
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#define IT8XXX2_JTAG_VOLT_SET ECREG(0xF016e9)
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#endif
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#endif
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#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V2
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/* --- External GPIO Control (EGPIO) --- */
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#define IT8XXX2_EGPIO_BASE 0x00F02100
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#define IT8XXX2_EGPIO_EGCR ECREG(IT8XXX2_EGPIO_BASE + 0x04)
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/* EGPIO register fields */
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/* EGPIO register fields */
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/*
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/*
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* 0x04: External GPIO Control
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* 0x04: External GPIO Control
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* BIT(4): EXGPIO EGAD Pin Output Driving Disable
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* BIT(4): EXGPIO EGAD Pin Output Driving Disable
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*/
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*/
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#define IT8XXX2_EGPIO_EEPODD BIT(4)
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#define IT8XXX2_EGPIO_EEPODD BIT(4)
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#endif
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/**
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/**
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*
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*
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* (11xxh) Interrupt controller (INTC)
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* (11xxh) Interrupt controller (INTC)
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*
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*
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*/
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*/
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#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
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#define ISR0 ECREG(EC_REG_BASE_ADDR + 0x3F00)
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#define ISR0 ECREG(EC_REG_BASE_ADDR + 0x3F00)
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#define ISR1 ECREG(EC_REG_BASE_ADDR + 0x3F01)
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#define ISR1 ECREG(EC_REG_BASE_ADDR + 0x3F01)
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#define ISR2 ECREG(EC_REG_BASE_ADDR + 0x3F02)
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#define ISR2 ECREG(EC_REG_BASE_ADDR + 0x3F02)
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@ -178,7 +181,7 @@
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#define IPOLR21 ECREG(EC_REG_BASE_ADDR + 0x3F5B)
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#define IPOLR21 ECREG(EC_REG_BASE_ADDR + 0x3F5B)
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#define IPOLR22 ECREG(EC_REG_BASE_ADDR + 0x3F5F)
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#define IPOLR22 ECREG(EC_REG_BASE_ADDR + 0x3F5F)
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#define IPOLR23 ECREG(EC_REG_BASE_ADDR + 0x3F93)
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#define IPOLR23 ECREG(EC_REG_BASE_ADDR + 0x3F93)
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#endif
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#define IVECT ECREG(EC_REG_BASE_ADDR + 0x3F10)
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#define IVECT ECREG(EC_REG_BASE_ADDR + 0x3F10)
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@ -187,10 +190,17 @@
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* to fix in tcpm\it83xx_pd.h.
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* to fix in tcpm\it83xx_pd.h.
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*/
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*/
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/* GPIO control register */
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/* GPIO control register */
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#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
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#define GPCRF4 ECREG(EC_REG_BASE_ADDR + 0x163C)
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#define GPCRF4 ECREG(EC_REG_BASE_ADDR + 0x163C)
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#define GPCRF5 ECREG(EC_REG_BASE_ADDR + 0x163D)
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#define GPCRF5 ECREG(EC_REG_BASE_ADDR + 0x163D)
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#define GPCRH1 ECREG(EC_REG_BASE_ADDR + 0x1649)
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#define GPCRH1 ECREG(EC_REG_BASE_ADDR + 0x1649)
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#define GPCRH2 ECREG(EC_REG_BASE_ADDR + 0x164A)
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#define GPCRH2 ECREG(EC_REG_BASE_ADDR + 0x164A)
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#elif CONFIG_SOC_IT8XXX2_REG_SET_V2
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#define GPCRF4 ECREG(EC_REG_BASE_ADDR + 0x168C)
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#define GPCRF5 ECREG(EC_REG_BASE_ADDR + 0x168D)
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#define GPCRH1 ECREG(EC_REG_BASE_ADDR + 0x1699)
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#define GPCRH2 ECREG(EC_REG_BASE_ADDR + 0x169A)
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#endif
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/*
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/*
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* IT8XXX2 register structure size/offset checking macro function to mitigate
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* IT8XXX2 register structure size/offset checking macro function to mitigate
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@ -268,6 +278,7 @@ struct pwm_it8xxx2_regs {
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/* --- Wake-Up Control (WUC) --- */
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/* --- Wake-Up Control (WUC) --- */
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#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
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#define IT8XXX2_WUC_BASE 0x00F01B00
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#define IT8XXX2_WUC_BASE 0x00F01B00
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/* TODO: should a defined interface for configuring wake-up interrupts */
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/* TODO: should a defined interface for configuring wake-up interrupts */
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@ -277,6 +288,7 @@ struct pwm_it8xxx2_regs {
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#define IT8XXX2_WUC_WUESR5 (IT8XXX2_WUC_BASE + 0x0d)
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#define IT8XXX2_WUC_WUESR5 (IT8XXX2_WUC_BASE + 0x0d)
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#define IT8XXX2_WUC_WUBEMR1 (IT8XXX2_WUC_BASE + 0x3c)
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#define IT8XXX2_WUC_WUBEMR1 (IT8XXX2_WUC_BASE + 0x3c)
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#define IT8XXX2_WUC_WUBEMR5 (IT8XXX2_WUC_BASE + 0x0f)
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#define IT8XXX2_WUC_WUBEMR5 (IT8XXX2_WUC_BASE + 0x0f)
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#endif
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/**
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/**
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*
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*
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@ -1117,8 +1129,8 @@ struct gpio_it8xxx2_regs {
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GPCR_PORT_PIN_MODE_PULLDOWN)
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GPCR_PORT_PIN_MODE_PULLDOWN)
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/* --- GPIO --- */
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/* --- GPIO --- */
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#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
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#define IT8XXX2_GPIO_BASE 0x00F01600
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#define IT8XXX2_GPIO_BASE 0x00F01600
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#define IT8XXX2_GPIO2_BASE 0x00F03E00
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#define IT8XXX2_GPIO_GCRX(offset) ECREG(IT8XXX2_GPIO_BASE + (offset))
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#define IT8XXX2_GPIO_GCRX(offset) ECREG(IT8XXX2_GPIO_BASE + (offset))
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#define IT8XXX2_GPIO_GCR25_OFFSET 0xd1
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#define IT8XXX2_GPIO_GCR25_OFFSET 0xd1
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@ -1136,11 +1148,14 @@ struct gpio_it8xxx2_regs {
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#define IT8XXX2_GPIO_GCR24_OFFSET 0xe9
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#define IT8XXX2_GPIO_GCR24_OFFSET 0xe9
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#define IT8XXX2_GPIO_GCR30_OFFSET 0xed
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#define IT8XXX2_GPIO_GCR30_OFFSET 0xed
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#define IT8XXX2_GPIO_GCR29_OFFSET 0xee
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#define IT8XXX2_GPIO_GCR29_OFFSET 0xee
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#endif
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/*
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/*
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* TODO: use pinctrl node instead of following register declarations
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* TODO: use pinctrl node instead of following register declarations
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* to fix in tcpm\it83xx_pd.h.
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* to fix in tcpm\it83xx_pd.h.
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*/
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*/
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#define IT8XXX2_GPIO2_BASE 0x00F03E00
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#define IT8XXX2_GPIO_GPCRP0 ECREG(IT8XXX2_GPIO2_BASE + 0x18)
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#define IT8XXX2_GPIO_GPCRP0 ECREG(IT8XXX2_GPIO2_BASE + 0x18)
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#define IT8XXX2_GPIO_GPCRP1 ECREG(IT8XXX2_GPIO2_BASE + 0x19)
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#define IT8XXX2_GPIO_GPCRP1 ECREG(IT8XXX2_GPIO2_BASE + 0x19)
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@ -1494,11 +1509,7 @@ enum chip_pll_mode {
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#define IT83XX_SPI_RXFFSM (BIT(4) | BIT(3))
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#define IT83XX_SPI_RXFFSM (BIT(4) | BIT(3))
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#define IT83XX_SPI_RXF2FS BIT(2)
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#define IT83XX_SPI_RXF2FS BIT(2)
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#define IT83XX_SPI_RXF1FS BIT(1)
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#define IT83XX_SPI_RXF1FS BIT(1)
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#ifdef CHIP_VARIANT_IT83202BX
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#define IT83XX_SPI_SPISRDR ECREG(IT83XX_SPI_BASE + 0x08)
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#else
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#define IT83XX_SPI_SPISRDR ECREG(IT83XX_SPI_BASE + 0x0b)
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#define IT83XX_SPI_SPISRDR ECREG(IT83XX_SPI_BASE + 0x0b)
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#endif
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#define IT83XX_SPI_CPUWTFDB0 ECREG_u32(IT83XX_SPI_BASE + 0x08)
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#define IT83XX_SPI_CPUWTFDB0 ECREG_u32(IT83XX_SPI_BASE + 0x08)
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#define IT83XX_SPI_FCR ECREG(IT83XX_SPI_BASE + 0x09)
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#define IT83XX_SPI_FCR ECREG(IT83XX_SPI_BASE + 0x09)
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#define IT83XX_SPI_SPISRTXF BIT(2)
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#define IT83XX_SPI_SPISRTXF BIT(2)
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