boards: stm32h747i_disco: enable SDRAM
Enable SDRAM on M7 core. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit is contained in:
parent
eedb1125b9
commit
ca3488cb9b
3 changed files with 50 additions and 0 deletions
|
@ -67,6 +67,8 @@ The current Zephyr stm32h747i_disco board configuration supports the following h
|
||||||
+-----------+------------+-------------------------------------+
|
+-----------+------------+-------------------------------------+
|
||||||
| RNG | on-chip | True Random number generator |
|
| RNG | on-chip | True Random number generator |
|
||||||
+-----------+------------+-------------------------------------+
|
+-----------+------------+-------------------------------------+
|
||||||
|
| FMC | on-chip | memc (SDRAM) |
|
||||||
|
+-----------+------------+-------------------------------------+
|
||||||
|
|
||||||
(*) From UM2411 Rev 4:
|
(*) From UM2411 Rev 4:
|
||||||
With the default setting, the Ethernet feature is not working because of
|
With the default setting, the Ethernet feature is not working because of
|
||||||
|
|
|
@ -21,6 +21,11 @@
|
||||||
zephyr,flash = &flash0;
|
zephyr,flash = &flash0;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
sdram2: sdram@d0000000 {
|
||||||
|
device_type = "memory";
|
||||||
|
reg = <0xd0000000 DT_SIZE_M(32)>;
|
||||||
|
};
|
||||||
|
|
||||||
leds {
|
leds {
|
||||||
green_led_1:led_1 {
|
green_led_1:led_1 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
|
@ -74,3 +79,45 @@
|
||||||
&rng {
|
&rng {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
&fmc {
|
||||||
|
status = "okay";
|
||||||
|
pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 &fmc_nbl2_pi4 &fmc_nbl3_pi5
|
||||||
|
&fmc_sdclk_pg8 &fmc_sdnwe_ph5 &fmc_sdcke1_ph7
|
||||||
|
&fmc_sdne1_ph6 &fmc_sdnras_pf11 &fmc_sdncas_pg15
|
||||||
|
&fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4
|
||||||
|
&fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
|
||||||
|
&fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1 &fmc_a12_pg2
|
||||||
|
&fmc_a13_pg3 &fmc_a14_pg4 &fmc_a15_pg5 &fmc_d0_pd14
|
||||||
|
&fmc_d1_pd15 &fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7
|
||||||
|
&fmc_d5_pe8 &fmc_d6_pe9 &fmc_d7_pe10 &fmc_d8_pe11
|
||||||
|
&fmc_d9_pe12 &fmc_d10_pe13 &fmc_d11_pe14 &fmc_d12_pe15
|
||||||
|
&fmc_d13_pd8 &fmc_d14_pd9 &fmc_d15_pd10 &fmc_d16_ph8
|
||||||
|
&fmc_d17_ph9 &fmc_d18_ph10 &fmc_d19_ph11 &fmc_d20_ph12
|
||||||
|
&fmc_d21_ph13 &fmc_d22_ph14 &fmc_d23_ph15 &fmc_d24_pi0
|
||||||
|
&fmc_d26_pi2 &fmc_d27_pi3 &fmc_d28_pi6 &fmc_d29_pi7
|
||||||
|
&fmc_d30_pi9 &fmc_d31_pi10>;
|
||||||
|
|
||||||
|
sdram {
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
power-up-delay = <100>;
|
||||||
|
num-auto-refresh = <8>;
|
||||||
|
mode-register = <0x220>;
|
||||||
|
refresh-rate = <603>;
|
||||||
|
|
||||||
|
bank@1 {
|
||||||
|
reg = <1>;
|
||||||
|
|
||||||
|
st,sdram-control = <STM32_FMC_SDRAM_NC_9
|
||||||
|
STM32_FMC_SDRAM_NR_12
|
||||||
|
STM32_FMC_SDRAM_MWID_32
|
||||||
|
STM32_FMC_SDRAM_NB_4
|
||||||
|
STM32_FMC_SDRAM_CAS_2
|
||||||
|
STM32_FMC_SDRAM_SDCLK_PERIOD_2
|
||||||
|
STM32_FMC_SDRAM_RBURST_ENABLE
|
||||||
|
STM32_FMC_SDRAM_RPIPE_0>;
|
||||||
|
st,sdram-timing = <2 6 4 6 2 2 2>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
|
@ -12,3 +12,4 @@ supported:
|
||||||
- arduino_gpio
|
- arduino_gpio
|
||||||
- gpio
|
- gpio
|
||||||
- netif:eth
|
- netif:eth
|
||||||
|
- memc
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue