soc: renesas: Add initial support for RA6M5 SoC
Initial commit to support RA6M5 SoC Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
This commit is contained in:
Duy Phuong Hoang. Nguyen
Anas Nashif
parent
7060672c37
commit
c9ba4bf234
11 changed files with 755 additions and 0 deletions
21
dts/arm/renesas/ra/ra6/r7fa6m5bh3cfc.dtsi
Normal file
21
dts/arm/renesas/ra/ra6/r7fa6m5bh3cfc.dtsi
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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/renesas/ra/ra6/r7fa6m5xh.dtsi>
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/ {
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soc {
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flash-controller@407e0000 {
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reg = <0x407e0000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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reg = <0x0 DT_SIZE_M(2)>;
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};
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};
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};
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};
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344
dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi
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344
dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi
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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
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#include <zephyr/dt-bindings/clock/ra_clock.h>
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/ {
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soc {
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(512)>;
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};
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ioport6: gpio@400800c0 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x400800c0 0x20>;
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port = <6>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport7: gpio@400800e0 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x400800e0 0x20>;
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port = <7>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport8: gpio@40080100 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40080100 0x20>;
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port = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport9: gpio@40080120 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40080120 0x20>;
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port = <9>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioporta: gpio@40080140 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40080140 0x20>;
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port = <10>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioportb: gpio@40080160 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40080160 0x20>;
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port = <11>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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sci1: sci1@40118100 {
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compatible = "renesas,ra-sci";
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interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40118100 0x100>;
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clocks = <&pclka MSTPB 30>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <1>;
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status = "disabled";
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};
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};
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sci2: sci2@40118200 {
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compatible = "renesas,ra-sci";
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interrupts = <8 1>, <9 1>, <10 1>, <11 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40118200 0x100>;
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clocks = <&pclka MSTPB 29>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <2>;
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status = "disabled";
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};
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};
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sci3: sci3@40118300 {
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compatible = "renesas,ra-sci";
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interrupts = <12 1>, <13 1>, <14 1>, <15 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40118300 0x100>;
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clocks = <&pclka MSTPB 28>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <3>;
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status = "disabled";
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};
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};
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sci4: sci4@40118400 {
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compatible = "renesas,ra-sci";
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interrupts = <16 1>, <17 1>, <18 1>, <19 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40118400 0x100>;
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clocks = <&pclka MSTPB 27>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <4>;
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status = "disabled";
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};
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};
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sci5: sci5@40118500 {
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compatible = "renesas,ra-sci";
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interrupts = <20 1>, <21 1>, <22 1>, <23 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40118500 0x100>;
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clocks = <&pclka MSTPB 26>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <5>;
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status = "disabled";
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};
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};
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sci6: sci6@40118600 {
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compatible = "renesas,ra-sci";
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interrupts = <24 1>, <25 1>, <26 1>, <27 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40118600 0x100>;
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clocks = <&pclka MSTPB 25>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <6>;
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status = "disabled";
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};
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};
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sci7: sci7@40118700 {
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compatible = "renesas,ra-sci";
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interrupts = <28 1>, <29 1>, <30 1>, <31 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40118700 0x100>;
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clocks = <&pclka MSTPB 24>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <7>;
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status = "disabled";
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};
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};
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sci8: sci8@40118800 {
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compatible = "renesas,ra-sci";
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interrupts = <32 1>, <33 1>, <34 1>, <35 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40118800 0x100>;
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clocks = <&pclka MSTPB 23>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <8>;
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status = "disabled";
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};
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};
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};
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clocks: clocks {
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xtal: clock-xtal {
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compatible = "renesas,ra-cgc-external-clock";
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clock-frequency = <DT_FREQ_M(24)>;
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#clock-cells = <0>;
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status = "disabled";
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};
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hoco: clock-hoco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(20)>;
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#clock-cells = <0>;
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};
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moco: clock-moco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(8)>;
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#clock-cells = <0>;
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};
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loco: clock-loco {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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subclk: clock-subclk {
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compatible = "renesas,ra-cgc-subclk";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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status = "disabled";
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};
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pll: pll {
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compatible = "renesas,ra-cgc-pll";
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#clock-cells = <0>;
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/* PLL */
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source = <RA_PLL_SOURCE_MAIN_OSC>;
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div = <RA_PLL_DIV_3>;
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mul = <25 0>;
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freq = <DT_FREQ_M(200)>;
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status = "disabled";
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};
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pll2: pll2 {
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compatible = "renesas,ra-cgc-pll";
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#clock-cells = <0>;
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/* PLL2 */
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source = <RA_PLL_SOURCE_DISABLE>;
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div = <RA_PLL_DIV_2>;
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mul = <20 0>;
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status = "disabled";
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};
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pclkblock: pclkblock {
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compatible = "renesas,ra-cgc-pclk-block";
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#clock-cells = <0>;
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sysclock-src = <RA_CLOCK_SOURCE_PLL>;
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status = "okay";
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iclk: iclk {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_1>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclka: pclka {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_2>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkb: pclkb {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_4>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkc: pclkc {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_4>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkd: pclkd {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_2>;
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#clock-cells = <2>;
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status = "okay";
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};
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bclk: bclk {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_2>;
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bclkout: bclkout {
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compatible = "renesas,ra-cgc-busclk";
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clk_out_div = <2>;
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sdclk = <0>;
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#clock-cells = <0>;
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};
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#clock-cells = <2>;
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status = "okay";
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};
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fclk: fclk {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_4>;
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#clock-cells = <2>;
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status = "okay";
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};
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clkout: clkout {
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compatible = "renesas,ra-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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uclk: uclk {
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compatible = "renesas,ra-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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u60clk: u60clk {
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compatible = "renesas,ra-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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octaspiclk: octaspiclk {
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compatible = "renesas,ra-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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canfdclk: canfdclk {
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compatible = "renesas,ra-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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cecclk: cecclk {
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compatible = "renesas,ra-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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};
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};
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};
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160
dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi
Normal file
160
dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi
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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv8-m.dtsi>
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#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
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#include <zephyr/dt-bindings/clock/ra_clock.h>
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#include <freq.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m33";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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};
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soc {
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interrupt-parent = <&nvic>;
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system: system@4001e000 {
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compatible = "renesas,ra-system";
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reg = <0x4001e000 0x1000>;
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status = "okay";
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};
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ioport0: gpio@40080000 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40080000 0x20>;
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port = <0>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport1: gpio@40080020 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40080020 0x20>;
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port = <1>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport2: gpio@40080040 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40080040 0x20>;
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port = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport3: gpio@40080060 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40080060 0x20>;
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port = <3>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport4: gpio@40080080 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40080080 0x20>;
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port = <4>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport5: gpio@400800a0 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x400800a0 0x20>;
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port = <5>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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pinctrl: pin-contrller@40080800 {
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compatible = "renesas,ra-pinctrl-pfs";
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reg = <0x40080800 0x3c0>;
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status = "okay";
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};
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sci0: sci0@40118000 {
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compatible = "renesas,ra-sci";
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interrupts = <0 1>, <1 1>, <2 1>, <3 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40118000 0x100>;
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clocks = <&pclka MSTPB 31>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <0>;
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status = "disabled";
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};
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};
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sci9: sci9@40118900 {
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compatible = "renesas,ra-sci";
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interrupts = <36 1>, <37 1>, <38 1>, <39 1>;
|
||||
interrupt-names = "rxi", "txi", "tei", "eri";
|
||||
reg = <0x40118900 0x100>;
|
||||
clocks = <&pclka MSTPB 22>;
|
||||
status = "disabled";
|
||||
uart {
|
||||
compatible = "renesas,ra-sci-uart";
|
||||
channel = <9>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
option_setting_ofs: option_setting_ofs@100a100 {
|
||||
compatible = "zephyr,memory-region";
|
||||
reg = <0x0100a100 0x18>;
|
||||
zephyr,memory-region = "OPTION_SETTING_OFS";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
option_setting_sas: option_setting_sas@100a134 {
|
||||
compatible = "zephyr,memory-region";
|
||||
reg = <0x0100a134 0xcc>;
|
||||
zephyr,memory-region = "OPTION_SETTING_SAS";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
option_setting_s: option_setting_s@100a200 {
|
||||
compatible = "zephyr,memory-region";
|
||||
reg = <0x0100a200 0x100>;
|
||||
zephyr,memory-region = "OPTION_SETTING_S";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <4>;
|
||||
};
|
||||
12
soc/renesas/ra/ra6m5/CMakeLists.txt
Normal file
12
soc/renesas/ra/ra6m5/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
# Copyright (c) 2024 Renesas Electronics Corporation
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_include_directories(.)
|
||||
|
||||
zephyr_sources(
|
||||
soc.c
|
||||
)
|
||||
|
||||
zephyr_linker_sources(SECTIONS sections.ld)
|
||||
|
||||
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
|
||||
14
soc/renesas/ra/ra6m5/Kconfig
Normal file
14
soc/renesas/ra/ra6m5/Kconfig
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
# Copyright (c) 2024 Renesas Electronics Corporation
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_RA6M5
|
||||
select ARM
|
||||
select CPU_CORTEX_M33
|
||||
select CPU_HAS_ARM_MPU
|
||||
select HAS_RENESAS_RA_FSP
|
||||
select CPU_CORTEX_M_HAS_DWT
|
||||
select CPU_HAS_FPU
|
||||
select ARMV8_M_DSP
|
||||
select FPU
|
||||
select HAS_SWO
|
||||
select XIP
|
||||
12
soc/renesas/ra/ra6m5/Kconfig.defconfig
Normal file
12
soc/renesas/ra/ra6m5/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
# Copyright (c) 2024 Renesas Electronics Corporation
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_RA6M5
|
||||
|
||||
config NUM_IRQS
|
||||
default 96
|
||||
|
||||
config PINCTRL
|
||||
default y
|
||||
|
||||
endif # SOC_SERIES_RA6M5
|
||||
20
soc/renesas/ra/ra6m5/Kconfig.soc
Normal file
20
soc/renesas/ra/ra6m5/Kconfig.soc
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
# Copyright (c) 2024 Renesas Electronics Corporation
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_RA6M5
|
||||
bool
|
||||
select SOC_FAMILY_RENESAS_RA
|
||||
help
|
||||
Renesas RA6M5 series
|
||||
|
||||
config SOC_R7FA6M5BH3CFC
|
||||
bool
|
||||
select SOC_SERIES_RA6M5
|
||||
help
|
||||
R7FA6M5BH3CFC
|
||||
|
||||
config SOC_SERIES
|
||||
default "ra6m5" if SOC_SERIES_RA6M5
|
||||
|
||||
config SOC
|
||||
default "r7fa6m5bh3cfc" if SOC_R7FA6M5BH3CFC
|
||||
79
soc/renesas/ra/ra6m5/sections.ld
Normal file
79
soc/renesas/ra/ra6m5/sections.ld
Normal file
|
|
@ -0,0 +1,79 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
.code_in_ram :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__Code_In_RAM_Start = .;
|
||||
KEEP(*(.code_in_ram*))
|
||||
__Code_In_RAM_End = .;
|
||||
} > RAMABLE_REGION
|
||||
|
||||
SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
|
||||
{
|
||||
/* If DTC is used, put the DTC vector table at the start of SRAM.
|
||||
This avoids memory holes due to 1K alignment required by it. */
|
||||
*(.fsp_dtc_vector_table)
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
|
||||
|
||||
SECTION_PROLOGUE(.option_setting_ofs,,)
|
||||
{
|
||||
__OPTION_SETTING_OFS_Start = .;
|
||||
KEEP(*(.option_setting_ofs0))
|
||||
. = __OPTION_SETTING_OFS_Start + 0x04;
|
||||
KEEP(*(.option_setting_ofs2))
|
||||
. = __OPTION_SETTING_OFS_Start + 0x10;
|
||||
KEEP(*(.option_setting_dualsel))
|
||||
__OPTION_SETTING_OFS_End = .;
|
||||
} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
|
||||
|
||||
SECTION_PROLOGUE(.option_setting_sas,,)
|
||||
{
|
||||
__OPTION_SETTING_SAS_Start = .;
|
||||
KEEP(*(.option_setting_sas))
|
||||
__OPTION_SETTING_SAS_End = .;
|
||||
} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
|
||||
|
||||
SECTION_PROLOGUE(.option_setting_s,,)
|
||||
{
|
||||
__OPTION_SETTING_S_Start = .;
|
||||
KEEP(*(.option_setting_ofs1_sec))
|
||||
. = __OPTION_SETTING_S_Start + 0x04;
|
||||
KEEP(*(.option_setting_ofs3_sec))
|
||||
. = __OPTION_SETTING_S_Start + 0x10;
|
||||
KEEP(*(.option_setting_banksel_sec))
|
||||
. = __OPTION_SETTING_S_Start + 0x40;
|
||||
KEEP(*(.option_setting_bps_sec0))
|
||||
. = __OPTION_SETTING_S_Start + 0x44;
|
||||
KEEP(*(.option_setting_bps_sec1))
|
||||
. = __OPTION_SETTING_S_Start + 0x48;
|
||||
KEEP(*(.option_setting_bps_sec2))
|
||||
. = __OPTION_SETTING_S_Start + 0x4C;
|
||||
KEEP(*(.option_setting_bps_sec3))
|
||||
. = __OPTION_SETTING_S_Start + 0x60;
|
||||
KEEP(*(.option_setting_pbps_sec0))
|
||||
. = __OPTION_SETTING_S_Start + 0x64;
|
||||
KEEP(*(.option_setting_pbps_sec1))
|
||||
. = __OPTION_SETTING_S_Start + 0x68;
|
||||
KEEP(*(.option_setting_pbps_sec2))
|
||||
. = __OPTION_SETTING_S_Start + 0x6C;
|
||||
KEEP(*(.option_setting_pbps_sec3))
|
||||
. = __OPTION_SETTING_S_Start + 0x80;
|
||||
KEEP(*(.option_setting_ofs1_sel))
|
||||
. = __OPTION_SETTING_S_Start + 0x84;
|
||||
KEEP(*(.option_setting_ofs3_sel))
|
||||
. = __OPTION_SETTING_S_Start + 0x90;
|
||||
KEEP(*(.option_setting_banksel_sel))
|
||||
. = __OPTION_SETTING_S_Start + 0xC0;
|
||||
KEEP(*(.option_setting_bps_sel0))
|
||||
. = __OPTION_SETTING_S_Start + 0xC4;
|
||||
KEEP(*(.option_setting_bps_sel1))
|
||||
. = __OPTION_SETTING_S_Start + 0xC8;
|
||||
KEEP(*(.option_setting_bps_sel2))
|
||||
. = __OPTION_SETTING_S_Start + 0xCC;
|
||||
KEEP(*(.option_setting_bps_sel3))
|
||||
__OPTION_SETTING_S_End = .;
|
||||
} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
|
||||
74
soc/renesas/ra/ra6m5/soc.c
Normal file
74
soc/renesas/ra/ra6m5/soc.c
Normal file
|
|
@ -0,0 +1,74 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief System/hardware module for Renesas RA6M5 family processor
|
||||
*/
|
||||
|
||||
#include <zephyr/device.h>
|
||||
#include <zephyr/init.h>
|
||||
#include <zephyr/kernel.h>
|
||||
#include <zephyr/arch/cpu.h>
|
||||
#include <cmsis_core.h>
|
||||
#include <zephyr/irq.h>
|
||||
#include <zephyr/logging/log.h>
|
||||
LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
|
||||
|
||||
#include "bsp_cfg.h"
|
||||
#include <bsp_api.h>
|
||||
|
||||
uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
|
||||
|
||||
volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
|
||||
|
||||
/**
|
||||
* @brief Perform basic hardware initialization at boot.
|
||||
*
|
||||
* This needs to be run from the very beginning.
|
||||
* So the init priority has to be 0 (zero).
|
||||
*
|
||||
* @return 0
|
||||
*/
|
||||
static int renesas_ra6m5_init(void)
|
||||
{
|
||||
uint32_t key;
|
||||
|
||||
key = irq_lock();
|
||||
|
||||
extern volatile uint16_t g_protect_counters[];
|
||||
for (uint32_t i = 0; i < 4; i++) {
|
||||
g_protect_counters[i] = 0;
|
||||
}
|
||||
|
||||
#if FSP_PRIV_TZ_USE_SECURE_REGS
|
||||
/* Disable protection using PRCR register. */
|
||||
R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);
|
||||
|
||||
/* Initialize peripherals to secure mode for flat projects */
|
||||
R_PSCU->PSARB = 0;
|
||||
R_PSCU->PSARC = 0;
|
||||
R_PSCU->PSARD = 0;
|
||||
R_PSCU->PSARE = 0;
|
||||
|
||||
R_CPSCU->ICUSARG = 0;
|
||||
R_CPSCU->ICUSARH = 0;
|
||||
R_CPSCU->ICUSARI = 0;
|
||||
|
||||
/* Enable protection using PRCR register. */
|
||||
R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);
|
||||
#endif
|
||||
|
||||
SystemCoreClock = BSP_MOCO_HZ;
|
||||
g_protect_pfswe_counter = 0;
|
||||
bsp_clock_init();
|
||||
|
||||
irq_unlock(key);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(renesas_ra6m5_init, PRE_KERNEL_1, 0);
|
||||
16
soc/renesas/ra/ra6m5/soc.h
Normal file
16
soc/renesas/ra/ra6m5/soc.h
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SoC configuration macros for the Renesas RA6M5 family MCU
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_RENESAS_RA6M5_SOC_H_
|
||||
#define ZEPHYR_SOC_RENESAS_RA6M5_SOC_H_
|
||||
|
||||
#include <bsp_api.h>
|
||||
|
||||
#endif /* ZEPHYR_SOC_RENESAS_RA6M5_SOC_H_ */
|
||||
|
|
@ -13,3 +13,6 @@ family:
|
|||
- name: ra8t1
|
||||
socs:
|
||||
- name: r7fa8t1ahecbd
|
||||
- name: ra6m5
|
||||
socs:
|
||||
- name: r7fa6m5bh3cfc
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue