riscv32: timer: replace riscv_qemu_driver by the generic riscv_machine_driver
riscv defines the machine-mode timer registers that are implemented by the all riscv SOCs that follow the riscv privileged architecture specification. The timer registers implemented in riscv-qemu follow this specification. To account for future riscv SOCs, reimplement the riscv_qemu_driver by the riscv_machine_driver. Change-Id: I645b03c91b4e07d0f2609908decc27ba9b8240d4 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
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9 changed files with 122 additions and 120 deletions
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@ -15,7 +15,7 @@
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#define RISCV_QEMU_MSTATUS mstatus /* Machine Status Register */
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/* IRQ numbers */
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#define RISCV_QEMU_TIMER_IRQ 7 /* Timer Interrupt */
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#define RISCV_MACHINE_TIMER_IRQ 7 /* Machine Timer Interrupt */
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/* Exception numbers */
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#define RISCV_QEMU_ECALL_EXP 11 /* ECALL Instruction */
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@ -53,7 +53,8 @@
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#define RISCV_QEMU_UART_BASE 0x40002000
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/* Timer configuration */
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#define RISCV_QEMU_TIMER_BASE 0x40000000
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#define RISCV_MTIME_BASE 0x40000000
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#define RISCV_MTIMECMP_BASE 0x40000008
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#ifndef _ASMLANGUAGE
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#include <irq.h>
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@ -39,8 +39,8 @@ SECTION_FUNC(exception.other, __soc_is_irq)
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li t1, SOC_MCAUSE_IRQ_MASK
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and t0, t0, t1
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/* if IRQ number != RISCV_QEMU_TIMER_IRQ, not interrupt */
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li t1, RISCV_QEMU_TIMER_IRQ
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/* if IRQ number != RISCV_MACHINE_TIMER_IRQ, not interrupt */
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li t1, RISCV_MACHINE_TIMER_IRQ
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addi a0, x0, 0
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bne t0, t1, not_interrupt
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addi a0, a0, 1
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@ -7,5 +7,5 @@ CONFIG_SERIAL=y
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CONFIG_UART_RISCV_QEMU=y
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CONFIG_UART_CONSOLE=y
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CONFIG_UART_CONSOLE_ON_DEV_NAME="uart0"
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CONFIG_RISCV_QEMU_TIMER=y
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CONFIG_RISCV_MACHINE_TIMER=y
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CONFIG_BOOT_BANNER=y
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@ -157,12 +157,12 @@ config PULPINO_TIMER
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This module implements a kernel device driver for the pulpino processor
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timer driver. It provides the standard "system clock driver" interfaces.
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config RISCV_QEMU_TIMER
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bool "riscv-qemu Timer"
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config RISCV_MACHINE_TIMER
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bool "RISCV Machine Timer"
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default y
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depends on SOC_RISCV32_QEMU
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depends on RISCV32
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help
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This module implements a kernel device driver for the riscv32-qemu
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This module implements a kernel device driver for the generic RISCV machine
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timer driver. It provides the standard "system clock driver" interfaces.
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config SYSTEM_CLOCK_DISABLE
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@ -4,7 +4,7 @@ obj-$(CONFIG_ARCV2_TIMER) += arcv2_timer0.o
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obj-$(CONFIG_ALTERA_AVALON_TIMER) += altera_avalon_timer.o
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obj-$(CONFIG_NRF_RTC_TIMER) += nrf_rtc_timer.o
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obj-$(CONFIG_PULPINO_TIMER) += pulpino_timer.o
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obj-$(CONFIG_RISCV_QEMU_TIMER) += riscv_qemu_timer.o
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obj-$(CONFIG_RISCV_MACHINE_TIMER) += riscv_machine_timer.o
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obj-$(CONFIG_CORTEX_M_SYSTICK) += cortex_m_systick.o
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107
drivers/timer/riscv_machine_timer.c
Normal file
107
drivers/timer/riscv_machine_timer.c
Normal file
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@ -0,0 +1,107 @@
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/*
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* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <device.h>
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#include <system_timer.h>
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#include <board.h>
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typedef struct {
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uint32_t val_low;
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uint32_t val_high;
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} riscv_machine_timer_t;
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static volatile riscv_machine_timer_t *mtime =
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(riscv_machine_timer_t *)RISCV_MTIME_BASE;
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static volatile riscv_machine_timer_t *mtimecmp =
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(riscv_machine_timer_t *)RISCV_MTIMECMP_BASE;
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static uint32_t accumulated_cycle_count;
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static uint64_t last_rtc_value;
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/*
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* The RISCV machine-mode timer is a one shot timer that needs to be rearm upon
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* every interrupt. Timer clock is a 64-bits ART.
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* To arm timer, we need to read the RTC value and update the
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* timer compare register by the RTC value + time interval we want timer
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* to interrupt.
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*/
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static ALWAYS_INLINE void riscv_machine_rearm_timer(void)
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{
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uint64_t rtc;
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/*
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* Following machine-mode timer implementation in QEMU, the actual
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* RTC read is performed when reading low timer value register.
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* Reading high timer value just reads the most significant 32-bits
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* of a cache value, obtained from a previous read to the low
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* timer value register. Hence, always read timer->val_low first.
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* This also works for other implementations.
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*/
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rtc = mtime->val_low;
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rtc |= ((uint64_t)mtime->val_high << 32);
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last_rtc_value = rtc;
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/*
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* Rearm timer to generate an interrupt after
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* sys_clock_hw_cycles_per_tick
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*/
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rtc += sys_clock_hw_cycles_per_tick;
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mtimecmp->val_low = (uint32_t)(rtc & 0xffffffff);
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mtimecmp->val_high = (uint32_t)((rtc >> 32) & 0xffffffff);
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}
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static void riscv_machine_timer_irq_handler(void *unused)
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{
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ARG_UNUSED(unused);
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accumulated_cycle_count += sys_clock_hw_cycles_per_tick;
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_sys_clock_tick_announce();
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/* Rearm timer */
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riscv_machine_rearm_timer();
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}
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#ifdef CONFIG_TICKLESS_IDLE
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#error "Tickless idle not yet implemented for riscv-machine timer"
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#endif
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int _sys_clock_driver_init(struct device *device)
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{
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ARG_UNUSED(device);
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IRQ_CONNECT(RISCV_MACHINE_TIMER_IRQ, 0,
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riscv_machine_timer_irq_handler, NULL, 0);
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irq_enable(RISCV_MACHINE_TIMER_IRQ);
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/* Initialize timer, just call riscv_machine_rearm_timer */
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riscv_machine_rearm_timer();
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return 0;
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}
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/**
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*
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* @brief Read the platform's timer hardware
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*
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* This routine returns the current time in terms of timer hardware clock
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* cycles.
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*
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* @return up counter of elapsed clock cycles
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*/
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uint32_t k_cycle_get_32(void)
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{
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uint64_t rtc;
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rtc = mtime->val_low;
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rtc |= ((uint64_t)mtime->val_high << 32);
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/* rtc - last_rtc_value is always <= sys_clock_hw_cycles_per_tick */
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return accumulated_cycle_count + (uint32_t)(rtc - last_rtc_value);
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}
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@ -1,106 +0,0 @@
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/*
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* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <device.h>
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#include <system_timer.h>
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#include <board.h>
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typedef struct {
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uint32_t val_low;
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uint32_t val_high;
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uint32_t cmp_low;
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uint32_t cmp_high;
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} riscv_qemu_timer_t;
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static volatile riscv_qemu_timer_t *timer =
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(riscv_qemu_timer_t *)RISCV_QEMU_TIMER_BASE;
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static uint32_t accumulated_cycle_count;
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static uint64_t last_rtc_value;
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/*
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* riscv-qemu timer is a one shot timer that needs to be rearm upon
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* every interrupt. Timer clock is a 64-bits ART.
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* To arm timer, we need to read the RTC value and update the
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* timer compare register by the RTC value + time interval we want timer
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* to interrupt.
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*/
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static ALWAYS_INLINE void riscv_qemu_rearm_timer(void)
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{
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uint64_t rtc;
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/*
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* Following qemu implementation, the actual RTC read is performed
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* when reading low timer value register. Reading high timer value
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* just reads the most significant 32-bits of a cache value, obtained
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* from a previous read to the low timer value register.
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* Hence, always read timer->val_low first.
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*/
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rtc = timer->val_low;
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rtc |= ((uint64_t)timer->val_high << 32);
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last_rtc_value = rtc;
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/*
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* Rearm timer to generate an interrupt after
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* sys_clock_hw_cycles_per_tick
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*/
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rtc += sys_clock_hw_cycles_per_tick;
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timer->cmp_low = (uint32_t)(rtc & 0xffffffff);
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timer->cmp_high = (uint32_t)((rtc >> 32) & 0xffffffff);
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}
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static void riscv_qemu_timer_irq_handler(void *unused)
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{
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ARG_UNUSED(unused);
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accumulated_cycle_count += sys_clock_hw_cycles_per_tick;
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_sys_clock_tick_announce();
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/* Rearm timer */
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riscv_qemu_rearm_timer();
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}
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#ifdef CONFIG_TICKLESS_IDLE
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#error "Tickless idle not yet implemented for riscv32-qemu timer"
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#endif
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int _sys_clock_driver_init(struct device *device)
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{
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ARG_UNUSED(device);
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IRQ_CONNECT(RISCV_QEMU_TIMER_IRQ, 0,
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riscv_qemu_timer_irq_handler, NULL, 0);
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irq_enable(RISCV_QEMU_TIMER_IRQ);
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/* Initialize timer, just call riscv_qemu_rearm_timer */
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riscv_qemu_rearm_timer();
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return 0;
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}
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/**
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*
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* @brief Read the platform's timer hardware
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*
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* This routine returns the current time in terms of timer hardware clock
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* cycles.
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*
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* @return up counter of elapsed clock cycles
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*/
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uint32_t k_cycle_get_32(void)
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{
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uint64_t rtc;
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rtc = timer->val_low;
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rtc |= ((uint64_t)timer->val_high << 32);
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/* rtc - last_rtc_value is always <= sys_clock_hw_cycles_per_tick */
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return accumulated_cycle_count + (uint32_t)(rtc - last_rtc_value);
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}
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@ -57,8 +57,8 @@
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#define TICK_IRQ IRQ_TIMER0
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#elif defined(CONFIG_PULPINO_TIMER)
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#define TICK_IRQ PULP_TIMER_A_CMP_IRQ
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#elif defined(CONFIG_RISCV_QEMU_TIMER)
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#define TICK_IRQ RISCV_QEMU_TIMER_IRQ
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#elif defined(CONFIG_RISCV_MACHINE_TIMER)
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#define TICK_IRQ RISCV_MACHINE_TIMER_IRQ
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#elif defined(CONFIG_CPU_CORTEX_M)
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/*
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* The Cortex-M use the SYSTICK exception for the system timer, which is
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@ -58,8 +58,8 @@
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#define TICK_IRQ IRQ_TIMER0
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#elif defined(CONFIG_PULPINO_TIMER)
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#define TICK_IRQ PULP_TIMER_A_CMP_IRQ
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#elif defined(CONFIG_RISCV_QEMU_TIMER)
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#define TICK_IRQ RISCV_QEMU_TIMER_IRQ
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#elif defined(CONFIG_RISCV_MACHINE_TIMER)
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#define TICK_IRQ RISCV_MACHINE_TIMER_IRQ
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#elif defined(CONFIG_CPU_CORTEX_M)
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/*
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* The Cortex-M use the SYSTICK exception for the system timer, which is
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