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riscv32: timer: replace riscv_qemu_driver by the generic riscv_machine_driver

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riscv defines the machine-mode timer registers that are implemented
by the all riscv SOCs that follow the riscv privileged architecture
specification.

The timer registers implemented in riscv-qemu follow this specification.
To account for future riscv SOCs, reimplement the riscv_qemu_driver by
the riscv_machine_driver.

Change-Id: I645b03c91b4e07d0f2609908decc27ba9b8240d4
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
This commit is contained in:
Jean-Paul Etienne 2017-01-24 01:03:56 +01:00
commit c989f0b408
9 changed files with 122 additions and 120 deletions
Download patch file Download diff file Expand all files Collapse all files

5
arch/riscv32/soc/riscv32-qemu/soc.h
View file

@ -15,7 +15,7 @@
#define RISCV_QEMU_MSTATUS mstatus /* Machine Status Register */
/* IRQ numbers */
#define RISCV_QEMU_TIMER_IRQ 7 /* Timer Interrupt */
#define RISCV_MACHINE_TIMER_IRQ 7 /* Machine Timer Interrupt */
/* Exception numbers */
#define RISCV_QEMU_ECALL_EXP 11 /* ECALL Instruction */
@ -53,7 +53,8 @@
#define RISCV_QEMU_UART_BASE 0x40002000
/* Timer configuration */
#define RISCV_QEMU_TIMER_BASE 0x40000000
#define RISCV_MTIME_BASE 0x40000000
#define RISCV_MTIMECMP_BASE 0x40000008
#ifndef _ASMLANGUAGE
#include <irq.h>

4
arch/riscv32/soc/riscv32-qemu/soc_irq.S
View file

@ -39,8 +39,8 @@ SECTION_FUNC(exception.other, __soc_is_irq)
li t1, SOC_MCAUSE_IRQ_MASK
and t0, t0, t1
/* if IRQ number != RISCV_QEMU_TIMER_IRQ, not interrupt */
li t1, RISCV_QEMU_TIMER_IRQ
/* if IRQ number != RISCV_MACHINE_TIMER_IRQ, not interrupt */
li t1, RISCV_MACHINE_TIMER_IRQ
addi a0, x0, 0
bne t0, t1, not_interrupt
addi a0, a0, 1

2
boards/riscv32/qemu_riscv32/qemu_riscv32_defconfig
View file

@ -7,5 +7,5 @@ CONFIG_SERIAL=y
CONFIG_UART_RISCV_QEMU=y
CONFIG_UART_CONSOLE=y
CONFIG_UART_CONSOLE_ON_DEV_NAME="uart0"
CONFIG_RISCV_QEMU_TIMER=y
CONFIG_RISCV_MACHINE_TIMER=y
CONFIG_BOOT_BANNER=y

8
drivers/timer/Kconfig
View file

@ -157,12 +157,12 @@ config PULPINO_TIMER
This module implements a kernel device driver for the pulpino processor
timer driver. It provides the standard "system clock driver" interfaces.
config RISCV_QEMU_TIMER
bool "riscv-qemu Timer"
config RISCV_MACHINE_TIMER
bool "RISCV Machine Timer"
default y
depends on SOC_RISCV32_QEMU
depends on RISCV32
help
This module implements a kernel device driver for the riscv32-qemu
This module implements a kernel device driver for the generic RISCV machine
timer driver. It provides the standard "system clock driver" interfaces.
config SYSTEM_CLOCK_DISABLE

2
drivers/timer/Makefile
View file

@ -4,7 +4,7 @@ obj-$(CONFIG_ARCV2_TIMER) += arcv2_timer0.o
obj-$(CONFIG_ALTERA_AVALON_TIMER) += altera_avalon_timer.o
obj-$(CONFIG_NRF_RTC_TIMER) += nrf_rtc_timer.o
obj-$(CONFIG_PULPINO_TIMER) += pulpino_timer.o
obj-$(CONFIG_RISCV_QEMU_TIMER) += riscv_qemu_timer.o
obj-$(CONFIG_RISCV_MACHINE_TIMER) += riscv_machine_timer.o
obj-$(CONFIG_CORTEX_M_SYSTICK) += cortex_m_systick.o

107
drivers/timer/riscv_machine_timer.c Normal file
View file

@ -0,0 +1,107 @@
/*
* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <kernel.h>
#include <arch/cpu.h>
#include <device.h>
#include <system_timer.h>
#include <board.h>
typedef struct {
uint32_t val_low;
uint32_t val_high;
} riscv_machine_timer_t;
static volatile riscv_machine_timer_t *mtime =
(riscv_machine_timer_t *)RISCV_MTIME_BASE;
static volatile riscv_machine_timer_t *mtimecmp =
(riscv_machine_timer_t *)RISCV_MTIMECMP_BASE;
static uint32_t accumulated_cycle_count;
static uint64_t last_rtc_value;
/*
* The RISCV machine-mode timer is a one shot timer that needs to be rearm upon
* every interrupt. Timer clock is a 64-bits ART.
* To arm timer, we need to read the RTC value and update the
* timer compare register by the RTC value + time interval we want timer
* to interrupt.
*/
static ALWAYS_INLINE void riscv_machine_rearm_timer(void)
{
uint64_t rtc;
/*
* Following machine-mode timer implementation in QEMU, the actual
* RTC read is performed when reading low timer value register.
* Reading high timer value just reads the most significant 32-bits
* of a cache value, obtained from a previous read to the low
* timer value register. Hence, always read timer->val_low first.
* This also works for other implementations.
*/
rtc = mtime->val_low;
rtc |= ((uint64_t)mtime->val_high << 32);
last_rtc_value = rtc;
/*
* Rearm timer to generate an interrupt after
* sys_clock_hw_cycles_per_tick
*/
rtc += sys_clock_hw_cycles_per_tick;
mtimecmp->val_low = (uint32_t)(rtc & 0xffffffff);
mtimecmp->val_high = (uint32_t)((rtc >> 32) & 0xffffffff);
}
static void riscv_machine_timer_irq_handler(void *unused)
{
ARG_UNUSED(unused);
accumulated_cycle_count += sys_clock_hw_cycles_per_tick;
_sys_clock_tick_announce();
/* Rearm timer */
riscv_machine_rearm_timer();
}
#ifdef CONFIG_TICKLESS_IDLE
#error "Tickless idle not yet implemented for riscv-machine timer"
#endif
int _sys_clock_driver_init(struct device *device)
{
ARG_UNUSED(device);
IRQ_CONNECT(RISCV_MACHINE_TIMER_IRQ, 0,
riscv_machine_timer_irq_handler, NULL, 0);
irq_enable(RISCV_MACHINE_TIMER_IRQ);
/* Initialize timer, just call riscv_machine_rearm_timer */
riscv_machine_rearm_timer();
return 0;
}
/**
*
* @brief Read the platform's timer hardware
*
* This routine returns the current time in terms of timer hardware clock
* cycles.
*
* @return up counter of elapsed clock cycles
*/
uint32_t k_cycle_get_32(void)
{
uint64_t rtc;
rtc = mtime->val_low;
rtc |= ((uint64_t)mtime->val_high << 32);
/* rtc - last_rtc_value is always <= sys_clock_hw_cycles_per_tick */
return accumulated_cycle_count + (uint32_t)(rtc - last_rtc_value);
}

106
drivers/timer/riscv_qemu_timer.c
View file

@ -1,106 +0,0 @@
/*
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <kernel.h>
#include <arch/cpu.h>
#include <device.h>
#include <system_timer.h>
#include <board.h>
typedef struct {
uint32_t val_low;
uint32_t val_high;
uint32_t cmp_low;
uint32_t cmp_high;
} riscv_qemu_timer_t;
static volatile riscv_qemu_timer_t *timer =
(riscv_qemu_timer_t *)RISCV_QEMU_TIMER_BASE;
static uint32_t accumulated_cycle_count;
static uint64_t last_rtc_value;
/*
* riscv-qemu timer is a one shot timer that needs to be rearm upon
* every interrupt. Timer clock is a 64-bits ART.
* To arm timer, we need to read the RTC value and update the
* timer compare register by the RTC value + time interval we want timer
* to interrupt.
*/
static ALWAYS_INLINE void riscv_qemu_rearm_timer(void)
{
uint64_t rtc;
/*
* Following qemu implementation, the actual RTC read is performed
* when reading low timer value register. Reading high timer value
* just reads the most significant 32-bits of a cache value, obtained
* from a previous read to the low timer value register.
* Hence, always read timer->val_low first.
*/
rtc = timer->val_low;
rtc |= ((uint64_t)timer->val_high << 32);
last_rtc_value = rtc;
/*
* Rearm timer to generate an interrupt after
* sys_clock_hw_cycles_per_tick
*/
rtc += sys_clock_hw_cycles_per_tick;
timer->cmp_low = (uint32_t)(rtc & 0xffffffff);
timer->cmp_high = (uint32_t)((rtc >> 32) & 0xffffffff);
}
static void riscv_qemu_timer_irq_handler(void *unused)
{
ARG_UNUSED(unused);
accumulated_cycle_count += sys_clock_hw_cycles_per_tick;
_sys_clock_tick_announce();
/* Rearm timer */
riscv_qemu_rearm_timer();
}
#ifdef CONFIG_TICKLESS_IDLE
#error "Tickless idle not yet implemented for riscv32-qemu timer"
#endif
int _sys_clock_driver_init(struct device *device)
{
ARG_UNUSED(device);
IRQ_CONNECT(RISCV_QEMU_TIMER_IRQ, 0,
riscv_qemu_timer_irq_handler, NULL, 0);
irq_enable(RISCV_QEMU_TIMER_IRQ);
/* Initialize timer, just call riscv_qemu_rearm_timer */
riscv_qemu_rearm_timer();
return 0;
}
/**
*
* @brief Read the platform's timer hardware
*
* This routine returns the current time in terms of timer hardware clock
* cycles.
*
* @return up counter of elapsed clock cycles
*/
uint32_t k_cycle_get_32(void)
{
uint64_t rtc;
rtc = timer->val_low;
rtc |= ((uint64_t)timer->val_high << 32);
/* rtc - last_rtc_value is always <= sys_clock_hw_cycles_per_tick */
return accumulated_cycle_count + (uint32_t)(rtc - last_rtc_value);
}

4
tests/kernel/context/src/context.c
View file

@ -57,8 +57,8 @@
#define TICK_IRQ IRQ_TIMER0
#elif defined(CONFIG_PULPINO_TIMER)
#define TICK_IRQ PULP_TIMER_A_CMP_IRQ
#elif defined(CONFIG_RISCV_QEMU_TIMER)
#define TICK_IRQ RISCV_QEMU_TIMER_IRQ
#elif defined(CONFIG_RISCV_MACHINE_TIMER)
#define TICK_IRQ RISCV_MACHINE_TIMER_IRQ
#elif defined(CONFIG_CPU_CORTEX_M)
/*
* The Cortex-M use the SYSTICK exception for the system timer, which is

4
tests/legacy/kernel/test_context/src/context.c
View file

@ -58,8 +58,8 @@
#define TICK_IRQ IRQ_TIMER0
#elif defined(CONFIG_PULPINO_TIMER)
#define TICK_IRQ PULP_TIMER_A_CMP_IRQ
#elif defined(CONFIG_RISCV_QEMU_TIMER)
#define TICK_IRQ RISCV_QEMU_TIMER_IRQ
#elif defined(CONFIG_RISCV_MACHINE_TIMER)
#define TICK_IRQ RISCV_MACHINE_TIMER_IRQ
#elif defined(CONFIG_CPU_CORTEX_M)
/*
* The Cortex-M use the SYSTICK exception for the system timer, which is