diff --git a/boards/xtensa/intel_s1000_crb/intel_s1000_crb_defconfig b/boards/xtensa/intel_s1000_crb/intel_s1000_crb_defconfig
index 3fb4888e9d2..255882862eb 100644
--- a/boards/xtensa/intel_s1000_crb/intel_s1000_crb_defconfig
+++ b/boards/xtensa/intel_s1000_crb/intel_s1000_crb_defconfig
@@ -52,3 +52,5 @@ CONFIG_UART_NS16550=y
 CONFIG_AUDIO=y
 CONFIG_AUDIO_CODEC=y
 CONFIG_AUDIO_TLV320DAC=y
+CONFIG_AUDIO_DMIC=y
+CONFIG_AUDIO_INTEL_DMIC=y
diff --git a/drivers/audio/CMakeLists.txt b/drivers/audio/CMakeLists.txt
index 701d63e27f4..49b05d66bf3 100644
--- a/drivers/audio/CMakeLists.txt
+++ b/drivers/audio/CMakeLists.txt
@@ -1,3 +1,13 @@
 zephyr_library()
 
 zephyr_library_sources_ifdef(CONFIG_AUDIO_TLV320DAC	tlv320dac310x.c)
+zephyr_library_sources_ifdef(CONFIG_AUDIO_INTEL_DMIC	intel_dmic.c)
+zephyr_library_sources_ifdef(CONFIG_AUDIO_INTEL_DMIC	decimation/pdm_decim_int32_02_4288_5100_010_095.c)
+zephyr_library_sources_ifdef(CONFIG_AUDIO_INTEL_DMIC	decimation/pdm_decim_int32_02_4375_5100_010_095.c)
+zephyr_library_sources_ifdef(CONFIG_AUDIO_INTEL_DMIC	decimation/pdm_decim_int32_03_3850_5100_010_095.c)
+zephyr_library_sources_ifdef(CONFIG_AUDIO_INTEL_DMIC	decimation/pdm_decim_int32_03_4375_5100_010_095.c)
+zephyr_library_sources_ifdef(CONFIG_AUDIO_INTEL_DMIC	decimation/pdm_decim_int32_04_4375_5100_010_095.c)
+zephyr_library_sources_ifdef(CONFIG_AUDIO_INTEL_DMIC	decimation/pdm_decim_int32_05_4331_5100_010_095.c)
+zephyr_library_sources_ifdef(CONFIG_AUDIO_INTEL_DMIC	decimation/pdm_decim_int32_06_4156_5100_010_095.c)
+zephyr_library_sources_ifdef(CONFIG_AUDIO_INTEL_DMIC	decimation/pdm_decim_int32_08_4156_5380_010_090.c)
+zephyr_library_sources_ifdef(CONFIG_AUDIO_INTEL_DMIC	decimation/pdm_decim_table.c)
diff --git a/drivers/audio/Kconfig b/drivers/audio/Kconfig
index 5de26185e42..bfeea859d14 100644
--- a/drivers/audio/Kconfig
+++ b/drivers/audio/Kconfig
@@ -35,4 +35,26 @@ source "subsys/logging/Kconfig.template.log_config"
 source "drivers/audio/Kconfig.tlv320dac"
 
 endif # AUDIO_CODEC
+
+menuconfig AUDIO_DMIC
+	bool "Digital Microphone (Audio) Drivers"
+	help
+	  Enable Digital Microphone Driver Configuration
+
+if AUDIO_DMIC
+
+config AUDIO_DMIC_INIT_PRIORITY
+	int "Init priority"
+	default 60
+	help
+	  Audio Digital Microphone device driver initialization priority.
+
+module = AUDIO_DMIC
+module-str = audio_dmic
+source "subsys/logging/Kconfig.template.log_config"
+
+source "drivers/audio/Kconfig.intel_dmic"
+
+endif # AUDIO_DMIC
+
 endif # AUDIO
diff --git a/drivers/audio/Kconfig.intel_dmic b/drivers/audio/Kconfig.intel_dmic
new file mode 100644
index 00000000000..ff2b5879540
--- /dev/null
+++ b/drivers/audio/Kconfig.intel_dmic
@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2018 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+menuconfig AUDIO_INTEL_DMIC
+	bool "Intel digital PDM microphone driver support"
+	depends on AUDIO_DMIC
+	help
+	  Enable Intel digital PDM microphone driver
diff --git a/drivers/audio/decimation/pdm_decim_fir.h b/drivers/audio/decimation/pdm_decim_fir.h
new file mode 100644
index 00000000000..589a7a82c07
--- /dev/null
+++ b/drivers/audio/decimation/pdm_decim_fir.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2018, Intel Corporation
+ * All rights reserved.
+ *
+ * Author:	Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
+ *		Sathish Kuttan <sathish.k.kuttan@intel.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __PDM_DECIM_FIR__H__
+#define __PDM_DECIM_FIR__H__
+
+#define DMIC_FIR_LIST_LENGTH 8
+
+/* Format for generated coefficients tables */
+
+struct pdm_decim {
+	int decim_factor;
+	int length;
+	int shift;
+	int relative_passband;
+	int relative_stopband;
+	int passband_ripple;
+	int stopband_ripple;
+	const s32_t *coef;
+};
+
+struct pdm_decim **pdm_decim_get_fir_list(void);
+
+#endif /* __PDM_DECIM_FIR__H__ */
diff --git a/drivers/audio/decimation/pdm_decim_int32_02_4288_5100_010_095.c b/drivers/audio/decimation/pdm_decim_int32_02_4288_5100_010_095.c
new file mode 100644
index 00000000000..d6c92e1fc1b
--- /dev/null
+++ b/drivers/audio/decimation/pdm_decim_int32_02_4288_5100_010_095.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2018, Intel Corporation
+ * All rights reserved.
+ *
+ * Author:	Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
+ *		Sathish Kuttan <sathish.k.kuttan@intel.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr.h>
+
+#include "pdm_decim_fir.h"
+
+static const s32_t fir_int32_02_4288_5100_010_095[91] = {
+	-193886,
+	104552,
+	2140521,
+	5355562,
+	5945318,
+	1216991,
+	-4511367,
+	-3527243,
+	3415937,
+	5526880,
+	-1935806,
+	-7515849,
+	-386524,
+	9252379,
+	3862172,
+	-10093681,
+	-8251552,
+	9738620,
+	13536988,
+	-7464432,
+	-19100785,
+	2935187,
+	24375729,
+	4314479,
+	-28271418,
+	-14141458,
+	29999307,
+	26636531,
+	-28180625,
+	-41208987,
+	21649022,
+	57264356,
+	-8757879,
+	-73520802,
+	-12043366,
+	88868414,
+	43784598,
+	-101162825,
+	-91853580,
+	106519993,
+	169110273,
+	-94206010,
+	-317139630,
+	5894310,
+	739661049,
+	1132200744,
+	739661049,
+	5894310,
+	-317139630,
+	-94206010,
+	169110273,
+	106519993,
+	-91853580,
+	-101162825,
+	43784598,
+	88868414,
+	-12043366,
+	-73520802,
+	-8757879,
+	57264356,
+	21649022,
+	-41208987,
+	-28180625,
+	26636531,
+	29999307,
+	-14141458,
+	-28271418,
+	4314479,
+	24375729,
+	2935187,
+	-19100785,
+	-7464432,
+	13536988,
+	9738620,
+	-8251552,
+	-10093681,
+	3862172,
+	9252379,
+	-386524,
+	-7515849,
+	-1935806,
+	5526880,
+	3415937,
+	-3527243,
+	-4511367,
+	1216991,
+	5945318,
+	5355562,
+	2140521,
+	104552,
+	-193886
+
+};
+
+struct pdm_decim pdm_decim_int32_02_4288_5100_010_095 = {
+	2, 91, 0, 4288, 5100, 10, 95, fir_int32_02_4288_5100_010_095
+};
diff --git a/drivers/audio/decimation/pdm_decim_int32_02_4375_5100_010_095.c b/drivers/audio/decimation/pdm_decim_int32_02_4375_5100_010_095.c
new file mode 100644
index 00000000000..3a56104a1f9
--- /dev/null
+++ b/drivers/audio/decimation/pdm_decim_int32_02_4375_5100_010_095.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2018, Intel Corporation
+ * All rights reserved.
+ *
+ * Author:	Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
+ *		Sathish Kuttan <sathish.k.kuttan@intel.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr.h>
+
+#include "pdm_decim_fir.h"
+
+static const s32_t fir_int32_02_4375_5100_010_095[101] = {
+	-587830,
+	-2653881,
+	-5154608,
+	-4845367,
+	-226473,
+	4220832,
+	2571159,
+	-3184701,
+	-4043579,
+	2206821,
+	5554546,
+	-750496,
+	-6923900,
+	-1268584,
+	8073360,
+	4085183,
+	-8546477,
+	-7505364,
+	8176185,
+	11533751,
+	-6471060,
+	-15704256,
+	3359707,
+	19852409,
+	1635593,
+	-23144509,
+	-8252640,
+	25285013,
+	16574479,
+	-25723227,
+	-26663304,
+	23549736,
+	38139664,
+	-17943366,
+	-50446983,
+	8141043,
+	63090267,
+	7051351,
+	-75166959,
+	-29039894,
+	85772627,
+	60568979,
+	-93167356,
+	-106799776,
+	94198973,
+	180962815,
+	-78385592,
+	-324820245,
+	-12243140,
+	742491441,
+	1151461281,
+	742491441,
+	-12243140,
+	-324820245,
+	-78385592,
+	180962815,
+	94198973,
+	-106799776,
+	-93167356,
+	60568979,
+	85772627,
+	-29039894,
+	-75166959,
+	7051351,
+	63090267,
+	8141043,
+	-50446983,
+	-17943366,
+	38139664,
+	23549736,
+	-26663304,
+	-25723227,
+	16574479,
+	25285013,
+	-8252640,
+	-23144509,
+	1635593,
+	19852409,
+	3359707,
+	-15704256,
+	-6471060,
+	11533751,
+	8176185,
+	-7505364,
+	-8546477,
+	4085183,
+	8073360,
+	-1268584,
+	-6923900,
+	-750496,
+	5554546,
+	2206821,
+	-4043579,
+	-3184701,
+	2571159,
+	4220832,
+	-226473,
+	-4845367,
+	-5154608,
+	-2653881,
+	-587830
+
+};
+
+struct pdm_decim pdm_decim_int32_02_4375_5100_010_095 = {
+	2, 101, 0, 4375, 5100, 10, 95, fir_int32_02_4375_5100_010_095
+};
diff --git a/drivers/audio/decimation/pdm_decim_int32_03_3850_5100_010_095.c b/drivers/audio/decimation/pdm_decim_int32_03_3850_5100_010_095.c
new file mode 100644
index 00000000000..7ec22efdc25
--- /dev/null
+++ b/drivers/audio/decimation/pdm_decim_int32_03_3850_5100_010_095.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2018, Intel Corporation
+ * All rights reserved.
+ *
+ * Author:	Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
+ *		Sathish Kuttan <sathish.k.kuttan@intel.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr.h>
+
+#include "pdm_decim_fir.h"
+
+static const s32_t fir_int32_03_3850_5100_010_095[93] = {
+	44212,
+	-302176,
+	-1360920,
+	-3291119,
+	-5495374,
+	-6588668,
+	-5102927,
+	-753403,
+	4644861,
+	7677973,
+	5490212,
+	-1618066,
+	-9302333,
+	-11445730,
+	-4732005,
+	7709057,
+	17063964,
+	14699335,
+	-457541,
+	-18980508,
+	-26202607,
+	-13319132,
+	13695670,
+	35545996,
+	32740745,
+	1994202,
+	-37267233,
+	-54079734,
+	-29355959,
+	25448678,
+	71128406,
+	67328423,
+	5964667,
+	-74773313,
+	-111583346,
+	-62643893,
+	52737606,
+	154899783,
+	153311689,
+	16759099,
+	-184962926,
+	-304661987,
+	-201939017,
+	160731847,
+	673585388,
+	1122541471,
+	1300561761,
+	1122541471,
+	673585388,
+	160731847,
+	-201939017,
+	-304661987,
+	-184962926,
+	16759099,
+	153311689,
+	154899783,
+	52737606,
+	-62643893,
+	-111583346,
+	-74773313,
+	5964667,
+	67328423,
+	71128406,
+	25448678,
+	-29355959,
+	-54079734,
+	-37267233,
+	1994202,
+	32740745,
+	35545996,
+	13695670,
+	-13319132,
+	-26202607,
+	-18980508,
+	-457541,
+	14699335,
+	17063964,
+	7709057,
+	-4732005,
+	-11445730,
+	-9302333,
+	-1618066,
+	5490212,
+	7677973,
+	4644861,
+	-753403,
+	-5102927,
+	-6588668,
+	-5495374,
+	-3291119,
+	-1360920,
+	-302176,
+	44212
+
+};
+
+struct pdm_decim pdm_decim_int32_03_3850_5100_010_095 = {
+	3, 93, 1, 3850, 5100, 10, 95, fir_int32_03_3850_5100_010_095
+};
diff --git a/drivers/audio/decimation/pdm_decim_int32_03_4375_5100_010_095.c b/drivers/audio/decimation/pdm_decim_int32_03_4375_5100_010_095.c
new file mode 100644
index 00000000000..252abe21f2a
--- /dev/null
+++ b/drivers/audio/decimation/pdm_decim_int32_03_4375_5100_010_095.c
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2018, Intel Corporation
+ * All rights reserved.
+ *
+ * Author:	Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
+ *		Sathish Kuttan <sathish.k.kuttan@intel.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr.h>
+
+#include "pdm_decim_fir.h"
+
+static const s32_t fir_int32_03_4375_5100_010_095[157] = {
+	350904,
+	1127891,
+	2233546,
+	3059556,
+	2752177,
+	818057,
+	-2252661,
+	-4944515,
+	-5550704,
+	-3466227,
+	53089,
+	2496755,
+	1904111,
+	-1421730,
+	-4818556,
+	-5204443,
+	-1721082,
+	3155305,
+	5311444,
+	2454515,
+	-3518616,
+	-7589471,
+	-5713308,
+	1327821,
+	7901341,
+	7958087,
+	527903,
+	-8633996,
+	-11354795,
+	-4214518,
+	7627116,
+	13970242,
+	8263364,
+	-5861946,
+	-16549651,
+	-13529964,
+	2213919,
+	17870757,
+	19056207,
+	2854066,
+	-18029728,
+	-24979102,
+	-9860164,
+	16175117,
+	30545984,
+	18605951,
+	-11894271,
+	-35172531,
+	-28918160,
+	4746528,
+	38201092,
+	40590666,
+	5825429,
+	-38712951,
+	-53159148,
+	-20283384,
+	35723256,
+	66120531,
+	39265868,
+	-27910967,
+	-78795928,
+	-63663750,
+	13458962,
+	90416047,
+	95193346,
+	10755142,
+	-99897049,
+	-137497231,
+	-51075841,
+	105457455,
+	200047804,
+	124561003,
+	-101612190,
+	-313384381,
+	-297343743,
+	53701878,
+	639681661,
+	1187800564,
+	1411050887,
+	1187800564,
+	639681661,
+	53701878,
+	-297343743,
+	-313384381,
+	-101612190,
+	124561003,
+	200047804,
+	105457455,
+	-51075841,
+	-137497231,
+	-99897049,
+	10755142,
+	95193346,
+	90416047,
+	13458962,
+	-63663750,
+	-78795928,
+	-27910967,
+	39265868,
+	66120531,
+	35723256,
+	-20283384,
+	-53159148,
+	-38712951,
+	5825429,
+	40590666,
+	38201092,
+	4746528,
+	-28918160,
+	-35172531,
+	-11894271,
+	18605951,
+	30545984,
+	16175117,
+	-9860164,
+	-24979102,
+	-18029728,
+	2854066,
+	19056207,
+	17870757,
+	2213919,
+	-13529964,
+	-16549651,
+	-5861946,
+	8263364,
+	13970242,
+	7627116,
+	-4214518,
+	-11354795,
+	-8633996,
+	527903,
+	7958087,
+	7901341,
+	1327821,
+	-5713308,
+	-7589471,
+	-3518616,
+	2454515,
+	5311444,
+	3155305,
+	-1721082,
+	-5204443,
+	-4818556,
+	-1421730,
+	1904111,
+	2496755,
+	53089,
+	-3466227,
+	-5550704,
+	-4944515,
+	-2252661,
+	818057,
+	2752177,
+	3059556,
+	2233546,
+	1127891,
+	350904
+
+};
+
+struct pdm_decim pdm_decim_int32_03_4375_5100_010_095 = {
+	3, 157, 1, 4375, 5100, 10, 95, fir_int32_03_4375_5100_010_095
+};
diff --git a/drivers/audio/decimation/pdm_decim_int32_04_4375_5100_010_095.c b/drivers/audio/decimation/pdm_decim_int32_04_4375_5100_010_095.c
new file mode 100644
index 00000000000..b5478e20936
--- /dev/null
+++ b/drivers/audio/decimation/pdm_decim_int32_04_4375_5100_010_095.c
@@ -0,0 +1,232 @@
+/*
+ * Copyright (c) 2018, Intel Corporation
+ * All rights reserved.
+ *
+ * Author:	Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
+ *		Sathish Kuttan <sathish.k.kuttan@intel.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr.h>
+
+#include "pdm_decim_fir.h"
+
+static const s32_t fir_int32_04_4375_5100_010_095[211] = {
+	126017,
+	745791,
+	1735783,
+	3250059,
+	4963537,
+	6400069,
+	6949502,
+	6142229,
+	3902336,
+	705842,
+	-2485787,
+	-4540607,
+	-4626085,
+	-2636100,
+	646448,
+	3784383,
+	5275090,
+	4259502,
+	1015665,
+	-3045153,
+	-5950963,
+	-6099091,
+	-3115593,
+	1807814,
+	6342508,
+	8093924,
+	5838000,
+	296533,
+	-6011752,
+	-9879686,
+	-9013045,
+	-3339610,
+	4700101,
+	11152288,
+	12461593,
+	7387989,
+	-2085667,
+	-11448775,
+	-15769545,
+	-12252662,
+	-1940150,
+	10437445,
+	18576639,
+	17768944,
+	7550319,
+	-7626200,
+	-20251921,
+	-23428157,
+	-14572076,
+	2797464,
+	20329234,
+	28790530,
+	22864155,
+	4330980,
+	-18201801,
+	-33211863,
+	-32081436,
+	-13923851,
+	13233081,
+	35870337,
+	41620943,
+	25914222,
+	-4896316,
+	-35895437,
+	-50712381,
+	-40042952,
+	-7212823,
+	32428935,
+	58525317,
+	56015029,
+	23582638,
+	-24374765,
+	-63897455,
+	-73234460,
+	-44550852,
+	10604843,
+	65540282,
+	91054416,
+	70624752,
+	10408242,
+	-61706258,
+	-108584856,
+	-102490195,
+	-40744453,
+	50090298,
+	124919090,
+	141743373,
+	84173003,
+	-26760833,
+	-138851415,
+	-191966143,
+	-148464813,
+	-16173880,
+	148695193,
+	262835505,
+	254088691,
+	100293640,
+	-149816104,
+	-385869984,
+	-474827254,
+	-315628113,
+	112831849,
+	731720961,
+	1381072959,
+	1872325415,
+	2055132469,
+	1872325415,
+	1381072959,
+	731720961,
+	112831849,
+	-315628113,
+	-474827254,
+	-385869984,
+	-149816104,
+	100293640,
+	254088691,
+	262835505,
+	148695193,
+	-16173880,
+	-148464813,
+	-191966143,
+	-138851415,
+	-26760833,
+	84173003,
+	141743373,
+	124919090,
+	50090298,
+	-40744453,
+	-102490195,
+	-108584856,
+	-61706258,
+	10408242,
+	70624752,
+	91054416,
+	65540282,
+	10604843,
+	-44550852,
+	-73234460,
+	-63897455,
+	-24374765,
+	23582638,
+	56015029,
+	58525317,
+	32428935,
+	-7212823,
+	-40042952,
+	-50712381,
+	-35895437,
+	-4896316,
+	25914222,
+	41620943,
+	35870337,
+	13233081,
+	-13923851,
+	-32081436,
+	-33211863,
+	-18201801,
+	4330980,
+	22864155,
+	28790530,
+	20329234,
+	2797464,
+	-14572076,
+	-23428157,
+	-20251921,
+	-7626200,
+	7550319,
+	17768944,
+	18576639,
+	10437445,
+	-1940150,
+	-12252662,
+	-15769545,
+	-11448775,
+	-2085667,
+	7387989,
+	12461593,
+	11152288,
+	4700101,
+	-3339610,
+	-9013045,
+	-9879686,
+	-6011752,
+	296533,
+	5838000,
+	8093924,
+	6342508,
+	1807814,
+	-3115593,
+	-6099091,
+	-5950963,
+	-3045153,
+	1015665,
+	4259502,
+	5275090,
+	3784383,
+	646448,
+	-2636100,
+	-4626085,
+	-4540607,
+	-2485787,
+	705842,
+	3902336,
+	6142229,
+	6949502,
+	6400069,
+	4963537,
+	3250059,
+	1735783,
+	745791,
+	126017
+
+};
+
+struct pdm_decim pdm_decim_int32_04_4375_5100_010_095 = {
+	4, 211, 2, 4375, 5100, 10, 95, fir_int32_04_4375_5100_010_095
+};
diff --git a/drivers/audio/decimation/pdm_decim_int32_05_4331_5100_010_095.c b/drivers/audio/decimation/pdm_decim_int32_05_4331_5100_010_095.c
new file mode 100644
index 00000000000..1f1d3db35c3
--- /dev/null
+++ b/drivers/audio/decimation/pdm_decim_int32_05_4331_5100_010_095.c
@@ -0,0 +1,272 @@
+/*
+ * Copyright (c) 2018, Intel Corporation
+ * All rights reserved.
+ *
+ * Author:	Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
+ *		Sathish Kuttan <sathish.k.kuttan@intel.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr.h>
+
+#include "pdm_decim_fir.h"
+
+static const s32_t fir_int32_05_4331_5100_010_095[251] = {
+	-250963,
+	-530472,
+	-956449,
+	-1440505,
+	-1861966,
+	-2058350,
+	-1862594,
+	-1155766,
+	78930,
+	1719645,
+	3501958,
+	5061143,
+	6013975,
+	6066039,
+	5113131,
+	3303104,
+	1032343,
+	-1135681,
+	-2614668,
+	-2968117,
+	-2057986,
+	-118896,
+	2276521,
+	4363476,
+	5409644,
+	4953617,
+	2982225,
+	-20415,
+	-3181416,
+	-5487913,
+	-6107986,
+	-4685208,
+	-1505051,
+	2535666,
+	6167372,
+	8134966,
+	7619351,
+	4554012,
+	-280001,
+	-5435156,
+	-9220394,
+	-10246686,
+	-7922490,
+	-2726786,
+	3853867,
+	9734139,
+	12878468,
+	11991508,
+	7020539,
+	-717311,
+	-8859727,
+	-14705610,
+	-16097433,
+	-12195790,
+	-3874308,
+	6431337,
+	15415517,
+	19946809,
+	18139792,
+	10093658,
+	-1980159,
+	-14334496,
+	-22829097,
+	-24298020,
+	-17696570,
+	-4621840,
+	11019276,
+	24149376,
+	30144976,
+	26434112,
+	13524367,
+	-4930822,
+	-23124320,
+	-34892082,
+	-35768599,
+	-24626114,
+	-4311380,
+	19011680,
+	37690383,
+	45054463,
+	37744852,
+	17102968,
+	-10919933,
+	-37416293,
+	-53300866,
+	-52364722,
+	-33596881,
+	-1935268,
+	32928131,
+	59438198,
+	67925581,
+	54022129,
+	20569914,
+	-22737901,
+	-62048140,
+	-83661289,
+	-78659667,
+	-46330665,
+	4859442,
+	59276671,
+	98707953,
+	108233225,
+	81552245,
+	23955872,
+	-48257755,
+	-112070264,
+	-144691658,
+	-131171943,
+	-70276392,
+	23448172,
+	122479978,
+	193637242,
+	208100323,
+	151336952,
+	29895897,
+	-127299559,
+	-274102498,
+	-357874627,
+	-333256339,
+	-175377009,
+	111180608,
+	490397234,
+	900786668,
+	1268179136,
+	1522305381,
+	1613059887,
+	1522305381,
+	1268179136,
+	900786668,
+	490397234,
+	111180608,
+	-175377009,
+	-333256339,
+	-357874627,
+	-274102498,
+	-127299559,
+	29895897,
+	151336952,
+	208100323,
+	193637242,
+	122479978,
+	23448172,
+	-70276392,
+	-131171943,
+	-144691658,
+	-112070264,
+	-48257755,
+	23955872,
+	81552245,
+	108233225,
+	98707953,
+	59276671,
+	4859442,
+	-46330665,
+	-78659667,
+	-83661289,
+	-62048140,
+	-22737901,
+	20569914,
+	54022129,
+	67925581,
+	59438198,
+	32928131,
+	-1935268,
+	-33596881,
+	-52364722,
+	-53300866,
+	-37416293,
+	-10919933,
+	17102968,
+	37744852,
+	45054463,
+	37690383,
+	19011680,
+	-4311380,
+	-24626114,
+	-35768599,
+	-34892082,
+	-23124320,
+	-4930822,
+	13524367,
+	26434112,
+	30144976,
+	24149376,
+	11019276,
+	-4621840,
+	-17696570,
+	-24298020,
+	-22829097,
+	-14334496,
+	-1980159,
+	10093658,
+	18139792,
+	19946809,
+	15415517,
+	6431337,
+	-3874308,
+	-12195790,
+	-16097433,
+	-14705610,
+	-8859727,
+	-717311,
+	7020539,
+	11991508,
+	12878468,
+	9734139,
+	3853867,
+	-2726786,
+	-7922490,
+	-10246686,
+	-9220394,
+	-5435156,
+	-280001,
+	4554012,
+	7619351,
+	8134966,
+	6167372,
+	2535666,
+	-1505051,
+	-4685208,
+	-6107986,
+	-5487913,
+	-3181416,
+	-20415,
+	2982225,
+	4953617,
+	5409644,
+	4363476,
+	2276521,
+	-118896,
+	-2057986,
+	-2968117,
+	-2614668,
+	-1135681,
+	1032343,
+	3303104,
+	5113131,
+	6066039,
+	6013975,
+	5061143,
+	3501958,
+	1719645,
+	78930,
+	-1155766,
+	-1862594,
+	-2058350,
+	-1861966,
+	-1440505,
+	-956449,
+	-530472,
+	-250963
+
+};
+
+struct pdm_decim pdm_decim_int32_05_4331_5100_010_095 = {
+	5, 251, 2, 4331, 5100, 10, 95, fir_int32_05_4331_5100_010_095
+};
diff --git a/drivers/audio/decimation/pdm_decim_int32_06_4156_5100_010_095.c b/drivers/audio/decimation/pdm_decim_int32_06_4156_5100_010_095.c
new file mode 100644
index 00000000000..524058ddd11
--- /dev/null
+++ b/drivers/audio/decimation/pdm_decim_int32_06_4156_5100_010_095.c
@@ -0,0 +1,270 @@
+/*
+ * Copyright (c) 2018, Intel Corporation
+ * All rights reserved.
+ *
+ * Author:	Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
+ *		Sathish Kuttan <sathish.k.kuttan@intel.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr.h>
+
+#include "pdm_decim_fir.h"
+
+static const s32_t fir_int32_06_4156_5100_010_095[249] = {
+	-145670,
+	-159762,
+	-183049,
+	-132077,
+	40047,
+	375196,
+	897258,
+	1599108,
+	2433074,
+	3308273,
+	4097062,
+	4651618,
+	4829700,
+	4525669,
+	3700263,
+	2402258,
+	776038,
+	-950161,
+	-2496541,
+	-3579851,
+	-3970442,
+	-3547641,
+	-2337956,
+	-529617,
+	1547925,
+	3476297,
+	4827277,
+	5253398,
+	4572039,
+	2823110,
+	284249,
+	-2564887,
+	-5127174,
+	-6808166,
+	-7148614,
+	-5940791,
+	-3300873,
+	324045,
+	4222816,
+	7553233,
+	9518313,
+	9550081,
+	7459490,
+	3515883,
+	-1570147,
+	-6764980,
+	-10915019,
+	-12995804,
+	-12355318,
+	-8895306,
+	-3143626,
+	3808819,
+	10504528,
+	15416643,
+	17288185,
+	15439779,
+	9973227,
+	1815303,
+	-7421871,
+	-15747713,
+	-21211963,
+	-22349384,
+	-18551421,
+	-10274491,
+	976318,
+	12902423,
+	22867792,
+	28468157,
+	28093650,
+	21356476,
+	9275878,
+	-5840836,
+	-20818261,
+	-32262581,
+	-37311768,
+	-34324420,
+	-23346677,
+	-6234152,
+	13625405,
+	31957173,
+	44495096,
+	47945809,
+	40808741,
+	23856504,
+	140921,
+	-25513494,
+	-47455167,
+	-60412143,
+	-60710132,
+	-47229950,
+	-21869611,
+	10631696,
+	43519737,
+	69370312,
+	81696614,
+	76484113,
+	53307373,
+	15747228,
+	-29042608,
+	-71597234,
+	-102026296,
+	-112167649,
+	-97565632,
+	-58831316,
+	-2036750,
+	62029440,
+	119693403,
+	157031723,
+	162840122,
+	131357475,
+	64171528,
+	-29147598,
+	-131921532,
+	-222701994,
+	-278742412,
+	-280032642,
+	-213184166,
+	-74440208,
+	128790505,
+	378234661,
+	646928572,
+	902966510,
+	1114231037,
+	1253321369,
+	1301843153,
+	1253321369,
+	1114231037,
+	902966510,
+	646928572,
+	378234661,
+	128790505,
+	-74440208,
+	-213184166,
+	-280032642,
+	-278742412,
+	-222701994,
+	-131921532,
+	-29147598,
+	64171528,
+	131357475,
+	162840122,
+	157031723,
+	119693403,
+	62029440,
+	-2036750,
+	-58831316,
+	-97565632,
+	-112167649,
+	-102026296,
+	-71597234,
+	-29042608,
+	15747228,
+	53307373,
+	76484113,
+	81696614,
+	69370312,
+	43519737,
+	10631696,
+	-21869611,
+	-47229950,
+	-60710132,
+	-60412143,
+	-47455167,
+	-25513494,
+	140921,
+	23856504,
+	40808741,
+	47945809,
+	44495096,
+	31957173,
+	13625405,
+	-6234152,
+	-23346677,
+	-34324420,
+	-37311768,
+	-32262581,
+	-20818261,
+	-5840836,
+	9275878,
+	21356476,
+	28093650,
+	28468157,
+	22867792,
+	12902423,
+	976318,
+	-10274491,
+	-18551421,
+	-22349384,
+	-21211963,
+	-15747713,
+	-7421871,
+	1815303,
+	9973227,
+	15439779,
+	17288185,
+	15416643,
+	10504528,
+	3808819,
+	-3143626,
+	-8895306,
+	-12355318,
+	-12995804,
+	-10915019,
+	-6764980,
+	-1570147,
+	3515883,
+	7459490,
+	9550081,
+	9518313,
+	7553233,
+	4222816,
+	324045,
+	-3300873,
+	-5940791,
+	-7148614,
+	-6808166,
+	-5127174,
+	-2564887,
+	284249,
+	2823110,
+	4572039,
+	5253398,
+	4827277,
+	3476297,
+	1547925,
+	-529617,
+	-2337956,
+	-3547641,
+	-3970442,
+	-3579851,
+	-2496541,
+	-950161,
+	776038,
+	2402258,
+	3700263,
+	4525669,
+	4829700,
+	4651618,
+	4097062,
+	3308273,
+	2433074,
+	1599108,
+	897258,
+	375196,
+	40047,
+	-132077,
+	-183049,
+	-159762,
+	-145670
+
+};
+
+struct pdm_decim pdm_decim_int32_06_4156_5100_010_095 = {
+	6, 249, 2, 4156, 5100, 10, 95, fir_int32_06_4156_5100_010_095
+};
diff --git a/drivers/audio/decimation/pdm_decim_int32_08_4156_5380_010_090.c b/drivers/audio/decimation/pdm_decim_int32_08_4156_5380_010_090.c
new file mode 100644
index 00000000000..e1619fb8389
--- /dev/null
+++ b/drivers/audio/decimation/pdm_decim_int32_08_4156_5380_010_090.c
@@ -0,0 +1,268 @@
+/*
+ * Copyright (c) 2018, Intel Corporation
+ * All rights reserved.
+ *
+ * Author:	Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
+ *		Sathish Kuttan <sathish.k.kuttan@intel.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr.h>
+
+#include "pdm_decim_fir.h"
+
+static const s32_t fir_int32_08_4156_5380_010_090[247] = {
+	-337052,
+	-90075,
+	37780,
+	310298,
+	762602,
+	1418014,
+	2279975,
+	3324413,
+	4495298,
+	5703536,
+	6831280,
+	7740936,
+	8289504,
+	8346168,
+	7812523,
+	6641741,
+	4854841,
+	2549644,
+	-98570,
+	-2847418,
+	-5407472,
+	-7472951,
+	-8758755,
+	-9040926,
+	-8192669,
+	-6213693,
+	-3246278,
+	424677,
+	4395972,
+	8180309,
+	11265189,
+	13176475,
+	13545386,
+	12170147,
+	9059463,
+	4454447,
+	-1180491,
+	-7196755,
+	-12830960,
+	-17296055,
+	-19885729,
+	-20077500,
+	-17621714,
+	-12601266,
+	-5452197,
+	3062539,
+	11925735,
+	19980775,
+	26075722,
+	29220338,
+	28734576,
+	24368837,
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+	5519930,
+	-6982346,
+	-19587960,
+	-30609997,
+	-38433685,
+	-41741838,
+	-39718804,
+	-32202058,
+	-19758650,
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+	31565234,
+	46060011,
+	55497992,
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+	53292128,
+	40817642,
+	21874421,
+	-1487369,
+	-26460171,
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+	-68227825,
+	-78875217,
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+	-69816864,
+	-49730377,
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+	58408793,
+	16001822,
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+	-121085165,
+	-149268412,
+	-159601418,
+	-149086287,
+	-117235239,
+	-66355092,
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+	69965597,
+	139055884,
+	196228005,
+	232526458,
+	240790250,
+	216740138,
+	159811182,
+	73611998,
+	-34070591,
+	-151754583,
+	-265210746,
+	-358796902,
+	-417052464,
+	-426388521,
+	-376691518,
+	-262659116,
+	-84707915,
+	150664267,
+	431125422,
+	739363099,
+	1054476937,
+	1353781691,
+	1614844650,
+	1817552687,
+	1945997296,
+	1989982406,
+	1945997296,
+	1817552687,
+	1614844650,
+	1353781691,
+	1054476937,
+	739363099,
+	431125422,
+	150664267,
+	-84707915,
+	-262659116,
+	-376691518,
+	-426388521,
+	-417052464,
+	-358796902,
+	-265210746,
+	-151754583,
+	-34070591,
+	73611998,
+	159811182,
+	216740138,
+	240790250,
+	232526458,
+	196228005,
+	139055884,
+	69965597,
+	-1494553,
+	-66355092,
+	-117235239,
+	-149086287,
+	-159601418,
+	-149268412,
+	-121085165,
+	-79996329,
+	-32138446,
+	16001822,
+	58408793,
+	90240198,
+	108334402,
+	111473843,
+	100390923,
+	77532435,
+	46630130,
+	12143051,
+	-21350328,
+	-49730377,
+	-69816864,
+	-79697543,
+	-78875217,
+	-68227825,
+	-49799428,
+	-26460171,
+	-1487369,
+	21874421,
+	40817642,
+	53292128,
+	58207057,
+	55497992,
+	46060011,
+	31565234,
+	14195787,
+	-3667506,
+	-19758650,
+	-32202058,
+	-39718804,
+	-41741838,
+	-38433685,
+	-30609997,
+	-19587960,
+	-6982346,
+	5519930,
+	16375791,
+	24368837,
+	28734576,
+	29220338,
+	26075722,
+	19980775,
+	11925735,
+	3062539,
+	-5452197,
+	-12601266,
+	-17621714,
+	-20077500,
+	-19885729,
+	-17296055,
+	-12830960,
+	-7196755,
+	-1180491,
+	4454447,
+	9059463,
+	12170147,
+	13545386,
+	13176475,
+	11265189,
+	8180309,
+	4395972,
+	424677,
+	-3246278,
+	-6213693,
+	-8192669,
+	-9040926,
+	-8758755,
+	-7472951,
+	-5407472,
+	-2847418,
+	-98570,
+	2549644,
+	4854841,
+	6641741,
+	7812523,
+	8346168,
+	8289504,
+	7740936,
+	6831280,
+	5703536,
+	4495298,
+	3324413,
+	2279975,
+	1418014,
+	762602,
+	310298,
+	37780,
+	-90075,
+	-337052
+
+};
+
+struct pdm_decim pdm_decim_int32_08_4156_5380_010_090 = {
+	8, 247, 3, 4156, 5380, 10, 90, fir_int32_08_4156_5380_010_090
+};
diff --git a/drivers/audio/decimation/pdm_decim_table.c b/drivers/audio/decimation/pdm_decim_table.c
new file mode 100644
index 00000000000..9771ebff112
--- /dev/null
+++ b/drivers/audio/decimation/pdm_decim_table.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2018, Intel Corporation
+ * All rights reserved.
+ *
+ * Author:	Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
+ *		Sathish Kuttan <sathish.k.kuttan@intel.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* PDM decimation FIR filters */
+
+#include <zephyr.h>
+
+#include "pdm_decim_fir.h"
+
+extern struct pdm_decim pdm_decim_int32_02_4375_5100_010_095;
+extern struct pdm_decim pdm_decim_int32_02_4288_5100_010_095;
+extern struct pdm_decim pdm_decim_int32_03_4375_5100_010_095;
+extern struct pdm_decim pdm_decim_int32_03_3850_5100_010_095;
+extern struct pdm_decim pdm_decim_int32_04_4375_5100_010_095;
+extern struct pdm_decim pdm_decim_int32_05_4331_5100_010_095;
+extern struct pdm_decim pdm_decim_int32_06_4156_5100_010_095;
+extern struct pdm_decim pdm_decim_int32_08_4156_5380_010_090;
+
+/* Note: Higher spec filter must be before lower spec filter
+ * if there are multiple filters for a decimation factor. The naming
+ * scheme of coefficients set is:
+ * <type>_<decim factor>_<rel passband>_<rel stopband>_<ripple>_<attenuation>
+ */
+static struct pdm_decim *fir_list[DMIC_FIR_LIST_LENGTH] = {
+	&pdm_decim_int32_02_4375_5100_010_095,
+	&pdm_decim_int32_02_4288_5100_010_095,
+	&pdm_decim_int32_03_4375_5100_010_095,
+	&pdm_decim_int32_03_3850_5100_010_095,
+	&pdm_decim_int32_04_4375_5100_010_095,
+	&pdm_decim_int32_05_4331_5100_010_095,
+	&pdm_decim_int32_06_4156_5100_010_095,
+	&pdm_decim_int32_08_4156_5380_010_090,
+};
+
+struct pdm_decim **pdm_decim_get_fir_list(void)
+{
+	return fir_list;
+}
diff --git a/drivers/audio/intel_dmic.c b/drivers/audio/intel_dmic.c
new file mode 100644
index 00000000000..16a37a51684
--- /dev/null
+++ b/drivers/audio/intel_dmic.c
@@ -0,0 +1,1440 @@
+/*
+ * Copyright (c) 2018, Intel Corporation
+ * All rights reserved.
+ *
+ * Author:	Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
+ *		Liam Girdwood <liam.r.girdwood@linux.intel.com>
+ *		Keyon Jie <yang.jie@linux.intel.com>
+ *		Sathish Kuttan <sathish.k.kuttan@intel.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <errno.h>
+#include <zephyr.h>
+#include <device.h>
+#include <soc.h>
+#include <dma.h>
+
+#include <audio/dmic.h>
+#include "intel_dmic.h"
+#include "decimation/pdm_decim_fir.h"
+
+#define LOG_LEVEL CONFIG_AUDIO_DMIC_LOG_LEVEL
+#include <logging/log.h>
+LOG_MODULE_REGISTER(audio_dmic)
+
+/*
+ * Maximum number of PDM controller instances supported by this driver
+ * configuration data types are selected based on this max.
+ * For example, u32_t is selected when a config parameter is 4bits wide
+ * and 8 instances fit within a 32 bit type
+ */
+#define MAX_PDM_CONTROLLERS_SUPPORTED	8
+/* Actual number of hardware controllers */
+#define DMIC_HW_CONTROLLERS		4
+
+#define DMIC_MAX_MODES 50
+
+/* HW FIR pipeline needs 5 additional cycles per channel for internal
+ * operations. This is used in MAX filter length check.
+ */
+#define DMIC_FIR_PIPELINE_OVERHEAD 5
+
+struct decim_modes {
+	s16_t clkdiv[DMIC_MAX_MODES];
+	s16_t mcic[DMIC_MAX_MODES];
+	s16_t mfir[DMIC_MAX_MODES];
+	int num_of_modes;
+};
+
+struct matched_modes {
+	s16_t clkdiv[DMIC_MAX_MODES];
+	s16_t mcic[DMIC_MAX_MODES];
+	s16_t mfir_a[DMIC_MAX_MODES];
+	s16_t mfir_b[DMIC_MAX_MODES];
+	int num_of_modes;
+};
+
+struct dmic_configuration {
+	struct pdm_decim *fir_a;
+	struct pdm_decim *fir_b;
+	int clkdiv;
+	int mcic;
+	int mfir_a;
+	int mfir_b;
+	int cic_shift;
+	int fir_a_shift;
+	int fir_b_shift;
+	int fir_a_length;
+	int fir_b_length;
+	s32_t fir_a_scale;
+	s32_t fir_b_scale;
+};
+
+/* Minimum OSR is always applied for 48 kHz and less sample rates */
+#define DMIC_MIN_OSR  50
+
+/* These are used as guideline for configuring > 48 kHz sample rates. The
+ * minimum OSR can be relaxed down to 40 (use 3.84 MHz clock for 96 kHz).
+ */
+#define DMIC_HIGH_RATE_MIN_FS	64000
+#define DMIC_HIGH_RATE_OSR_MIN	40
+
+/* Used for scaling FIR coeffcients for HW */
+#define DMIC_HW_FIR_COEF_MAX ((1 << (DMIC_HW_BITS_FIR_COEF - 1)) - 1)
+#define DMIC_HW_FIR_COEF_Q (DMIC_HW_BITS_FIR_COEF - 1)
+
+/* Internal precision in gains computation, e.g. Q4.28 in s32_t */
+#define DMIC_FIR_SCALE_Q 28
+
+/* Fractional multiplication with shift and round
+ * Note that the parameters px and py must be cast to (s64_t) if other type.
+ */
+#define Q_MULTSR_32X32(px, py, qx, qy, qp) \
+	((((px) * (py) >> ((qx)+(qy)-(qp)-1)) + 1) >> 1)
+
+/* Saturation */
+#define SATP_INT32(x) (((x) > INT32_MAX) ? INT32_MAX : (x))
+#define SATM_INT32(x) (((x) < INT32_MIN) ? INT32_MIN : (x))
+
+/* Macros to set bit(s) */
+#define SET_BIT(b, x)		(((x) & 1) << (b))
+#define SET_BITS(b_hi, b_lo, x)	\
+	(((x) & ((1 << ((b_hi) - (b_lo) + 1)) - 1)) << (b_lo))
+
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+
+/* queue size to hold buffers in process */
+#define DMIC_BUF_Q_LEN		2
+
+#define DMIC_REG_RD(reg)	(*((volatile u32_t *)(PDM_BASE + (reg))))
+#define DMIC_REG_WR(reg, val)	\
+	(*((volatile u32_t *)(PDM_BASE + (reg))) = (val))
+#define DMIC_REG_UPD(reg, mask, val)		\
+	DMIC_REG_WR((reg), (DMIC_REG_RD((reg)) & ~(mask)) | ((val) & (mask)))
+
+#define DCACHE_INVALIDATE(addr, size)		\
+	xthal_dcache_region_invalidate(addr, size)
+
+struct _stream_data {
+	struct k_msgq in_queue;
+	struct k_msgq out_queue;
+	void *in_msgs[DMIC_BUF_Q_LEN];
+	void *out_msgs[DMIC_BUF_Q_LEN];
+	struct k_mem_slab *mem_slab;
+	size_t block_size;
+};
+
+/* DMIC private data */
+static struct _dmic_pdata {
+	enum dmic_state state;
+	u16_t fifo_a;
+	u16_t fifo_b;
+	u16_t mic_en_mask;
+	u8_t num_streams;
+	u8_t reserved;
+	struct _stream_data streams[DMIC_MAX_STREAMS];
+	struct device *dma_dev;
+} dmic_private;
+
+static inline void dmic_parse_channel_map(u32_t channel_map_lo,
+		u32_t channel_map_hi, u8_t channel, u8_t *pdm, enum pdm_lr *lr);
+static inline u8_t dmic_parse_clk_skew_map(u32_t skew_map, u8_t pdm);
+static void dmic_stop(void);
+
+/* This function searches from vec[] (of length vec_length) integer values
+ * of n. The indexes to equal values is returned in idx[]. The function
+ * returns the number of found matches. The max_results should be set to
+ * 0 (or negative) or vec_length get all the matches. The max_result can be set
+ * to 1 to receive only the first match in ascending order. It avoids need
+ * for an array for idx.
+ */
+int find_equal_int16(s16_t idx[], s16_t vec[], int n, int vec_length,
+	int max_results)
+{
+	int nresults = 0;
+	int i;
+
+	for (i = 0; i < vec_length; i++) {
+		if (vec[i] == n) {
+			idx[nresults++] = i;
+			if (nresults == max_results)
+				break;
+		}
+	}
+
+	return nresults;
+}
+
+/* Return the smallest value found in the vector */
+s16_t find_min_int16(s16_t vec[], int vec_length)
+{
+	int i;
+	int min = vec[0];
+
+	for (i = 1; i < vec_length; i++)
+		min = (vec[i] < min) ? vec[i] : min;
+
+	return min;
+}
+
+/* Return the largest absolute value found in the vector. Note that
+ * smallest negative value need to be saturated to preset as s32_t.
+ */
+s32_t find_max_abs_int32(s32_t vec[], int vec_length)
+{
+	int i;
+	s64_t amax = (vec[0] > 0) ? vec[0] : -vec[0];
+
+	for (i = 1; i < vec_length; i++) {
+		amax = (vec[i] > amax) ? vec[i] : amax;
+		amax = (-vec[i] > amax) ? -vec[i] : amax;
+	}
+
+	return SATP_INT32(amax); /* Amax is always a positive value */
+}
+
+/* Count the left shift amount to normalize a 32 bit signed integer value
+ * without causing overflow. Input value 0 will result to 31.
+ */
+int norm_int32(s32_t val)
+{
+	if (val == 0) {
+		return 31;
+	}
+
+	if (val < 0) {
+		val = -val;
+	}
+
+	return __builtin_clz(val) - 1;
+}
+
+/* This function returns a raw list of potential microphone clock and decimation
+ * modes for achieving requested sample rates. The search is constrained by
+ * decimation HW capabililies and setup parameters. The parameters such as
+ * microphone clock min/max and duty cycle requirements need be checked from
+ * used microphone component datasheet.
+ */
+static void find_modes(struct decim_modes *modes,
+		struct dmic_cfg *config, u32_t fs)
+{
+	int clkdiv_min;
+	int clkdiv_max;
+	int clkdiv;
+	int c1;
+	int du_min;
+	int du_max;
+	int pdmclk;
+	int osr;
+	int mfir;
+	int mcic;
+	int ioclk_test;
+	int osr_min = DMIC_MIN_OSR;
+	int i = 0;
+
+	/* Defaults, empty result */
+	modes->num_of_modes = 0;
+
+	/* The FIFO is not requested if sample rate is set to zero. Just
+	 * return in such case with num_of_modes as zero.
+	 */
+	if (fs == 0) {
+		return;
+	}
+
+	/* Override DMIC_MIN_OSR for very high sample rates, use as minimum
+	 * the nominal clock for the high rates.
+	 */
+	if (fs >= DMIC_HIGH_RATE_MIN_FS) {
+		osr_min = DMIC_HIGH_RATE_OSR_MIN;
+	}
+
+	/* Check for sane pdm clock, min 100 kHz, max ioclk/2 */
+	if ((config->io.max_pdm_clk_freq < DMIC_HW_PDM_CLK_MIN) ||
+		(config->io.max_pdm_clk_freq > (DMIC_HW_IOCLK / 2))) {
+		LOG_ERR("max_pdm_clk_freq %u invalid",
+				config->io.max_pdm_clk_freq);
+		return;
+	}
+
+	if ((config->io.min_pdm_clk_freq < DMIC_HW_PDM_CLK_MIN) ||
+		(config->io.min_pdm_clk_freq > config->io.max_pdm_clk_freq)) {
+		LOG_ERR("min_pdm_clk_freq %u invalid",
+				config->io.min_pdm_clk_freq);
+		return;
+	}
+
+	/* Check for sane duty cycle */
+	if (config->io.min_pdm_clk_dc > config->io.max_pdm_clk_dc) {
+		LOG_ERR("min_pdm_clk_dc %u max_pdm_clk_dc %u invalid",
+				config->io.min_pdm_clk_dc,
+				config->io.max_pdm_clk_dc);
+		return;
+	}
+
+	if ((config->io.min_pdm_clk_dc < DMIC_HW_DUTY_MIN) ||
+		(config->io.min_pdm_clk_dc > DMIC_HW_DUTY_MAX)) {
+		LOG_ERR("min_pdm_clk_dc %u invalid",
+				config->io.min_pdm_clk_dc);
+		return;
+	}
+
+	if ((config->io.max_pdm_clk_dc < DMIC_HW_DUTY_MIN) ||
+		(config->io.max_pdm_clk_dc > DMIC_HW_DUTY_MAX)) {
+		LOG_ERR("max_pdm_clk_dc %u invalid", config->io.max_pdm_clk_dc);
+		return;
+	}
+
+	/* Min and max clock dividers */
+	clkdiv_min = (DMIC_HW_IOCLK + config->io.max_pdm_clk_freq - 1) /
+		config->io.max_pdm_clk_freq;
+	clkdiv_min = (clkdiv_min > DMIC_HW_CIC_DECIM_MIN) ?
+		clkdiv_min : DMIC_HW_CIC_DECIM_MIN;
+	clkdiv_max = DMIC_HW_IOCLK / config->io.min_pdm_clk_freq;
+
+	/* Loop possible clock dividers and check based on resulting
+	 * oversampling ratio that CIC and FIR decimation ratios are
+	 * feasible. The ratios need to be integers. Also the mic clock
+	 * duty cycle need to be within limits.
+	 */
+	for (clkdiv = clkdiv_min; clkdiv <= clkdiv_max; clkdiv++) {
+		/* Calculate duty cycle for this clock divider. Note that
+		 * odd dividers cause non-50% duty cycle.
+		 */
+		c1 = clkdiv >> 1;
+		du_min = 100 * c1 / clkdiv;
+		du_max = 100 - du_min;
+
+		/* Calculate PDM clock rate and oversampling ratio. */
+		pdmclk = DMIC_HW_IOCLK / clkdiv;
+		osr = pdmclk / fs;
+
+		/* Check that OSR constraints is met and clock duty cycle does
+		 * not exceed microphone specification. If exceed proceed to
+		 * next clkdiv.
+		 */
+		if ((osr < osr_min) || (du_min < config->io.min_pdm_clk_dc) ||
+			(du_max > config->io.max_pdm_clk_dc)) {
+			continue;
+		}
+
+		/* Loop FIR decimation factors candidates. If the
+		 * integer divided decimation factors and clock dividers
+		 * as multiplied with sample rate match the IO clock
+		 * rate the division was exact and such decimation mode
+		 * is possible. Then check that CIC decimation constraints
+		 * are met. The passed decimation modes are added to array.
+		 */
+		for (mfir = DMIC_HW_FIR_DECIM_MIN;
+			mfir <= DMIC_HW_FIR_DECIM_MAX; mfir++) {
+			mcic = osr / mfir;
+			ioclk_test = fs * mfir * mcic * clkdiv;
+
+			if (ioclk_test == DMIC_HW_IOCLK &&
+				mcic >= DMIC_HW_CIC_DECIM_MIN &&
+				mcic <= DMIC_HW_CIC_DECIM_MAX &&
+				i < DMIC_MAX_MODES) {
+				modes->clkdiv[i] = clkdiv;
+				modes->mcic[i] = mcic;
+				modes->mfir[i] = mfir;
+				i++;
+				modes->num_of_modes = i;
+			}
+		}
+	}
+}
+
+/* The previous raw modes list contains sane configuration possibilities. When
+ * there is request for both FIFOs A and B operation this function returns
+ * list of compatible settings.
+ */
+static void match_modes(struct matched_modes *c, struct decim_modes *a,
+		struct decim_modes *b)
+{
+	s16_t idx[DMIC_MAX_MODES];
+	int idx_length;
+	int i;
+	int n;
+	int m;
+
+	/* Check if previous search got results. */
+	c->num_of_modes = 0;
+	if (a->num_of_modes == 0 && b->num_of_modes == 0) {
+		/* Nothing to do */
+		return;
+	}
+
+	/* Check for request only for FIFO A or B. In such case pass list for
+	 * A or B as such.
+	 */
+	if (b->num_of_modes == 0) {
+		c->num_of_modes = a->num_of_modes;
+		for (i = 0; i < a->num_of_modes; i++) {
+			c->clkdiv[i] = a->clkdiv[i];
+			c->mcic[i] = a->mcic[i];
+			c->mfir_a[i] = a->mfir[i];
+			c->mfir_b[i] = 0; /* Mark FIR B as non-used */
+		}
+		return;
+	}
+
+	if (a->num_of_modes == 0) {
+		c->num_of_modes = b->num_of_modes;
+		for (i = 0; i < b->num_of_modes; i++) {
+			c->clkdiv[i] = b->clkdiv[i];
+			c->mcic[i] = b->mcic[i];
+			c->mfir_b[i] = b->mfir[i];
+			c->mfir_a[i] = 0; /* Mark FIR A as non-used */
+		}
+		return;
+	}
+
+	/* Merge a list of compatible modes */
+	i = 0;
+	for (n = 0; n < a->num_of_modes; n++) {
+		/* Find all indices of values a->clkdiv[n] in b->clkdiv[] */
+		idx_length = find_equal_int16(idx, b->clkdiv, a->clkdiv[n],
+			b->num_of_modes, 0);
+		for (m = 0; m < idx_length; m++) {
+			if (b->mcic[idx[m]] == a->mcic[n]) {
+				c->clkdiv[i] = a->clkdiv[n];
+				c->mcic[i] = a->mcic[n];
+				c->mfir_a[i] = a->mfir[n];
+				c->mfir_b[i] = b->mfir[idx[m]];
+				i++;
+			}
+		}
+		c->num_of_modes = i;
+	}
+}
+
+/* Finds a suitable FIR decimation filter from the included set */
+static struct pdm_decim *get_fir(struct dmic_configuration *cfg, int mfir)
+{
+	int i;
+	int fs;
+	int cic_fs;
+	int fir_max_length;
+	struct pdm_decim *fir = NULL;
+	struct pdm_decim **fir_list;
+
+	if (mfir <= 0)
+		return fir;
+
+	cic_fs = DMIC_HW_IOCLK / cfg->clkdiv / cfg->mcic;
+	fs = cic_fs / mfir;
+	/* FIR max. length depends on available cycles and coef RAM
+	 * length. Exceeding this length sets HW overrun status and
+	 * overwrite of other register.
+	 */
+	fir_max_length = (DMIC_HW_IOCLK / fs / 2) - DMIC_FIR_PIPELINE_OVERHEAD;
+	fir_max_length = MIN(fir_max_length, DMIC_HW_FIR_LENGTH_MAX);
+
+	fir_list = pdm_decim_get_fir_list();
+
+	for (i = 0; i < DMIC_FIR_LIST_LENGTH; i++) {
+		if (fir_list[i]->decim_factor == mfir &&
+			fir_list[i]->length <= fir_max_length) {
+			/* Store pointer, break from loop to avoid a
+			 * Possible other mode with lower FIR length.
+			 */
+			fir = fir_list[i];
+			break;
+		}
+	}
+
+	return fir;
+}
+
+/* Calculate scale and shift to use for FIR coefficients. Scale is applied
+ * before write to HW coef RAM. Shift will be programmed to HW register.
+ */
+static int fir_coef_scale(s32_t *fir_scale, int *fir_shift, int add_shift,
+	const s32_t coef[], int coef_length, s32_t gain)
+{
+	s32_t amax;
+	s32_t new_amax;
+	s32_t fir_gain;
+	int shift;
+
+	/* Multiply gain passed from CIC with output full scale. */
+	fir_gain = Q_MULTSR_32X32((s64_t)gain, DMIC_HW_SENS_Q28,
+		DMIC_FIR_SCALE_Q, 28, DMIC_FIR_SCALE_Q);
+
+	/* Find the largest FIR coefficient value. */
+	amax = find_max_abs_int32((s32_t *)coef, coef_length);
+
+	/* Scale max. tap value with FIR gain. */
+	new_amax = Q_MULTSR_32X32((s64_t)amax, fir_gain, 31,
+		DMIC_FIR_SCALE_Q, DMIC_FIR_SCALE_Q);
+	if (new_amax <= 0)
+		return -EINVAL;
+
+	/* Get left shifts count to normalize the fractional value as 32 bit.
+	 * We need right shifts count for scaling so need to invert. The
+	 * difference of Q31 vs. used Q format is added to get the correct
+	 * normalization right shift value.
+	 */
+	shift = 31 - DMIC_FIR_SCALE_Q - norm_int32(new_amax);
+
+	/* Add to shift for coef raw Q31 format shift and store to
+	 * configuration. Ensure range (fail should not happen with OK
+	 * coefficient set).
+	 */
+	*fir_shift = -shift + add_shift;
+	if (*fir_shift < DMIC_HW_FIR_SHIFT_MIN ||
+		*fir_shift > DMIC_HW_FIR_SHIFT_MAX)
+		return -EINVAL;
+
+	/* Compensate shift into FIR coef scaler and store as Q4.20. */
+	if (shift < 0)
+		*fir_scale = (fir_gain << -shift);
+	else
+		*fir_scale = (fir_gain >> shift);
+
+	return 0;
+}
+
+/* This function selects with a simple criteria one mode to set up the
+ * decimator. For the settings chosen for FIFOs A and B output a lookup
+ * is done for FIR coefficients from the included coefficients tables.
+ * For some decimation factors there may be several length coefficient sets.
+ * It is due to possible restruction of decimation engine cycles per given
+ * sample rate. If the coefficients length is exceeded the lookup continues.
+ * Therefore the list of coefficient set must present the filters for a
+ * decimation factor in decreasing length order.
+ *
+ * Note: If there is no filter available an error is returned. The parameters
+ * should be reviewed for such case. If still a filter is missing it should be
+ * added into the included set. FIR decimation with a high factor usually
+ * needs compromizes into specifications and is not desirable.
+ */
+static int select_mode(struct dmic_configuration *cfg,
+	struct matched_modes *modes)
+{
+	s32_t g_cic;
+	s32_t fir_in_max;
+	s32_t cic_out_max;
+	s32_t gain_to_fir;
+	s16_t idx[DMIC_MAX_MODES];
+	s16_t *mfir;
+	int n = 1;
+	int mmin;
+	int count;
+	int mcic;
+	int bits_cic;
+	int ret;
+
+	/* If there are more than one possibilities select a mode with lowest
+	 * FIR decimation factor. If there are several select mode with highest
+	 * ioclk divider to minimize microphone power consumption. The highest
+	 * clock divisors are in the end of list so select the last of list.
+	 * The minimum OSR criteria used in previous ensures that quality in
+	 * the candidates should be sufficient.
+	 */
+	if (modes->num_of_modes == 0) {
+		LOG_ERR("num_of_modes is 0");
+		return -EINVAL;
+	}
+
+	/* Valid modes presence is indicated with non-zero decimation
+	 * factor in 1st element. If FIR A is not used get decimation factors
+	 * from FIR B instead.
+	 */
+	if (modes->mfir_a[0] > 0)
+		mfir = modes->mfir_a;
+	else
+		mfir = modes->mfir_b;
+
+	mmin = find_min_int16(mfir, modes->num_of_modes);
+	count = find_equal_int16(idx, mfir, mmin, modes->num_of_modes, 0);
+	n = idx[count - 1];
+
+	/* Get microphone clock and decimation parameters for used mode from
+	 * the list.
+	 */
+	cfg->clkdiv = modes->clkdiv[n];
+	cfg->mfir_a = modes->mfir_a[n];
+	cfg->mfir_b = modes->mfir_b[n];
+	cfg->mcic = modes->mcic[n];
+	cfg->fir_a = NULL;
+	cfg->fir_b = NULL;
+
+	/* Find raw FIR coefficients to match the decimation factors of FIR
+	 * A and B.
+	 */
+	if (cfg->mfir_a > 0) {
+		cfg->fir_a = get_fir(cfg, cfg->mfir_a);
+		if (!cfg->fir_a) {
+			LOG_ERR("FIR filter not found for mfir_a %d",
+					cfg->mfir_a);
+			return -EINVAL;
+		}
+	}
+
+	if (cfg->mfir_b > 0) {
+		cfg->fir_b = get_fir(cfg, cfg->mfir_b);
+		if (!cfg->fir_b) {
+			LOG_ERR("FIR filter not found for mfir_b %d",
+					cfg->mfir_b);
+			return -EINVAL;
+		}
+	}
+
+	/* Calculate CIC shift from the decimation factor specific gain. The
+	 * gain of HW decimator equals decimation factor to power of 5.
+	 */
+	mcic = cfg->mcic;
+	g_cic = mcic * mcic * mcic * mcic * mcic;
+	if (g_cic < 0) {
+		/* Erroneous decimation factor and CIC gain */
+		LOG_ERR("Invalid CIC gain %d", g_cic);
+		return -EINVAL;
+	}
+
+	bits_cic = 32 - norm_int32(g_cic);
+	cfg->cic_shift = bits_cic - DMIC_HW_BITS_FIR_INPUT;
+
+	/* Calculate remaining gain to FIR in Q format used for gain
+	 * values.
+	 */
+	fir_in_max = (1 << (DMIC_HW_BITS_FIR_INPUT - 1));
+	if (cfg->cic_shift >= 0)
+		cic_out_max = g_cic >> cfg->cic_shift;
+	else
+		cic_out_max = g_cic << -cfg->cic_shift;
+
+	gain_to_fir = (s32_t)((((s64_t)fir_in_max) << DMIC_FIR_SCALE_Q) /
+		cic_out_max);
+
+	/* Calculate FIR scale and shift */
+	if (cfg->mfir_a > 0) {
+		cfg->fir_a_length = cfg->fir_a->length;
+		ret = fir_coef_scale(&cfg->fir_a_scale, &cfg->fir_a_shift,
+			cfg->fir_a->shift, cfg->fir_a->coef, cfg->fir_a->length,
+			gain_to_fir);
+		if (ret < 0) {
+			/* Invalid coefficient set found, should not happen. */
+			LOG_ERR("Invalid coefficient A");
+			return -EINVAL;
+		}
+	} else {
+		cfg->fir_a_scale = 0;
+		cfg->fir_a_shift = 0;
+		cfg->fir_a_length = 0;
+	}
+
+	if (cfg->mfir_b > 0) {
+		cfg->fir_b_length = cfg->fir_b->length;
+		ret = fir_coef_scale(&cfg->fir_b_scale, &cfg->fir_b_shift,
+			cfg->fir_b->shift, cfg->fir_b->coef, cfg->fir_b->length,
+			gain_to_fir);
+		if (ret < 0) {
+			/* Invalid coefficient set found, should not happen. */
+			LOG_ERR("Invalid coefficient B");
+			return -EINVAL;
+		}
+	} else {
+		cfg->fir_b_scale = 0;
+		cfg->fir_b_shift = 0;
+		cfg->fir_b_length = 0;
+	}
+
+	return 0;
+}
+
+static int source_ipm_helper(struct pdm_chan_cfg *config, u32_t *source_mask,
+		u8_t *controller_mask, u8_t *stereo_mask, u8_t *swap_mask)
+{
+	u8_t pdm_ix;
+	u8_t chan_ix;
+	enum pdm_lr lr;
+	u16_t pdm_lr_mask = 0;
+	int ipm = 0;
+
+	/* clear outputs */
+	*source_mask = 0;
+	*stereo_mask = 0;
+	*swap_mask = 0;
+	*controller_mask = 0;
+
+	/* Loop number of PDM controllers in the configuration. If mic A
+	 * or B is enabled then a pdm controller is marked as active. Also it
+	 * is checked whether the controller should operate as stereo or mono
+	 * left (A) or mono right (B) mode. Mono right mode is setup as channel
+	 * swapped mono left. The function returns also in array source[] the
+	 * indice of enabled pdm controllers to be used for IPM configuration.
+	 */
+	for (chan_ix = 0; chan_ix < config->req_num_chan; chan_ix++) {
+
+		dmic_parse_channel_map(config->req_chan_map_lo,
+				config->req_chan_map_hi,
+				chan_ix, &pdm_ix, &lr);
+
+		if (pdm_ix >= DMIC_HW_CONTROLLERS) {
+			LOG_ERR("Invalid PDM controller %u in channel %u",
+					pdm_ix, chan_ix);
+			continue;
+		}
+
+		if ((*controller_mask & BIT(pdm_ix)) == 0) {
+			*controller_mask |= BIT(pdm_ix);
+			*source_mask |= pdm_ix << (ipm << 2);
+			ipm++;
+		}
+		pdm_lr_mask |= BIT(lr) << (pdm_ix << 1);
+		/*
+		 * if both L and R are requested,
+		 * set the controller to be stereo
+		 */
+		if ((pdm_lr_mask >> (pdm_ix << 1)) &
+				(BIT(PDM_CHAN_LEFT) | BIT(PDM_CHAN_RIGHT))) {
+			*stereo_mask |= BIT(pdm_ix);
+		}
+
+		/*
+		 * if R channel mic was requested first
+		 * set the controller to swap the channels
+		 */
+		if ((pdm_lr_mask & BIT(PDM_CHAN_LEFT + (pdm_ix << 1))) == 0) {
+			*swap_mask |= BIT(pdm_ix);
+		}
+	}
+
+	/* IPM bit field is set to count of active pdm controllers. */
+	LOG_DBG("%u decimators has to be configured", ipm);
+	return ipm;
+}
+
+static int configure_registers(struct device *dev,
+		struct dmic_configuration *hw_cfg, struct dmic_cfg *config)
+{
+	u8_t skew;
+	u8_t swap_mask;
+	u8_t edge_mask;
+	u8_t stereo_mask;
+	u8_t controller_mask;
+	u32_t val;
+	s32_t ci;
+	u32_t cu;
+	u32_t coeff_ix;
+	int ipm;
+	int of0;
+	int of1;
+	int fir_decim;
+	int fir_length;
+	int length;
+	int dccomp;
+	int cic_start_a;
+	int cic_start_b;
+	int fir_start_a;
+	int fir_start_b;
+	int soft_reset;
+	int i;
+	int j;
+
+	int array_a = 0;
+	int array_b = 0;
+	int cic_mute = 0;
+	int fir_mute = 0;
+
+	/* Normal start sequence */
+	dccomp = 1;
+	soft_reset = 1;
+	cic_start_a = 0;
+	cic_start_b = 0;
+	fir_start_a = 0;
+	fir_start_b = 0;
+
+	u32_t source_mask;
+
+	/* OUTCONTROL0 and OUTCONTROL1 */
+	of0 = (config->streams[0].pcm_width == 32) ? 2 : 0;
+	if (config->channel.req_num_streams > 1) {
+		of1 = (config->streams[1].pcm_width == 32) ? 2 : 0;
+	} else {
+		of1 = 0;
+	}
+
+	ipm = source_ipm_helper(&config->channel, &source_mask,
+			&controller_mask, &stereo_mask, &swap_mask);
+	val = OUTCONTROL0_TIE(0) |
+		OUTCONTROL0_SIP(0) |
+		OUTCONTROL0_FINIT(1) |
+		OUTCONTROL0_FCI(0) |
+		OUTCONTROL0_BFTH(3) |
+		OUTCONTROL0_OF(of0) |
+		OUTCONTROL0_NUMBER_OF_DECIMATORS(ipm) |
+		OUTCONTROL0_IPM_SOURCE_1(source_mask) |
+		OUTCONTROL0_IPM_SOURCE_2(source_mask >> 4) |
+		OUTCONTROL0_IPM_SOURCE_3(source_mask >> 8) |
+		OUTCONTROL0_IPM_SOURCE_4(source_mask >> 12) |
+		OUTCONTROL0_TH(3);
+	DMIC_REG_WR(OUTCONTROL0, val);
+	LOG_DBG("WR: OUTCONTROL0: 0x%08X", val);
+
+	val = OUTCONTROL1_TIE(0) |
+		OUTCONTROL1_SIP(0) |
+		OUTCONTROL1_FINIT(1) |
+		OUTCONTROL1_FCI(0) |
+		OUTCONTROL1_BFTH(3) |
+		OUTCONTROL1_OF(of1) |
+		OUTCONTROL1_NUMBER_OF_DECIMATORS(ipm) |
+		OUTCONTROL1_IPM_SOURCE_1(source_mask) |
+		OUTCONTROL1_IPM_SOURCE_2(source_mask >> 4) |
+		OUTCONTROL1_IPM_SOURCE_3(source_mask >> 8) |
+		OUTCONTROL1_IPM_SOURCE_4(source_mask >> 12) |
+		OUTCONTROL1_TH(3);
+	DMIC_REG_WR(OUTCONTROL1, val);
+	LOG_DBG("WR: OUTCONTROL1: 0x%08X", val);
+
+	/* Mark enabled microphones into private data to be later used
+	 * for starting correct parts of the HW.
+	 */
+	for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
+		if ((controller_mask & BIT(i)) == 0) {
+			/* controller is not enabled */
+			continue;
+		}
+
+		if (stereo_mask & BIT(i)) {
+			dmic_private.mic_en_mask |= (BIT(PDM_CHAN_LEFT) |
+				BIT(PDM_CHAN_RIGHT)) << (i << 1);
+		} else {
+			dmic_private.mic_en_mask |=
+				((swap_mask & BIT(i)) == 0) ?
+				BIT(PDM_CHAN_LEFT) << (i << 1) :
+				BIT(PDM_CHAN_RIGHT) << (i << 1);
+		}
+	}
+
+	/*
+	 * Mono right channel mic usage requires swap of PDM channels
+	 * since the mono decimation is done with only left channel
+	 * processing active.
+	 */
+	edge_mask = config->io.pdm_clk_pol ^ swap_mask;
+
+	for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
+		/* CIC */
+		val = CIC_CONTROL_SOFT_RESET(soft_reset) |
+			CIC_CONTROL_CIC_START_B(cic_start_b) |
+			CIC_CONTROL_CIC_START_A(cic_start_a) |
+		CIC_CONTROL_MIC_B_POLARITY(config->io.pdm_data_pol >> i) |
+		CIC_CONTROL_MIC_A_POLARITY(config->io.pdm_data_pol >> i) |
+			CIC_CONTROL_MIC_MUTE(cic_mute) |
+			CIC_CONTROL_STEREO_MODE(stereo_mask >> i);
+		DMIC_REG_WR(CIC_CONTROL(i), val);
+		LOG_DBG("WR: CIC_CONTROL[%u]: 0x%08X", i, val);
+
+		val = CIC_CONFIG_CIC_SHIFT(hw_cfg->cic_shift + 8) |
+			CIC_CONFIG_COMB_COUNT(hw_cfg->mcic - 1);
+		DMIC_REG_WR(CIC_CONFIG(i), val);
+		LOG_DBG("WR: CIC_CONFIG[%u]: 0x%08X", i, val);
+
+		skew = dmic_parse_clk_skew_map(config->io.pdm_clk_skew, i);
+		val = MIC_CONTROL_PDM_CLKDIV(hw_cfg->clkdiv - 2) |
+			MIC_CONTROL_PDM_SKEW(skew) |
+			MIC_CONTROL_CLK_EDGE(edge_mask >> i) |
+			MIC_CONTROL_PDM_EN_B(cic_start_b) |
+			MIC_CONTROL_PDM_EN_A(cic_start_a);
+		DMIC_REG_WR(MIC_CONTROL(i), val);
+		LOG_DBG("WR: MIC_CONTROL[%u]: 0x%08X", i, val);
+
+		/* FIR A */
+		fir_decim = MAX(hw_cfg->mfir_a - 1, 0);
+		fir_length = MAX(hw_cfg->fir_a_length - 1, 0);
+		val = FIR_CONTROL_A_START(fir_start_a) |
+			FIR_CONTROL_A_ARRAY_START_EN(array_a) |
+			FIR_CONTROL_A_DCCOMP(dccomp) |
+			FIR_CONTROL_A_MUTE(fir_mute) |
+			FIR_CONTROL_A_STEREO(stereo_mask >> i);
+		DMIC_REG_WR(FIR_CONTROL_A(i), val);
+		LOG_DBG("WR: FIR_CONTROL_A[%u]: 0x%08X", i, val);
+
+		val = FIR_CONFIG_A_FIR_DECIMATION(fir_decim) |
+			FIR_CONFIG_A_FIR_SHIFT(hw_cfg->fir_a_shift) |
+			FIR_CONFIG_A_FIR_LENGTH(fir_length);
+		DMIC_REG_WR(FIR_CONFIG_A(i), val);
+		LOG_DBG("WR: FIR_CONFIG_A[%u]: 0x%08X", i, val);
+
+		val = DC_OFFSET_LEFT_A_DC_OFFS(DCCOMP_TC0);
+		DMIC_REG_WR(DC_OFFSET_LEFT_A(i), val);
+		LOG_DBG("WR: DC_OFFSET_LEFT_A[%u]: 0x%08X", i, val);
+
+		val = DC_OFFSET_RIGHT_A_DC_OFFS(DCCOMP_TC0);
+		DMIC_REG_WR(DC_OFFSET_RIGHT_A(i), val);
+		LOG_DBG("WR: DC_OFFSET_RIGHT_A[%u]: 0x%08X", i, val);
+
+		val = OUT_GAIN_LEFT_A_GAIN(0);
+		DMIC_REG_WR(OUT_GAIN_LEFT_A(i), val);
+		LOG_DBG("WR: OUT_GAIN_LEFT_A[%u]: 0x%08X", i, val);
+
+		val = OUT_GAIN_RIGHT_A_GAIN(0);
+		DMIC_REG_WR(OUT_GAIN_RIGHT_A(i), val);
+		LOG_DBG("WR: OUT_GAIN_RIGHT_A[%u]: 0x%08X", i, val);
+
+		/* FIR B */
+		fir_decim = MAX(hw_cfg->mfir_b - 1, 0);
+		fir_length = MAX(hw_cfg->fir_b_length - 1, 0);
+		val = FIR_CONTROL_B_START(fir_start_b) |
+			FIR_CONTROL_B_ARRAY_START_EN(array_b) |
+			FIR_CONTROL_B_DCCOMP(dccomp) |
+			FIR_CONTROL_B_MUTE(fir_mute) |
+			FIR_CONTROL_B_STEREO(stereo_mask >> i);
+		DMIC_REG_WR(FIR_CONTROL_B(i), val);
+		LOG_DBG("WR: FIR_CONTROL_B[%u]: 0x%08X", i, val);
+
+		val = FIR_CONFIG_B_FIR_DECIMATION(fir_decim) |
+			FIR_CONFIG_B_FIR_SHIFT(hw_cfg->fir_b_shift) |
+			FIR_CONFIG_B_FIR_LENGTH(fir_length);
+		DMIC_REG_WR(FIR_CONFIG_B(i), val);
+		LOG_DBG("WR: FIR_CONFIG_B[%u]: 0x%08X", i, val);
+
+		val = DC_OFFSET_LEFT_B_DC_OFFS(DCCOMP_TC0);
+		DMIC_REG_WR(DC_OFFSET_LEFT_B(i), val);
+		LOG_DBG("WR: DC_OFFSET_LEFT_B[%u]: 0x%08X", i, val);
+
+		val = DC_OFFSET_RIGHT_B_DC_OFFS(DCCOMP_TC0);
+		DMIC_REG_WR(DC_OFFSET_RIGHT_B(i), val);
+		LOG_DBG("WR: DC_OFFSET_RIGHT_B[%u]: 0x%08X", i, val);
+
+		val = OUT_GAIN_LEFT_B_GAIN(0);
+		DMIC_REG_WR(OUT_GAIN_LEFT_B(i), val);
+		LOG_DBG("WR: OUT_GAIN_LEFT_B[%u]: 0x%08X", i, val);
+
+		val = OUT_GAIN_RIGHT_B_GAIN(0);
+		DMIC_REG_WR(OUT_GAIN_RIGHT_B(i), val);
+		LOG_DBG("WR: OUT_GAIN_RIGHT_B[%u]: 0x%08X", i, val);
+	}
+
+	/* Write coef RAM A with scaled coefficient in reverse order */
+	length = hw_cfg->fir_a_length;
+	for (j = 0; j < length; j++) {
+		ci = (s32_t)Q_MULTSR_32X32((s64_t)hw_cfg->fir_a->coef[j],
+				hw_cfg->fir_a_scale, 31, DMIC_FIR_SCALE_Q,
+				DMIC_HW_FIR_COEF_Q);
+		cu = FIR_COEF_A(ci);
+		coeff_ix = (length - j - 1) << 2;
+		for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
+			DMIC_REG_WR(PDM_COEFF_A(i) + coeff_ix, cu);
+		}
+	}
+
+	/* Write coef RAM B with scaled coefficient in reverse order */
+	length = hw_cfg->fir_b_length;
+	for (j = 0; j < length; j++) {
+		ci = (s32_t)Q_MULTSR_32X32((s64_t)hw_cfg->fir_b->coef[j],
+				hw_cfg->fir_b_scale, 31, DMIC_FIR_SCALE_Q,
+				DMIC_HW_FIR_COEF_Q);
+		cu = FIR_COEF_B(ci);
+		coeff_ix = (length - j - 1) << 2;
+		for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
+			DMIC_REG_WR(PDM_COEFF_B(i) + coeff_ix, cu);
+		}
+	}
+
+	/* Function dmic_start() uses these to start the used FIFOs */
+	dmic_private.fifo_a = (hw_cfg->mfir_a > 0) ? 1 : 0;
+	dmic_private.fifo_b = (hw_cfg->mfir_b > 0) ? 1 : 0;
+
+	return 0;
+}
+
+static void dmic_dma_callback(void *arg, u32_t chan, int err_code)
+{
+	void *buffer;
+	size_t size;
+	int stream;
+	struct _stream_data *stream_data;
+	int ret;
+
+	stream = (chan == DMA_CHANNEL_DMIC_RXA) ? 0 : 1;
+	stream_data = &dmic_private.streams[stream];
+
+	/* retrieve buffer from input queue */
+	ret = k_msgq_get(&stream_data->in_queue, &buffer, K_NO_WAIT);
+
+	if (ret) {
+		LOG_ERR("stream %u in_queue is empty", stream);
+	}
+
+	if (dmic_private.state == DMIC_STATE_ACTIVE) {
+		size = stream_data->block_size;
+		/* put buffer in output queue */
+		ret = k_msgq_put(&stream_data->out_queue, &buffer,
+				K_NO_WAIT);
+		if (ret) {
+			LOG_ERR("stream%u out_queue is full", stream);
+		}
+
+		/* allocate new buffer for next audio frame */
+		ret = k_mem_slab_alloc(stream_data->mem_slab, &buffer,
+				K_NO_WAIT);
+		if (ret) {
+			LOG_ERR("buffer alloc from slab %p err %d",
+					stream_data->mem_slab, ret);
+		} else {
+			/* put buffer in input queue */
+			ret = k_msgq_put(&stream_data->in_queue, &buffer,
+					K_NO_WAIT);
+			if (ret) {
+				LOG_ERR("buffer %p -> in_queue %p err %d",
+						buffer, &stream_data->in_queue,
+						ret);
+			}
+
+			/* reload the DMA */
+			dmic_reload_dma(chan, buffer, stream_data->block_size);
+			dmic_start_dma(chan);
+		}
+	} else {
+		/* stop activity, free buffers */
+		dmic_stop();
+		dmic_stop_dma(chan);
+		k_mem_slab_free(stream_data->mem_slab, &buffer);
+	}
+}
+
+static int dmic_set_config(struct device *dev, struct dmic_cfg *config)
+{
+	struct decim_modes modes_a;
+	struct decim_modes modes_b;
+	struct matched_modes modes_ab;
+	struct dmic_configuration hw_cfg;
+	int ret;
+	int stream;
+
+	LOG_DBG("min_pdm_clk_freq %u max_pdm_clk_freq %u",
+			config->io.min_pdm_clk_freq,
+			config->io.max_pdm_clk_freq);
+	LOG_DBG("min_pdm_clk_dc %u max_pdm_clk_dc %u",
+			config->io.min_pdm_clk_dc,
+			config->io.max_pdm_clk_dc);
+	LOG_DBG("num_chan %u", config->channel.req_num_chan);
+	LOG_DBG("req_num_streams %u", config->channel.req_num_streams);
+
+	if (config->channel.req_num_streams == 0) {
+		LOG_ERR("req_num_streams is 0");
+		return -EINVAL;
+	}
+
+	config->channel.act_num_streams = MIN(config->channel.req_num_streams,
+			DMIC_MAX_STREAMS);
+
+	LOG_DBG("req_num_streams %u act_num_streams %u",
+			config->channel.req_num_streams,
+			config->channel.act_num_streams);
+	dmic_private.num_streams = config->channel.act_num_streams;
+
+	for (stream = 0; stream < dmic_private.num_streams; stream++) {
+		LOG_DBG("stream %u pcm_rate %u pcm_width %u", stream,
+				config->streams[stream].pcm_rate,
+				config->streams[stream].pcm_width);
+
+		if ((config->streams[stream].pcm_width) &&
+				(config->streams[stream].mem_slab == NULL)) {
+			LOG_ERR("Invalid mem_slab for stream %u", stream);
+			return -EINVAL;
+		}
+
+		dmic_private.streams[stream].mem_slab =
+			config->streams[stream].mem_slab;
+		dmic_private.streams[stream].block_size =
+			config->streams[stream].block_size;
+	}
+
+	/* Match and select optimal decimators configuration for FIFOs A and B
+	 * paths. This setup phase is still abstract. Successful completion
+	 * points struct cfg to FIR coefficients and contains the scale value
+	 * to use for FIR coefficient RAM write as well as the CIC and FIR
+	 * shift values.
+	 */
+	find_modes(&modes_a, config, config->streams[0].pcm_rate);
+	if ((modes_a.num_of_modes == 0) && (config->streams[0].pcm_rate > 0)) {
+		LOG_ERR("stream A num_of_modes is 0 and pcm_rate is %u",
+				config->streams[0].pcm_rate);
+		return -EINVAL;
+	}
+
+	if (dmic_private.num_streams > 1) {
+		find_modes(&modes_b, config, config->streams[1].pcm_rate);
+		if ((modes_b.num_of_modes == 0) &&
+				(config->streams[1].pcm_rate > 0)) {
+			LOG_ERR("stream B num_of_modes = 0 & pcm_rate = %u",
+					config->streams[1].pcm_rate);
+			return -EINVAL;
+		}
+	} else {
+		modes_b.num_of_modes = 0;
+	}
+
+	match_modes(&modes_ab, &modes_a, &modes_b);
+	ret = select_mode(&hw_cfg, &modes_ab);
+	if (ret < 0) {
+		LOG_ERR("select_mode failed");
+		return -EINVAL;
+	}
+
+	LOG_DBG("clkdiv %u mcic %u", hw_cfg.clkdiv, hw_cfg.mcic);
+	LOG_DBG("mfir_a %d mfir_b %d", hw_cfg.mfir_a, hw_cfg.mfir_b);
+	LOG_DBG("fir_a_length %d fir_b_length %d", hw_cfg.fir_a_length,
+			hw_cfg.fir_b_length);
+	LOG_DBG("cic_shift %d fir_a_shift %d fir_b_shift %d", hw_cfg.cic_shift,
+			hw_cfg.fir_a_shift, hw_cfg.fir_b_shift);
+
+	/* Struct reg contains a mirror of actual HW registers. Determine
+	 * register bits configuration from decimator configuration and the
+	 * requested parameters.
+	 */
+	ret = configure_registers(dev, &hw_cfg, config);
+	if (ret < 0) {
+		LOG_ERR("configure_registers failed RC: %d", ret);
+		return -EINVAL;
+	}
+
+	dmic_private.state = DMIC_STATE_CONFIGURED;
+
+	return 0;
+}
+
+/* start the DMIC for capture */
+static void dmic_start(struct device *dev)
+{
+	struct _stream_data *stream;
+	unsigned int key;
+	int i;
+	int mic_a;
+	int mic_b;
+	int fir_a;
+	int fir_b;
+	void *buffer;
+	int ret;
+
+	for (i = 0; i < dmic_private.num_streams; i++) {
+		stream = &dmic_private.streams[i];
+		/* allocate buffer for stream A */
+		ret = k_mem_slab_alloc(stream->mem_slab, &buffer, K_NO_WAIT);
+		if (ret) {
+			LOG_ERR("alloc from mem_slab_a %p failed",
+					stream->mem_slab);
+			return;
+		}
+		/* load buffer to DMA */
+		dmic_reload_dma((i == 0) ? DMA_CHANNEL_DMIC_RXA :
+				DMA_CHANNEL_DMIC_RXB,
+				buffer, stream->block_size);
+		ret = k_msgq_put(&stream->in_queue, &buffer, K_NO_WAIT);
+		if (ret) {
+			LOG_ERR("stream %u in_queue full", i);
+			k_mem_slab_free(stream->mem_slab, &buffer);
+			return;
+		}
+	}
+
+	/* enable port */
+	key = irq_lock();
+
+	for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
+		mic_a = dmic_private.mic_en_mask >> (PDM_CHAN_LEFT + (i << 1));
+		mic_a &= BIT(0);
+
+		mic_b = dmic_private.mic_en_mask >> (PDM_CHAN_RIGHT + (i << 1));
+		mic_b &= BIT(0);
+
+		if ((dmic_private.mic_en_mask >> (i << 1)) &
+				(BIT(PDM_CHAN_LEFT) | BIT(PDM_CHAN_RIGHT))) {
+			fir_a = (dmic_private.fifo_a) ? 1 : 0;
+			fir_b = (dmic_private.fifo_b) ? 1 : 0;
+		} else {
+			fir_a = fir_b = 0;
+		}
+
+		LOG_DBG("mic_a %d mic_b %d", mic_a, mic_b);
+		LOG_DBG("fir_a %d fir_b %d", fir_a, fir_b);
+
+		DMIC_REG_UPD(CIC_CONTROL(i),
+			CIC_CONTROL_CIC_START_A_BIT |
+			CIC_CONTROL_CIC_START_B_BIT,
+			CIC_CONTROL_CIC_START_A(mic_a) |
+			CIC_CONTROL_CIC_START_B(mic_b));
+		DMIC_REG_UPD(MIC_CONTROL(i),
+			MIC_CONTROL_PDM_EN_A_BIT |
+			MIC_CONTROL_PDM_EN_B_BIT,
+			MIC_CONTROL_PDM_EN_A(mic_a) |
+			MIC_CONTROL_PDM_EN_B(mic_b));
+
+		DMIC_REG_UPD(FIR_CONTROL_A(i),
+			FIR_CONTROL_A_START_BIT, FIR_CONTROL_A_START(fir_a));
+		DMIC_REG_UPD(FIR_CONTROL_B(i),
+			FIR_CONTROL_B_START_BIT, FIR_CONTROL_B_START(fir_b));
+		LOG_DBG("CIC_CONTROL[%u]: %08X", i,
+				DMIC_REG_RD(CIC_CONTROL(i)));
+		LOG_DBG("MIC_CONTROL[%u]: %08X", i,
+				DMIC_REG_RD(MIC_CONTROL(i)));
+		LOG_DBG("FIR_CONTROL_A[%u]: %08X", i,
+				DMIC_REG_RD(FIR_CONTROL_A(i)));
+		LOG_DBG("FIR_CONTROL_B[%u]: %08X", i,
+				DMIC_REG_RD(FIR_CONTROL_B(i)));
+	}
+
+	/* start the DMA channel(s) */
+	if (dmic_private.fifo_a) {
+		dmic_start_dma(DMA_CHANNEL_DMIC_RXA);
+	}
+
+	if (dmic_private.fifo_b) {
+		dmic_start_dma(DMA_CHANNEL_DMIC_RXB);
+	}
+
+	if (dmic_private.fifo_a) {
+		/*  Clear FIFO A initialize, Enable interrupts to DSP,
+		 *  Start FIFO A packer.
+		 */
+		DMIC_REG_UPD(OUTCONTROL0,
+			OUTCONTROL0_FINIT_BIT | OUTCONTROL0_SIP_BIT,
+			OUTCONTROL0_SIP_BIT);
+	}
+	if (dmic_private.fifo_b) {
+		/*  Clear FIFO B initialize, Enable interrupts to DSP,
+		 *  Start FIFO B packer.
+		 */
+		DMIC_REG_UPD(OUTCONTROL1,
+			OUTCONTROL1_FINIT_BIT | OUTCONTROL1_SIP_BIT,
+			OUTCONTROL1_SIP_BIT);
+	}
+
+	LOG_DBG("OUTCONTROL0: %08X", DMIC_REG_RD(OUTCONTROL0));
+	LOG_DBG("OUTCONTROL1: %08X", DMIC_REG_RD(OUTCONTROL1));
+
+	/* Clear soft reset for all/used PDM controllers. This should
+	 * start capture in sync.
+	 */
+	LOG_DBG("Releasing soft reset for all PDM controlers");
+	for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
+		DMIC_REG_UPD(CIC_CONTROL(i), CIC_CONTROL_SOFT_RESET_BIT, 0);
+	}
+
+	dmic_private.state = DMIC_STATE_ACTIVE;
+	irq_unlock(key);
+
+	LOG_DBG("State changed to DMIC_STATE_ACTIVE");
+
+	/* Currently there's no DMIC HW internal mutings and wait times
+	 * applied into this start sequence. It can be implemented here if
+	 * start of audio capture would contain clicks and/or noise and it
+	 * is not suppressed by gain ramp somewhere in the capture pipe.
+	 */
+}
+
+/* stop the DMIC for capture */
+static void dmic_stop(void)
+{
+	int i;
+
+	/* Stop FIFO packers and set FIFO initialize bits */
+	DMIC_REG_UPD(OUTCONTROL0,
+		OUTCONTROL0_SIP_BIT | OUTCONTROL0_FINIT_BIT,
+		OUTCONTROL0_FINIT_BIT);
+	DMIC_REG_UPD(OUTCONTROL1,
+		OUTCONTROL1_SIP_BIT | OUTCONTROL1_FINIT_BIT,
+		OUTCONTROL1_FINIT_BIT);
+
+	/* Set soft reset for all PDM controllers.
+	 */
+	LOG_DBG("Soft reset all PDM controllers");
+	for (i = 0; i < DMIC_HW_CONTROLLERS; i++) {
+		DMIC_REG_UPD(CIC_CONTROL(i),
+			CIC_CONTROL_SOFT_RESET_BIT, CIC_CONTROL_SOFT_RESET_BIT);
+	}
+}
+
+static int dmic_trigger_device(struct device *dev, enum dmic_trigger cmd)
+{
+	unsigned int key;
+
+	LOG_DBG("cmd: %d", cmd);
+
+	switch (cmd) {
+	case DMIC_TRIGGER_RELEASE:
+	case DMIC_TRIGGER_START:
+		if ((dmic_private.state == DMIC_STATE_CONFIGURED) ||
+				(dmic_private.state == DMIC_STATE_PAUSED)) {
+			dmic_start(dev);
+		} else {
+			LOG_ERR("Invalid state %d for cmd %d",
+					dmic_private.state, cmd);
+		}
+		break;
+	case DMIC_TRIGGER_STOP:
+	case DMIC_TRIGGER_PAUSE:
+	key = irq_lock();
+	dmic_private.state = DMIC_STATE_CONFIGURED;
+	irq_unlock(key);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static inline u8_t dmic_parse_clk_skew_map(u32_t skew_map, u8_t pdm)
+{
+	return (u8_t)((skew_map >> ((pdm & BIT_MASK(3)) * 4)) & BIT_MASK(4));
+}
+
+static int dmic_initialize_device(struct device *dev)
+{
+	int stream;
+	struct _stream_data *stream_data;
+	/* Initialize the buffer queues */
+	for (stream = 0; stream < DMIC_MAX_STREAMS; stream++) {
+		stream_data = &dmic_private.streams[stream];
+		k_msgq_init(&stream_data->in_queue,
+				(char *)stream_data->in_msgs,
+				sizeof(void *), DMIC_BUF_Q_LEN);
+		k_msgq_init(&stream_data->out_queue,
+				(char *)stream_data->out_msgs,
+				sizeof(void *), DMIC_BUF_Q_LEN);
+	}
+
+	/* Set state, note there is no playback direction support */
+	dmic_private.state = DMIC_STATE_INITIALIZED;
+
+	LOG_DBG("Device %s Initialized", dev->config->name);
+
+	return 0;
+}
+
+static int dmic_configure_device(struct device *dev, struct dmic_cfg *config)
+{
+	int ret = 0;
+
+	ret = dmic_set_config(dev, config);
+	if (ret) {
+		LOG_ERR("dmic_set_config failed with code %d", ret);
+	}
+
+	ret = dmic_configure_dma(config->streams, dmic_private.num_streams);
+	if (ret) {
+		LOG_ERR("dmic_configure_dma failed with code %d", ret);
+		return ret;
+	}
+
+	return ret;
+}
+
+static int dmic_read_device(struct device *dev, u8_t stream,
+		void **buffer, size_t *size, s32_t timeout)
+{
+	int ret;
+
+	if (stream >= dmic_private.num_streams) {
+		LOG_ERR("stream %u invalid. must be < %u", stream,
+				dmic_private.num_streams);
+		return -EINVAL;
+	}
+
+	/* retrieve buffer from out queue */
+	ret = k_msgq_get(&dmic_private.streams[stream].out_queue,
+			buffer, timeout);
+	if (ret) {
+		LOG_ERR("No buffers in stream %u out_queue", stream);
+	} else {
+		*size = dmic_private.streams[stream].block_size;
+		DCACHE_INVALIDATE(*buffer, *size);
+	}
+
+	return ret;
+}
+
+int dmic_configure_dma(struct pcm_stream_cfg *config, u8_t num_streams)
+{
+	int ret = 0;
+	int stream;
+	u32_t channel;
+	struct dma_block_config dma_block;
+	struct dma_config dma_cfg = {
+		.dma_slot		= DMA_HANDSHAKE_DMIC_RXA,
+		.channel_direction	= PERIPHERAL_TO_MEMORY,
+		.complete_callback_en	= 1,
+		.error_callback_en	= 0,
+		.source_handshake	= 0,
+		.dest_handshake		= 0,
+		.channel_priority	= 0,
+		.source_chaining_en	= 0,
+		.dest_chaining_en	= 0,
+		.source_data_size	= 4,
+		.dest_data_size		= 4,
+		.source_burst_length	= 8,
+		.dest_burst_length	= 8,
+		.block_count		= 1,
+		.head_block		= &dma_block,
+		.dma_callback		= dmic_dma_callback,
+	};
+
+	dmic_private.dma_dev = device_get_binding(DMIC_DMA_DEV_NAME);
+	if (!dmic_private.dma_dev) {
+		LOG_ERR("Failed to bind to device: %s", DMIC_DMA_DEV_NAME);
+		return -ENODEV;
+	}
+
+	for (stream = 0; stream < num_streams; stream++) {
+		channel = (stream == 0) ? DMA_CHANNEL_DMIC_RXA :
+			DMA_CHANNEL_DMIC_RXB;
+		dma_cfg.dma_slot = (stream == 0) ? DMA_HANDSHAKE_DMIC_RXA :
+			DMA_HANDSHAKE_DMIC_RXB;
+
+		LOG_DBG("Configuring stream %u DMA ch%u handshake %u", stream,
+				channel, dma_cfg.dma_slot);
+
+		dma_block.source_address = (u32_t)NULL;
+		dma_block.dest_address = (u32_t)NULL;
+		dma_block.block_size = 0;
+		dma_block.next_block = NULL;
+
+		ret = dma_config(dmic_private.dma_dev, channel, &dma_cfg);
+		if (ret) {
+			LOG_ERR("dma_config channel %u failed (%d)", channel,
+					ret);
+		}
+	}
+	return ret;
+}
+
+int dmic_reload_dma(u32_t channel, void *buffer, size_t size)
+{
+	u32_t source;
+
+	source = (channel == DMA_CHANNEL_DMIC_RXA) ? OUTDATA0 : OUTDATA1;
+
+	LOG_DBG("Loading buffer %p size %u to channel %u", buffer, size,
+			channel);
+	return dma_reload(dmic_private.dma_dev, channel,
+			PDM_BASE + source, (u32_t)buffer, size);
+}
+
+int dmic_start_dma(u32_t channel)
+{
+	LOG_DBG("Starting DMA channel %u", channel);
+	return dma_start(dmic_private.dma_dev, channel);
+}
+
+int dmic_stop_dma(u32_t channel)
+{
+	LOG_DBG("Stopping DMA channel %u", channel);
+	return dma_stop(dmic_private.dma_dev, channel);
+}
+
+static struct _dmic_ops dmic_ops = {
+	.trigger = dmic_trigger_device,
+	.configure = dmic_configure_device,
+	.read = dmic_read_device,
+};
+
+DEVICE_AND_API_INIT(dmic, "PDM", &dmic_initialize_device, NULL, NULL,
+		POST_KERNEL, CONFIG_AUDIO_DMIC_INIT_PRIORITY, &dmic_ops);
diff --git a/drivers/audio/intel_dmic.h b/drivers/audio/intel_dmic.h
new file mode 100644
index 00000000000..d9552798b87
--- /dev/null
+++ b/drivers/audio/intel_dmic.h
@@ -0,0 +1,237 @@
+/*
+ * Copyright (c) 2018, Intel Corporation
+ * All rights reserved.
+ *
+ * Author:	Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
+ *		Liam Girdwood <liam.r.girdwood@linux.intel.com>
+ *		Keyon Jie <yang.jie@linux.intel.com>
+ *		Sathish Kuttan <sathish.k.kuttan@intel.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __INTEL_DMIC_H__
+#define __INTEL_DMIC_H__
+
+#include <device.h>
+
+#define DMIC_HW_IOCLK		38400000
+
+/* Parameters used in modes computation */
+#define DMIC_HW_BITS_CIC		26
+#define DMIC_HW_BITS_FIR_COEF		20
+#define DMIC_HW_BITS_FIR_GAIN		20
+#define DMIC_HW_BITS_FIR_INPUT		22
+#define DMIC_HW_BITS_FIR_OUTPUT		24
+#define DMIC_HW_BITS_FIR_INTERNAL	26
+#define DMIC_HW_BITS_GAIN_OUTPUT	22
+#define DMIC_HW_FIR_LENGTH_MAX		250
+#define DMIC_HW_CIC_SHIFT_MIN		-8
+#define DMIC_HW_CIC_SHIFT_MAX		4
+#define DMIC_HW_FIR_SHIFT_MIN		0
+#define DMIC_HW_FIR_SHIFT_MAX		8
+#define DMIC_HW_CIC_DECIM_MIN		5
+#define DMIC_HW_CIC_DECIM_MAX		31 /* Note: Limited by BITS_CIC */
+#define DMIC_HW_FIR_DECIM_MIN		2
+#define DMIC_HW_FIR_DECIM_MAX		20 /* Note: Practical upper limit */
+#define DMIC_HW_SENS_Q28		BIT(28) /* 1.0 in Q1.28 format */
+#define DMIC_HW_PDM_CLK_MIN		100000 /* Note: Practical min value */
+#define DMIC_HW_DUTY_MIN		20 /* Note: Practical min value */
+#define DMIC_HW_DUTY_MAX		80 /* Note: Practical max value */
+
+/* DMIC register offsets */
+#define PDM_REG_BASE(pdm)	(((pdm) + 1) << 12)
+#define PDM_COEFF_A(pdm)	(PDM_REG_BASE(pdm) + 0x400)
+#define PDM_COEFF_B(pdm)	(PDM_REG_BASE(pdm) + 0x800)
+
+/* Global registers */
+#define OUTCONTROL0		0x0000
+#define OUTSTAT0		0x0004
+#define OUTDATA0		0x0008
+#define OUTCONTROL1		0x0100
+#define OUTSTAT1		0x0104
+#define OUTDATA1		0x0108
+
+/* Local registers in each PDMx */
+#define CIC_CONTROL(pdm)	(PDM_REG_BASE(pdm) + 0x000)
+#define CIC_CONFIG(pdm)		(PDM_REG_BASE(pdm) + 0x004)
+#define MIC_CONTROL(pdm)	(PDM_REG_BASE(pdm) + 0x00c)
+#define FIR_CONTROL_A(pdm)	(PDM_REG_BASE(pdm) + 0x020)
+#define FIR_CONFIG_A(pdm)	(PDM_REG_BASE(pdm) + 0x024)
+#define DC_OFFSET_LEFT_A(pdm)	(PDM_REG_BASE(pdm) + 0x028)
+#define DC_OFFSET_RIGHT_A(pdm)	(PDM_REG_BASE(pdm) + 0x02c)
+#define OUT_GAIN_LEFT_A(pdm)	(PDM_REG_BASE(pdm) + 0x030)
+#define OUT_GAIN_RIGHT_A(pdm)	(PDM_REG_BASE(pdm) + 0x034)
+#define FIR_CONTROL_B(pdm)	(PDM_REG_BASE(pdm) + 0x040)
+#define FIR_CONFIG_B(pdm)	(PDM_REG_BASE(pdm) + 0x044)
+#define DC_OFFSET_LEFT_B(pdm)	(PDM_REG_BASE(pdm) + 0x048)
+#define DC_OFFSET_RIGHT_B(pdm)	(PDM_REG_BASE(pdm) + 0x04c)
+#define OUT_GAIN_LEFT_B(pdm)	(PDM_REG_BASE(pdm) + 0x050)
+#define OUT_GAIN_RIGHT_B(pdm)	(PDM_REG_BASE(pdm) + 0x054)
+
+/* Register bits */
+
+/* OUTCONTROL0 bits */
+#define OUTCONTROL0_TIE_BIT			BIT(27)
+#define OUTCONTROL0_SIP_BIT			BIT(26)
+#define OUTCONTROL0_FINIT_BIT			BIT(25)
+#define OUTCONTROL0_FCI_BIT			BIT(24)
+#define OUTCONTROL0_TIE(x)			SET_BIT(27, x)
+#define OUTCONTROL0_SIP(x)			SET_BIT(26, x)
+#define OUTCONTROL0_FINIT(x)			SET_BIT(25, x)
+#define OUTCONTROL0_FCI(x)			SET_BIT(24, x)
+#define OUTCONTROL0_BFTH(x)			SET_BITS(23, 20, x)
+#define OUTCONTROL0_OF(x)			SET_BITS(19, 18, x)
+#define OUTCONTROL0_NUMBER_OF_DECIMATORS(x)	SET_BITS(17, 15, x)
+#define OUTCONTROL0_IPM_SOURCE_1(x)		SET_BITS(14, 13, x)
+#define OUTCONTROL0_IPM_SOURCE_2(x)		SET_BITS(12, 11, x)
+#define OUTCONTROL0_IPM_SOURCE_3(x)		SET_BITS(10, 9, x)
+#define OUTCONTROL0_IPM_SOURCE_4(x)		SET_BITS(8, 7, x)
+#define OUTCONTROL0_TH(x)			SET_BITS(5, 0, x)
+
+/* OUTCONTROL1 bits */
+#define OUTCONTROL1_TIE_BIT			BIT(27)
+#define OUTCONTROL1_SIP_BIT			BIT(26)
+#define OUTCONTROL1_FINIT_BIT			BIT(25)
+#define OUTCONTROL1_FCI_BIT			BIT(24)
+#define OUTCONTROL1_TIE(x)			SET_BIT(27, x)
+#define OUTCONTROL1_SIP(x)			SET_BIT(26, x)
+#define OUTCONTROL1_FINIT(x)			SET_BIT(25, x)
+#define OUTCONTROL1_FCI(x)			SET_BIT(24, x)
+#define OUTCONTROL1_BFTH(x)			SET_BITS(23, 20, x)
+#define OUTCONTROL1_OF(x)			SET_BITS(19, 18, x)
+#define OUTCONTROL1_NUMBER_OF_DECIMATORS(x)	SET_BITS(17, 15, x)
+#define OUTCONTROL1_IPM_SOURCE_1(x)		SET_BITS(14, 13, x)
+#define OUTCONTROL1_IPM_SOURCE_2(x)		SET_BITS(12, 11, x)
+#define OUTCONTROL1_IPM_SOURCE_3(x)		SET_BITS(10, 9, x)
+#define OUTCONTROL1_IPM_SOURCE_4(x)		SET_BITS(8, 7, x)
+#define OUTCONTROL1_TH(x)			SET_BITS(5, 0, x)
+
+/* OUTSTAT0 bits */
+#define OUTSTAT0_AFE_BIT	BIT(31)
+#define OUTSTAT0_ASNE_BIT	BIT(29)
+#define OUTSTAT0_RFS_BIT	BIT(28)
+#define OUTSTAT0_ROR_BIT	BIT(27)
+#define OUTSTAT0_FL_MASK	MASK(6, 0)
+
+/* OUTSTAT1 bits */
+#define OUTSTAT1_AFE_BIT	BIT(31)
+#define OUTSTAT1_ASNE_BIT	BIT(29)
+#define OUTSTAT1_RFS_BIT	BIT(28)
+#define OUTSTAT1_ROR_BIT	BIT(27)
+#define OUTSTAT1_FL_MASK	MASK(6, 0)
+
+/* CIC_CONTROL bits */
+#define CIC_CONTROL_SOFT_RESET_BIT	BIT(16)
+#define CIC_CONTROL_CIC_START_B_BIT	BIT(15)
+#define CIC_CONTROL_CIC_START_A_BIT	BIT(14)
+#define CIC_CONTROL_MIC_B_POLARITY_BIT	BIT(3)
+#define CIC_CONTROL_MIC_A_POLARITY_BIT	BIT(2)
+#define CIC_CONTROL_MIC_MUTE_BIT	BIT(1)
+#define CIC_CONTROL_STEREO_MODE_BIT	BIT(0)
+
+#define CIC_CONTROL_SOFT_RESET(x)	SET_BIT(16, x)
+#define CIC_CONTROL_CIC_START_B(x)	SET_BIT(15, x)
+#define CIC_CONTROL_CIC_START_A(x)	SET_BIT(14, x)
+#define CIC_CONTROL_MIC_B_POLARITY(x)	SET_BIT(3, x)
+#define CIC_CONTROL_MIC_A_POLARITY(x)	SET_BIT(2, x)
+#define CIC_CONTROL_MIC_MUTE(x)		SET_BIT(1, x)
+#define CIC_CONTROL_STEREO_MODE(x)	SET_BIT(0, x)
+
+/* CIC_CONFIG bits */
+#define CIC_CONFIG_CIC_SHIFT(x)		SET_BITS(27, 24, x)
+#define CIC_CONFIG_COMB_COUNT(x)	SET_BITS(15, 8, x)
+
+/* MIC_CONTROL bits */
+#define MIC_CONTROL_PDM_EN_B_BIT	BIT(1)
+#define MIC_CONTROL_PDM_EN_A_BIT	BIT(0)
+#define MIC_CONTROL_PDM_CLKDIV(x)	SET_BITS(15, 8, x)
+#define MIC_CONTROL_PDM_SKEW(x)		SET_BITS(7, 4, x)
+#define MIC_CONTROL_CLK_EDGE(x)		SET_BIT(3, x)
+#define MIC_CONTROL_PDM_EN_B(x)		SET_BIT(1, x)
+#define MIC_CONTROL_PDM_EN_A(x)		SET_BIT(0, x)
+
+/* FIR_CONTROL_A bits */
+#define FIR_CONTROL_A_START_BIT			BIT(7)
+#define FIR_CONTROL_A_ARRAY_START_EN_BIT	BIT(6)
+#define FIR_CONTROL_A_MUTE_BIT			BIT(1)
+#define FIR_CONTROL_A_START(x)			SET_BIT(7, x)
+#define FIR_CONTROL_A_ARRAY_START_EN(x)		SET_BIT(6, x)
+#define FIR_CONTROL_A_DCCOMP(x)			SET_BIT(4, x)
+#define FIR_CONTROL_A_MUTE(x)			SET_BIT(1, x)
+#define FIR_CONTROL_A_STEREO(x)			SET_BIT(0, x)
+
+/* FIR_CONFIG_A bits */
+#define FIR_CONFIG_A_FIR_DECIMATION(x)		SET_BITS(20, 16, x)
+#define FIR_CONFIG_A_FIR_SHIFT(x)		SET_BITS(11, 8, x)
+#define FIR_CONFIG_A_FIR_LENGTH(x)		SET_BITS(7, 0, x)
+
+/* DC offset compensation time constants */
+#define DCCOMP_TC0	0
+#define DCCOMP_TC1	1
+#define DCCOMP_TC2	2
+#define DCCOMP_TC3	3
+#define DCCOMP_TC4	4
+#define DCCOMP_TC5	5
+#define DCCOMP_TC6	6
+#define DCCOMP_TC7	7
+
+/* DC_OFFSET_LEFT_A bits */
+#define DC_OFFSET_LEFT_A_DC_OFFS(x)		SET_BITS(21, 0, x)
+
+/* DC_OFFSET_RIGHT_A bits */
+#define DC_OFFSET_RIGHT_A_DC_OFFS(x)		SET_BITS(21, 0, x)
+
+/* OUT_GAIN_LEFT_A bits */
+#define OUT_GAIN_LEFT_A_GAIN(x)			SET_BITS(19, 0, x)
+
+/* OUT_GAIN_RIGHT_A bits */
+#define OUT_GAIN_RIGHT_A_GAIN(x)		SET_BITS(19, 0, x)
+
+/* FIR_CONTROL_B bits */
+#define FIR_CONTROL_B_START_BIT			BIT(7)
+#define FIR_CONTROL_B_ARRAY_START_EN_BIT	BIT(6)
+#define FIR_CONTROL_B_MUTE_BIT			BIT(1)
+#define FIR_CONTROL_B_START(x)			SET_BIT(7, x)
+#define FIR_CONTROL_B_ARRAY_START_EN(x)		SET_BIT(6, x)
+#define FIR_CONTROL_B_DCCOMP(x)			SET_BIT(4, x)
+#define FIR_CONTROL_B_MUTE(x)			SET_BIT(1, x)
+#define FIR_CONTROL_B_STEREO(x)			SET_BIT(0, x)
+
+/* FIR_CONFIG_B bits */
+#define FIR_CONFIG_B_FIR_DECIMATION(x)		SET_BITS(20, 16, x)
+#define FIR_CONFIG_B_FIR_SHIFT(x)		SET_BITS(11, 8, x)
+#define FIR_CONFIG_B_FIR_LENGTH(x)		SET_BITS(7, 0, x)
+
+/* DC_OFFSET_LEFT_B bits */
+#define DC_OFFSET_LEFT_B_DC_OFFS(x)		SET_BITS(21, 0, x)
+
+/* DC_OFFSET_RIGHT_B bits */
+#define DC_OFFSET_RIGHT_B_DC_OFFS(x)		SET_BITS(21, 0, x)
+
+/* OUT_GAIN_LEFT_B bits */
+#define OUT_GAIN_LEFT_B_GAIN(x)			SET_BITS(19, 0, x)
+
+/* OUT_GAIN_RIGHT_B bits */
+#define OUT_GAIN_RIGHT_B_GAIN(x)		SET_BITS(19, 0, x)
+
+/* FIR coefficients */
+#define FIR_COEF_A(x)				SET_BITS(19, 0, x)
+#define FIR_COEF_B(x)				SET_BITS(19, 0, x)
+
+/* max number of streams supported by hardware 2 = Stream A & B */
+#define DMIC_MAX_STREAMS			2
+
+#define DMIC_DMA_DEV_NAME			CONFIG_DMA_0_NAME
+#define DMA_CHANNEL_DMIC_RXA			0
+#define DMA_CHANNEL_DMIC_RXB			1
+
+#define DMA_HANDSHAKE_DMIC_RXA			0
+#define DMA_HANDSHAKE_DMIC_RXB			1
+
+int dmic_configure_dma(struct pcm_stream_cfg *config, u8_t num_streams);
+int dmic_reload_dma(u32_t channel, void *buffer, size_t size);
+int dmic_start_dma(u32_t channel);
+int dmic_stop_dma(u32_t channel);
+
+#endif /* __INTEL_DMIC_H__ */
diff --git a/soc/xtensa/intel_s1000/soc.h b/soc/xtensa/intel_s1000/soc.h
index 07bcc3111b9..26a3925a5bc 100644
--- a/soc/xtensa/intel_s1000/soc.h
+++ b/soc/xtensa/intel_s1000/soc.h
@@ -62,6 +62,8 @@
 #define CAVS_DMA1_OWNERSHIP_REG			(0x00071A62)
 #define CAVS_DMA2_OWNERSHIP_REG			(0x00071A64)
 
+#define DMA_HANDSHAKE_DMIC_RXA			0
+#define DMA_HANDSHAKE_DMIC_RXB			1
 #define DMA_HANDSHAKE_SSP0_TX			2
 #define DMA_HANDSHAKE_SSP0_RX			3
 #define DMA_HANDSHAKE_SSP1_TX			4
@@ -71,6 +73,14 @@
 #define DMA_HANDSHAKE_SSP3_TX			8
 #define DMA_HANDSHAKE_SSP3_RX			9
 
+/* DMA Channel Allocation
+ * FIXME: I2S Driver assigns channel in Kconfig.
+ * Perhaps DTS is a better option
+ */
+#define DMIC_DMA_DEV_NAME			CONFIG_DMA_0_NAME
+#define DMA_CHANNEL_DMIC_RXA			0
+#define DMA_CHANNEL_DMIC_RXB			1
+
 /* I2S */
 #define I2S0_CAVS_IRQ				0x00000010
 #define I2S1_CAVS_IRQ				0x00000110