kconfig: Make the CPU_HAS_FPU_DOUBLE_PRECISION option global.
This option now applies to the RISC-V architecture and is no longer a ARM only configuration. Signed-off-by: Corey Wharton <coreyw7@fb.com>
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parent
22c52846a5
commit
c8f7cd5462
10 changed files with 25 additions and 31 deletions
14
arch/Kconfig
14
arch/Kconfig
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@ -464,6 +464,13 @@ config CPU_HAS_FPU
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This option is enabled when the CPU has hardware floating point
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unit.
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config CPU_HAS_FPU_DOUBLE_PRECISION
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bool
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select CPU_HAS_FPU
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help
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When enabled, this indicates that the CPU has a double floating point
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precision unit.
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config CPU_HAS_MPU
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bool
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help
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@ -531,13 +538,6 @@ config FP_SHARING
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This option allows multiple threads to use the floating point
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registers.
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config FLOAT_64BIT
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bool "Double precision floating point"
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depends on FLOAT
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depends on RISCV
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help
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This option means that floating point registers are 64bit width.
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config ARCH
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string
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help
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@ -12,16 +12,18 @@ else()
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string(CONCAT riscv_march ${riscv_march} "32ima")
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endif()
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if(CONFIG_FLOAT_64BIT)
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if(CONFIG_FLOAT_HARD)
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string(CONCAT riscv_mabi ${riscv_mabi} "d")
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if(CONFIG_FLOAT)
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if(CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION)
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if(CONFIG_FLOAT_HARD)
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string(CONCAT riscv_mabi ${riscv_mabi} "d")
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endif()
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string(CONCAT riscv_march ${riscv_march} "fd")
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else()
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if(CONFIG_FLOAT_HARD)
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string(CONCAT riscv_mabi ${riscv_mabi} "f")
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endif()
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string(CONCAT riscv_march ${riscv_march} "f")
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endif()
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string(CONCAT riscv_march ${riscv_march} "fd")
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elseif(CONFIG_FLOAT)
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if(CONFIG_FLOAT_HARD)
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string(CONCAT riscv_mabi ${riscv_mabi} "f")
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endif()
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string(CONCAT riscv_march ${riscv_march} "f")
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endif()
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if(CONFIG_COMPRESSED_ISA)
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@ -40,7 +40,7 @@
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#define RV_REGSHIFT 2
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#endif
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#ifdef CONFIG_FLOAT_64BIT
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#ifdef CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION
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#define RV_OP_LOADFPREG fld
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#define RV_OP_STOREFPREG fsd
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#else
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@ -42,7 +42,7 @@ struct soc_esf {
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#endif
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#if !defined(RV_FP_TYPE) && defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
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#ifdef CONFIG_FLOAT_64BIT
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#ifdef CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION
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#define RV_FP_TYPE u64_t
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#else
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#define RV_FP_TYPE u32_t
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@ -23,7 +23,7 @@
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#include <zephyr/types.h>
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#if !defined(RV_FP_TYPE) && defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
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#ifdef CONFIG_FLOAT_64BIT
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#ifdef CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION
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#define RV_FP_TYPE u64_t
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#else
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#define RV_FP_TYPE u32_t
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@ -57,14 +57,6 @@ config NRF_SPU_RAM_REGION_SIZE
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RAM region size for the NRF_SPU peripheral
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endif
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config CPU_HAS_FPU_DOUBLE_PRECISION
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bool
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depends on CPU_CORTEX_M7
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select CPU_HAS_FPU
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help
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When enabled, indicates that the SoC has a double
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floating point precision unit.
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config HAS_SWO
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bool
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help
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@ -78,7 +78,7 @@ void test_k_float_disable_common(void)
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"usr_fp_thread FP options not set (0x%0x)",
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usr_fp_thread.base.user_options);
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#if defined(CONFIG_ARM) || defined(RISCV)
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#if defined(CONFIG_ARM) || defined(CONFIG_RISCV)
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/* Verify FP mode can only be disabled for current thread */
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zassert_true((k_float_disable(&usr_fp_thread) == -EINVAL),
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"k_float_disable() successful on thread other than current!");
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@ -109,7 +109,7 @@ struct fp_non_volatile_register_set {
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#elif defined(CONFIG_RISCV)
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struct fp_volatile_register_set {
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#ifdef CONFIG_FLOAT_64BIT
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#ifdef CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION
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u64_t fp[32];
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#else
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u32_t fp[32];
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@ -19,7 +19,7 @@
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#include <toolchain.h>
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#include "float_context.h"
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#ifdef CONFIG_FLOAT_64BIT
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#ifdef CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION
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#define RV_FPREG_WIDTH 8
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#define RV_FPREG_SAVE "fsd "
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#define RV_FPREG_LOAD "fld "
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@ -9,7 +9,7 @@
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/*
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* Test Thread Parameters
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*/
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#define THREAD_STACK_SIZE 2048
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#define THREAD_STACK_SIZE 1024
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#define THREAD_HIGH_PRIORITY 5
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#define THREAD_LOW_PRIORITY 10
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