kconfig: Make the CPU_HAS_FPU_DOUBLE_PRECISION option global.

This option now applies to the RISC-V architecture and is no longer
a ARM only configuration.

Signed-off-by: Corey Wharton <coreyw7@fb.com>
This commit is contained in:
Corey Wharton 2020-04-14 11:06:23 -07:00 committed by Andrew Boie
commit c8f7cd5462
10 changed files with 25 additions and 31 deletions

View file

@ -464,6 +464,13 @@ config CPU_HAS_FPU
This option is enabled when the CPU has hardware floating point
unit.
config CPU_HAS_FPU_DOUBLE_PRECISION
bool
select CPU_HAS_FPU
help
When enabled, this indicates that the CPU has a double floating point
precision unit.
config CPU_HAS_MPU
bool
help
@ -531,13 +538,6 @@ config FP_SHARING
This option allows multiple threads to use the floating point
registers.
config FLOAT_64BIT
bool "Double precision floating point"
depends on FLOAT
depends on RISCV
help
This option means that floating point registers are 64bit width.
config ARCH
string
help

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@ -12,16 +12,18 @@ else()
string(CONCAT riscv_march ${riscv_march} "32ima")
endif()
if(CONFIG_FLOAT_64BIT)
if(CONFIG_FLOAT_HARD)
string(CONCAT riscv_mabi ${riscv_mabi} "d")
if(CONFIG_FLOAT)
if(CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION)
if(CONFIG_FLOAT_HARD)
string(CONCAT riscv_mabi ${riscv_mabi} "d")
endif()
string(CONCAT riscv_march ${riscv_march} "fd")
else()
if(CONFIG_FLOAT_HARD)
string(CONCAT riscv_mabi ${riscv_mabi} "f")
endif()
string(CONCAT riscv_march ${riscv_march} "f")
endif()
string(CONCAT riscv_march ${riscv_march} "fd")
elseif(CONFIG_FLOAT)
if(CONFIG_FLOAT_HARD)
string(CONCAT riscv_mabi ${riscv_mabi} "f")
endif()
string(CONCAT riscv_march ${riscv_march} "f")
endif()
if(CONFIG_COMPRESSED_ISA)

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@ -40,7 +40,7 @@
#define RV_REGSHIFT 2
#endif
#ifdef CONFIG_FLOAT_64BIT
#ifdef CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION
#define RV_OP_LOADFPREG fld
#define RV_OP_STOREFPREG fsd
#else

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@ -42,7 +42,7 @@ struct soc_esf {
#endif
#if !defined(RV_FP_TYPE) && defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
#ifdef CONFIG_FLOAT_64BIT
#ifdef CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION
#define RV_FP_TYPE u64_t
#else
#define RV_FP_TYPE u32_t

View file

@ -23,7 +23,7 @@
#include <zephyr/types.h>
#if !defined(RV_FP_TYPE) && defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
#ifdef CONFIG_FLOAT_64BIT
#ifdef CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION
#define RV_FP_TYPE u64_t
#else
#define RV_FP_TYPE u32_t

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@ -57,14 +57,6 @@ config NRF_SPU_RAM_REGION_SIZE
RAM region size for the NRF_SPU peripheral
endif
config CPU_HAS_FPU_DOUBLE_PRECISION
bool
depends on CPU_CORTEX_M7
select CPU_HAS_FPU
help
When enabled, indicates that the SoC has a double
floating point precision unit.
config HAS_SWO
bool
help

View file

@ -78,7 +78,7 @@ void test_k_float_disable_common(void)
"usr_fp_thread FP options not set (0x%0x)",
usr_fp_thread.base.user_options);
#if defined(CONFIG_ARM) || defined(RISCV)
#if defined(CONFIG_ARM) || defined(CONFIG_RISCV)
/* Verify FP mode can only be disabled for current thread */
zassert_true((k_float_disable(&usr_fp_thread) == -EINVAL),
"k_float_disable() successful on thread other than current!");

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@ -109,7 +109,7 @@ struct fp_non_volatile_register_set {
#elif defined(CONFIG_RISCV)
struct fp_volatile_register_set {
#ifdef CONFIG_FLOAT_64BIT
#ifdef CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION
u64_t fp[32];
#else
u32_t fp[32];

View file

@ -19,7 +19,7 @@
#include <toolchain.h>
#include "float_context.h"
#ifdef CONFIG_FLOAT_64BIT
#ifdef CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION
#define RV_FPREG_WIDTH 8
#define RV_FPREG_SAVE "fsd "
#define RV_FPREG_LOAD "fld "

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@ -9,7 +9,7 @@
/*
* Test Thread Parameters
*/
#define THREAD_STACK_SIZE 2048
#define THREAD_STACK_SIZE 1024
#define THREAD_HIGH_PRIORITY 5
#define THREAD_LOW_PRIORITY 10