Bluetooth: controller: remove hidden GPIOTE configs
The GPIOTE channels used to manage radio front end module GPIOs are configured with invisible Kconfig symbols. They are therefore not user visible. Remove them by redefining them in terms of equivalent macros defined in radio_nrf5.h. This lets us get rid of a couple of ifdefs that are no longer needed as well. This is because these invisible symbols depend on the CONFIG_BT_CTLR_GPIO_* pin configuration symbols. We would like to move all of that pin configuration to devicetree, because it's hardware description. It is therefore inconvenient to have the GPIOTE channel configuration set via Kconfig in a way that depends on something we would like to remove. No functional changes or user impact expected: invisible symbols cannot be set in .conf files. Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This commit is contained in:
parent
d2ba94bbea
commit
c8aee4d04f
5 changed files with 41 additions and 72 deletions
|
@ -791,33 +791,6 @@ config BT_CTLR_GPIO_PDN_CSN_OFFSET
|
||||||
|
|
||||||
endif # BT_CTLR_FEM_NRF21540
|
endif # BT_CTLR_FEM_NRF21540
|
||||||
|
|
||||||
config BT_CTLR_PA_LNA_GPIOTE_CHAN
|
|
||||||
# Hidden "nRF5 GPIO PA/LNA GPIOTE Channel"
|
|
||||||
int
|
|
||||||
depends on SOC_FAMILY_NRF && (BT_CTLR_GPIO_PA || BT_CTLR_GPIO_LNA)
|
|
||||||
default 3 if PWM_NRF5_SW
|
|
||||||
default 0
|
|
||||||
help
|
|
||||||
Select the nRF5 GPIOTE channel to use for PA/LNA GPIO feature.
|
|
||||||
|
|
||||||
config BT_CTLR_PDN_GPIOTE_CHAN
|
|
||||||
# Hidden "nRF5 GPIO FEM PDN GPIOTE Channel"
|
|
||||||
int
|
|
||||||
depends on SOC_FAMILY_NRF && BT_CTLR_FEM_NRF21540
|
|
||||||
default 4 if PWM_NRF5_SW
|
|
||||||
default 1
|
|
||||||
help
|
|
||||||
Select the nRF5 GPIOTE channel to use for FEM PDN GPIO pin toggle.
|
|
||||||
|
|
||||||
config BT_CTLR_CSN_GPIOTE_CHAN
|
|
||||||
# Hidden "nRF5 GPIO FEM CSN GPIOTE Channel"
|
|
||||||
int
|
|
||||||
depends on SOC_FAMILY_NRF && BT_CTLR_FEM_NRF21540
|
|
||||||
default 5 if PWM_NRF5_SW
|
|
||||||
default 2
|
|
||||||
help
|
|
||||||
Select the nRF5 GPIOTE channel to use for FEM CSN GPIO pin toggle.
|
|
||||||
|
|
||||||
comment "BLE Controller debug configuration"
|
comment "BLE Controller debug configuration"
|
||||||
|
|
||||||
config BT_CTLR_PROFILE_ISR
|
config BT_CTLR_PROFILE_ISR
|
||||||
|
|
|
@ -1129,7 +1129,7 @@ void radio_gpio_pa_setup(void)
|
||||||
* CONFIG_BT_CTLR_GPIO_PA_PIN by GPIOTE_CONFIG_PSEL_Pos will
|
* CONFIG_BT_CTLR_GPIO_PA_PIN by GPIOTE_CONFIG_PSEL_Pos will
|
||||||
* set the NRF_GPIOTE->CONFIG[n].PORT to 1 (P1 port).
|
* set the NRF_GPIOTE->CONFIG[n].PORT to 1 (P1 port).
|
||||||
*/
|
*/
|
||||||
NRF_GPIOTE->CONFIG[CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN] =
|
NRF_GPIOTE->CONFIG[HAL_PALNA_GPIOTE_CHAN] =
|
||||||
(GPIOTE_CONFIG_MODE_Task <<
|
(GPIOTE_CONFIG_MODE_Task <<
|
||||||
GPIOTE_CONFIG_MODE_Pos) |
|
GPIOTE_CONFIG_MODE_Pos) |
|
||||||
(CONFIG_BT_CTLR_GPIO_PA_PIN <<
|
(CONFIG_BT_CTLR_GPIO_PA_PIN <<
|
||||||
|
@ -1159,7 +1159,7 @@ void radio_gpio_lna_setup(void)
|
||||||
* CONFIG_BT_CTLR_GPIO_LNA_PIN by GPIOTE_CONFIG_PSEL_Pos will
|
* CONFIG_BT_CTLR_GPIO_LNA_PIN by GPIOTE_CONFIG_PSEL_Pos will
|
||||||
* set the NRF_GPIOTE->CONFIG[n].PORT to 1 (P1 port).
|
* set the NRF_GPIOTE->CONFIG[n].PORT to 1 (P1 port).
|
||||||
*/
|
*/
|
||||||
NRF_GPIOTE->CONFIG[CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN] =
|
NRF_GPIOTE->CONFIG[HAL_PALNA_GPIOTE_CHAN] =
|
||||||
(GPIOTE_CONFIG_MODE_Task <<
|
(GPIOTE_CONFIG_MODE_Task <<
|
||||||
GPIOTE_CONFIG_MODE_Pos) |
|
GPIOTE_CONFIG_MODE_Pos) |
|
||||||
(CONFIG_BT_CTLR_GPIO_LNA_PIN <<
|
(CONFIG_BT_CTLR_GPIO_LNA_PIN <<
|
||||||
|
@ -1188,7 +1188,7 @@ void radio_gpio_pdn_setup(void)
|
||||||
* CONFIG_BT_CTLR_GPIO_PA_PIN by GPIOTE_CONFIG_PSEL_Pos will
|
* CONFIG_BT_CTLR_GPIO_PA_PIN by GPIOTE_CONFIG_PSEL_Pos will
|
||||||
* set the NRF_GPIOTE->CONFIG[n].PORT to 1 (P1 port).
|
* set the NRF_GPIOTE->CONFIG[n].PORT to 1 (P1 port).
|
||||||
*/
|
*/
|
||||||
NRF_GPIOTE->CONFIG[CONFIG_BT_CTLR_PDN_GPIOTE_CHAN] =
|
NRF_GPIOTE->CONFIG[HAL_PDN_GPIOTE_CHAN] =
|
||||||
(GPIOTE_CONFIG_MODE_Task <<
|
(GPIOTE_CONFIG_MODE_Task <<
|
||||||
GPIOTE_CONFIG_MODE_Pos) |
|
GPIOTE_CONFIG_MODE_Pos) |
|
||||||
(CONFIG_BT_CTLR_GPIO_PDN_PIN <<
|
(CONFIG_BT_CTLR_GPIO_PDN_PIN <<
|
||||||
|
@ -1212,7 +1212,7 @@ void radio_gpio_csn_setup(void)
|
||||||
* CONFIG_BT_CTLR_GPIO_PA_PIN by GPIOTE_CONFIG_PSEL_Pos will
|
* CONFIG_BT_CTLR_GPIO_PA_PIN by GPIOTE_CONFIG_PSEL_Pos will
|
||||||
* set the NRF_GPIOTE->CONFIG[n].PORT to 1 (P1 port).
|
* set the NRF_GPIOTE->CONFIG[n].PORT to 1 (P1 port).
|
||||||
*/
|
*/
|
||||||
NRF_GPIOTE->CONFIG[CONFIG_BT_CTLR_CSN_GPIOTE_CHAN] =
|
NRF_GPIOTE->CONFIG[HAL_CSN_GPIOTE_CHAN] =
|
||||||
(GPIOTE_CONFIG_MODE_Task <<
|
(GPIOTE_CONFIG_MODE_Task <<
|
||||||
GPIOTE_CONFIG_MODE_Pos) |
|
GPIOTE_CONFIG_MODE_Pos) |
|
||||||
(CONFIG_BT_CTLR_GPIO_CSN_PIN <<
|
(CONFIG_BT_CTLR_GPIO_CSN_PIN <<
|
||||||
|
@ -1271,13 +1271,13 @@ void radio_gpio_pa_lna_disable(void)
|
||||||
BIT(HAL_DISABLE_PALNA_PPI) |
|
BIT(HAL_DISABLE_PALNA_PPI) |
|
||||||
BIT(HAL_ENABLE_FEM_PPI) |
|
BIT(HAL_ENABLE_FEM_PPI) |
|
||||||
BIT(HAL_DISABLE_FEM_PPI));
|
BIT(HAL_DISABLE_FEM_PPI));
|
||||||
NRF_GPIOTE->CONFIG[CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN] = 0;
|
NRF_GPIOTE->CONFIG[HAL_PALNA_GPIOTE_CHAN] = 0;
|
||||||
NRF_GPIOTE->CONFIG[CONFIG_BT_CTLR_PDN_GPIOTE_CHAN] = 0;
|
NRF_GPIOTE->CONFIG[HAL_PDN_GPIOTE_CHAN] = 0;
|
||||||
NRF_GPIOTE->CONFIG[CONFIG_BT_CTLR_CSN_GPIOTE_CHAN] = 0;
|
NRF_GPIOTE->CONFIG[HAL_CSN_GPIOTE_CHAN] = 0;
|
||||||
#else
|
#else
|
||||||
hal_radio_nrf_ppi_channels_disable(BIT(HAL_ENABLE_PALNA_PPI) |
|
hal_radio_nrf_ppi_channels_disable(BIT(HAL_ENABLE_PALNA_PPI) |
|
||||||
BIT(HAL_DISABLE_PALNA_PPI));
|
BIT(HAL_DISABLE_PALNA_PPI));
|
||||||
NRF_GPIOTE->CONFIG[CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN] = 0;
|
NRF_GPIOTE->CONFIG[HAL_PALNA_GPIOTE_CHAN] = 0;
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
#endif /* CONFIG_BT_CTLR_GPIO_PA_PIN || CONFIG_BT_CTLR_GPIO_LNA_PIN */
|
#endif /* CONFIG_BT_CTLR_GPIO_PA_PIN || CONFIG_BT_CTLR_GPIO_LNA_PIN */
|
||||||
|
|
|
@ -50,6 +50,16 @@
|
||||||
|
|
||||||
#include <nrf_peripherals.h>
|
#include <nrf_peripherals.h>
|
||||||
|
|
||||||
|
#if defined(CONFIG_PWM_NRF5_SW)
|
||||||
|
#define HAL_PALNA_GPIOTE_CHAN 3
|
||||||
|
#define HAL_PDN_GPIOTE_CHAN 4
|
||||||
|
#define HAL_CSN_GPIOTE_CHAN 5
|
||||||
|
#else
|
||||||
|
#define HAL_PALNA_GPIOTE_CHAN 0
|
||||||
|
#define HAL_PDN_GPIOTE_CHAN 1
|
||||||
|
#define HAL_CSN_GPIOTE_CHAN 2
|
||||||
|
#endif
|
||||||
|
|
||||||
#if defined(PPI_PRESENT)
|
#if defined(PPI_PRESENT)
|
||||||
#include "radio_nrf5_ppi.h"
|
#include "radio_nrf5_ppi.h"
|
||||||
#elif defined(DPPI_PRESENT)
|
#elif defined(DPPI_PRESENT)
|
||||||
|
|
|
@ -169,8 +169,6 @@ static inline void hal_trigger_rateoverride_ppi_config(void)
|
||||||
}
|
}
|
||||||
|
|
||||||
/******************************************************************************/
|
/******************************************************************************/
|
||||||
#if defined(CONFIG_BT_CTLR_GPIO_PA_PIN) || defined(CONFIG_BT_CTLR_GPIO_LNA_PIN)
|
|
||||||
|
|
||||||
#define HAL_ENABLE_PALNA_PPI 5
|
#define HAL_ENABLE_PALNA_PPI 5
|
||||||
|
|
||||||
#if defined(CONFIG_BT_CTLR_FEM_NRF21540)
|
#if defined(CONFIG_BT_CTLR_FEM_NRF21540)
|
||||||
|
@ -189,13 +187,11 @@ static inline void hal_palna_ppi_setup(void)
|
||||||
#if !defined(CONFIG_BT_CTLR_FEM_NRF21540)
|
#if !defined(CONFIG_BT_CTLR_FEM_NRF21540)
|
||||||
nrf_gpiote_task_t task;
|
nrf_gpiote_task_t task;
|
||||||
|
|
||||||
task = nrf_gpiote_out_task_get(CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN);
|
task = nrf_gpiote_out_task_get(HAL_PALNA_GPIOTE_CHAN);
|
||||||
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_PALNA_PPI);
|
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_PALNA_PPI);
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* CONFIG_BT_CTLR_GPIO_PA_PIN || CONFIG_BT_CTLR_GPIO_LNA_PIN */
|
|
||||||
|
|
||||||
/******************************************************************************/
|
/******************************************************************************/
|
||||||
#if defined(CONFIG_BT_CTLR_FEM_NRF21540)
|
#if defined(CONFIG_BT_CTLR_FEM_NRF21540)
|
||||||
|
|
||||||
|
@ -204,14 +200,14 @@ static inline void hal_pa_ppi_setup(void)
|
||||||
nrf_gpiote_task_t task;
|
nrf_gpiote_task_t task;
|
||||||
|
|
||||||
#if defined(CONFIG_BT_CTLR_GPIO_PA_POL_INV)
|
#if defined(CONFIG_BT_CTLR_GPIO_PA_POL_INV)
|
||||||
task = nrf_gpiote_clr_task_get(CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN);
|
task = nrf_gpiote_clr_task_get(HAL_PALNA_GPIOTE_CHAN);
|
||||||
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_ENABLE_PALNA_PPI);
|
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_ENABLE_PALNA_PPI);
|
||||||
task = nrf_gpiote_set_task_get(CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN);
|
task = nrf_gpiote_set_task_get(HAL_PALNA_GPIOTE_CHAN);
|
||||||
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_PALNA_PPI);
|
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_PALNA_PPI);
|
||||||
#else /* !CONFIG_BT_CTLR_GPIO_PA_POL_INV */
|
#else /* !CONFIG_BT_CTLR_GPIO_PA_POL_INV */
|
||||||
task = nrf_gpiote_set_task_get(CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN);
|
task = nrf_gpiote_set_task_get(HAL_PALNA_GPIOTE_CHAN);
|
||||||
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_ENABLE_PALNA_PPI);
|
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_ENABLE_PALNA_PPI);
|
||||||
task = nrf_gpiote_clr_task_get(CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN);
|
task = nrf_gpiote_clr_task_get(HAL_PALNA_GPIOTE_CHAN);
|
||||||
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_PALNA_PPI);
|
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_PALNA_PPI);
|
||||||
#endif /* !CONFIG_BT_CTLR_GPIO_PA_POL_INV */
|
#endif /* !CONFIG_BT_CTLR_GPIO_PA_POL_INV */
|
||||||
}
|
}
|
||||||
|
@ -221,14 +217,14 @@ static inline void hal_lna_ppi_setup(void)
|
||||||
nrf_gpiote_task_t task;
|
nrf_gpiote_task_t task;
|
||||||
|
|
||||||
#if defined(CONFIG_BT_CTLR_GPIO_LNA_POL_INV)
|
#if defined(CONFIG_BT_CTLR_GPIO_LNA_POL_INV)
|
||||||
task = nrf_gpiote_clr_task_get(CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN);
|
task = nrf_gpiote_clr_task_get(HAL_PALNA_GPIOTE_CHAN);
|
||||||
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_ENABLE_PALNA_PPI);
|
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_ENABLE_PALNA_PPI);
|
||||||
task = nrf_gpiote_set_task_get(CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN);
|
task = nrf_gpiote_set_task_get(HAL_PALNA_GPIOTE_CHAN);
|
||||||
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_PALNA_PPI);
|
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_PALNA_PPI);
|
||||||
#else /* !CONFIG_BT_CTLR_GPIO_LNA_POL_INV */
|
#else /* !CONFIG_BT_CTLR_GPIO_LNA_POL_INV */
|
||||||
task = nrf_gpiote_set_task_get(CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN);
|
task = nrf_gpiote_set_task_get(HAL_PALNA_GPIOTE_CHAN);
|
||||||
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_ENABLE_PALNA_PPI);
|
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_ENABLE_PALNA_PPI);
|
||||||
task = nrf_gpiote_clr_task_get(CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN);
|
task = nrf_gpiote_clr_task_get(HAL_PALNA_GPIOTE_CHAN);
|
||||||
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_PALNA_PPI);
|
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_PALNA_PPI);
|
||||||
#endif /* !CONFIG_BT_CTLR_GPIO_LNA_POL_INV */
|
#endif /* !CONFIG_BT_CTLR_GPIO_LNA_POL_INV */
|
||||||
}
|
}
|
||||||
|
@ -246,26 +242,26 @@ static inline void hal_fem_ppi_setup(void)
|
||||||
HAL_DISABLE_FEM_PPI);
|
HAL_DISABLE_FEM_PPI);
|
||||||
|
|
||||||
#if defined(CONFIG_BT_CTLR_GPIO_PDN_POL_INV)
|
#if defined(CONFIG_BT_CTLR_GPIO_PDN_POL_INV)
|
||||||
task = nrf_gpiote_clr_task_get(CONFIG_BT_CTLR_PDN_GPIOTE_CHAN);
|
task = nrf_gpiote_clr_task_get(HAL_PDN_GPIOTE_CHAN);
|
||||||
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_ENABLE_FEM_PPI);
|
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_ENABLE_FEM_PPI);
|
||||||
task = nrf_gpiote_set_task_get(CONFIG_BT_CTLR_PDN_GPIOTE_CHAN);
|
task = nrf_gpiote_set_task_get(HAL_PDN_GPIOTE_CHAN);
|
||||||
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_FEM_PPI);
|
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_FEM_PPI);
|
||||||
#else /* !CONFIG_BT_CTLR_GPIO_PDN_POL_INV */
|
#else /* !CONFIG_BT_CTLR_GPIO_PDN_POL_INV */
|
||||||
task = nrf_gpiote_set_task_get(CONFIG_BT_CTLR_PDN_GPIOTE_CHAN);
|
task = nrf_gpiote_set_task_get(HAL_PDN_GPIOTE_CHAN);
|
||||||
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_ENABLE_FEM_PPI);
|
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_ENABLE_FEM_PPI);
|
||||||
task = nrf_gpiote_clr_task_get(CONFIG_BT_CTLR_PDN_GPIOTE_CHAN);
|
task = nrf_gpiote_clr_task_get(HAL_PDN_GPIOTE_CHAN);
|
||||||
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_FEM_PPI);
|
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_FEM_PPI);
|
||||||
#endif /* !CONFIG_BT_CTLR_GPIO_PDN_POL_INV */
|
#endif /* !CONFIG_BT_CTLR_GPIO_PDN_POL_INV */
|
||||||
|
|
||||||
#if defined(CONFIG_BT_CTLR_GPIO_CSN_POL_INV)
|
#if defined(CONFIG_BT_CTLR_GPIO_CSN_POL_INV)
|
||||||
task = nrf_gpiote_clr_task_get(CONFIG_BT_CTLR_CSN_GPIOTE_CHAN);
|
task = nrf_gpiote_clr_task_get(HAL_CSN_GPIOTE_CHAN);
|
||||||
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_ENABLE_FEM_PPI);
|
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_ENABLE_FEM_PPI);
|
||||||
task = nrf_gpiote_set_task_get(CONFIG_BT_CTLR_CSN_GPIOTE_CHAN);
|
task = nrf_gpiote_set_task_get(HAL_CSN_GPIOTE_CHAN);
|
||||||
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_FEM_PPI);
|
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_FEM_PPI);
|
||||||
#else /* !CONFIG_BT_CTLR_GPIO_CSN_POL_INV */
|
#else /* !CONFIG_BT_CTLR_GPIO_CSN_POL_INV */
|
||||||
task = nrf_gpiote_set_task_get(CONFIG_BT_CTLR_CSN_GPIOTE_CHAN);
|
task = nrf_gpiote_set_task_get(HAL_CSN_GPIOTE_CHAN);
|
||||||
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_ENABLE_FEM_PPI);
|
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_ENABLE_FEM_PPI);
|
||||||
task = nrf_gpiote_clr_task_get(CONFIG_BT_CTLR_CSN_GPIOTE_CHAN);
|
task = nrf_gpiote_clr_task_get(HAL_CSN_GPIOTE_CHAN);
|
||||||
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_FEM_PPI);
|
nrf_gpiote_subscribe_set(NRF_GPIOTE, task, HAL_DISABLE_FEM_PPI);
|
||||||
#endif /* !CONFIG_BT_CTLR_GPIO_CSN_POL_INV */
|
#endif /* !CONFIG_BT_CTLR_GPIO_CSN_POL_INV */
|
||||||
}
|
}
|
||||||
|
|
|
@ -262,8 +262,6 @@ static inline void hal_trigger_rateoverride_ppi_config(void)
|
||||||
#endif /* CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
|
#endif /* CONFIG_HAS_HW_NRF_RADIO_BLE_CODED */
|
||||||
|
|
||||||
/******************************************************************************/
|
/******************************************************************************/
|
||||||
#if defined(CONFIG_BT_CTLR_GPIO_PA_PIN) || defined(CONFIG_BT_CTLR_GPIO_LNA_PIN)
|
|
||||||
|
|
||||||
#define HAL_ENABLE_PALNA_PPI 15
|
#define HAL_ENABLE_PALNA_PPI 15
|
||||||
#define HAL_DISABLE_PALNA_PPI 16
|
#define HAL_DISABLE_PALNA_PPI 16
|
||||||
|
|
||||||
|
@ -273,18 +271,14 @@ static inline void hal_palna_ppi_setup(void)
|
||||||
NRF_PPI,
|
NRF_PPI,
|
||||||
HAL_ENABLE_PALNA_PPI,
|
HAL_ENABLE_PALNA_PPI,
|
||||||
(uint32_t)&(EVENT_TIMER->EVENTS_COMPARE[2]),
|
(uint32_t)&(EVENT_TIMER->EVENTS_COMPARE[2]),
|
||||||
(uint32_t)&(NRF_GPIOTE->TASKS_OUT[
|
(uint32_t)&(NRF_GPIOTE->TASKS_OUT[HAL_PALNA_GPIOTE_CHAN]));
|
||||||
CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN]));
|
|
||||||
nrf_ppi_channel_endpoint_setup(
|
nrf_ppi_channel_endpoint_setup(
|
||||||
NRF_PPI,
|
NRF_PPI,
|
||||||
HAL_DISABLE_PALNA_PPI,
|
HAL_DISABLE_PALNA_PPI,
|
||||||
(uint32_t)&(NRF_RADIO->EVENTS_DISABLED),
|
(uint32_t)&(NRF_RADIO->EVENTS_DISABLED),
|
||||||
(uint32_t)&(NRF_GPIOTE->TASKS_OUT[
|
(uint32_t)&(NRF_GPIOTE->TASKS_OUT[HAL_PALNA_GPIOTE_CHAN]));
|
||||||
CONFIG_BT_CTLR_PA_LNA_GPIOTE_CHAN]));
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* CONFIG_BT_CTLR_GPIO_PA_PIN || CONFIG_BT_CTLR_GPIO_LNA_PIN */
|
|
||||||
|
|
||||||
/******************************************************************************/
|
/******************************************************************************/
|
||||||
#if defined(CONFIG_BT_CTLR_FEM_NRF21540)
|
#if defined(CONFIG_BT_CTLR_FEM_NRF21540)
|
||||||
static inline void hal_pa_ppi_setup(void)
|
static inline void hal_pa_ppi_setup(void)
|
||||||
|
@ -306,18 +300,14 @@ static inline void hal_fem_ppi_setup(void)
|
||||||
NRF_PPI,
|
NRF_PPI,
|
||||||
HAL_ENABLE_FEM_PPI,
|
HAL_ENABLE_FEM_PPI,
|
||||||
(uint32_t)&(EVENT_TIMER->EVENTS_COMPARE[3]),
|
(uint32_t)&(EVENT_TIMER->EVENTS_COMPARE[3]),
|
||||||
(uint32_t)&(NRF_GPIOTE->TASKS_OUT[
|
(uint32_t)&(NRF_GPIOTE->TASKS_OUT[HAL_PDN_GPIOTE_CHAN]),
|
||||||
CONFIG_BT_CTLR_PDN_GPIOTE_CHAN]),
|
(uint32_t)&(NRF_GPIOTE->TASKS_OUT[HAL_CSN_GPIOTE_CHAN]));
|
||||||
(uint32_t)&(NRF_GPIOTE->TASKS_OUT[
|
|
||||||
CONFIG_BT_CTLR_CSN_GPIOTE_CHAN]));
|
|
||||||
nrf_ppi_channel_and_fork_endpoint_setup(
|
nrf_ppi_channel_and_fork_endpoint_setup(
|
||||||
NRF_PPI,
|
NRF_PPI,
|
||||||
HAL_DISABLE_FEM_PPI,
|
HAL_DISABLE_FEM_PPI,
|
||||||
(uint32_t)&(NRF_RADIO->EVENTS_DISABLED),
|
(uint32_t)&(NRF_RADIO->EVENTS_DISABLED),
|
||||||
(uint32_t)&(NRF_GPIOTE->TASKS_OUT[
|
(uint32_t)&(NRF_GPIOTE->TASKS_OUT[HAL_PDN_GPIOTE_CHAN]),
|
||||||
CONFIG_BT_CTLR_PDN_GPIOTE_CHAN]),
|
(uint32_t)&(NRF_GPIOTE->TASKS_OUT[HAL_CSN_GPIOTE_CHAN]));
|
||||||
(uint32_t)&(NRF_GPIOTE->TASKS_OUT[
|
|
||||||
CONFIG_BT_CTLR_CSN_GPIOTE_CHAN]));
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* CONFIG_BT_CTLR_FEM_NRF21540 */
|
#endif /* CONFIG_BT_CTLR_FEM_NRF21540 */
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue