boards: arm: zybo: add board definition for the Digilent Zybo

Add board definition for the Xilinx Zynq-7000-based Digilent Zybo.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>

boards/arm/zybo/Kconfig.board

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+# Digilent Zybo board configuration
+
+# Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_ZYBO
+	bool "Digilent Zybo"
+	depends on SOC_XILINX_XC7Z010

boards/arm/zybo/Kconfig.defconfig

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+# Digilent Zybo board
+
+# Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk>
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_ZYBO
+
+config BOARD
+	default "zybo"
+
+config UART_XLNX_PS
+	default y
+	depends on SERIAL
+
+endif # BOARD_ZYBO

boards/arm/zybo/board.cmake

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+# Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk>
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(openocd "--use-elf" "--cmd-reset-halt" "halt")
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

boards/arm/zybo/doc/index.rst

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+.. _zybo:
+
+Digilent Zybo
+#############
+
+Overview
+********
+
+The `Digilent Zybo`_ (ZYnq BOard) is a feature-rich, ready-to-use embedded software and digital
+circuit development board. It is built around the Xilinx Zynq-7000 family, which is based on the
+Xilinx All Programmable System-on-Chip (AP SoC) architecture. This architecture tightly integrates a
+dual-core ARM Cortex-A9 processor with Xilinx 7-series Field Programmable Gate Array (FPGA) logic.
+
+.. figure:: ./zybo-0.png
+   :width: 600px
+   :align: center
+   :alt: Digilent Zybo
+
+   Digilent (Credit: Digilent)
+
+Hardware
+********
+
+Supported Features
+==================
+
+The zybo board configuration supports the following hardware features:
+
++------------+------------+-------------------------------------+
+| Interface  | Controller | Driver/Component                    |
++============+============+=====================================+
+| GICv1      | on-chip    | ARM generic interrupt controller v1 |
++------------+------------+-------------------------------------+
+| ARCH TIMER | on-chip    | ARM architected timer               |
++------------+------------+-------------------------------------+
+| PINCTRL    | on-chip    | pinctrl                             |
++------------+------------+-------------------------------------+
+| GPIO       | on-chip    | gpio                                |
++------------+------------+-------------------------------------+
+| UART       | on-chip    | serial port-polling;                |
+|            |            | serial port-interrupt               |
++------------+------------+-------------------------------------+
+
+The default configuration can be found in the defconfig file:
+``boards/arm/zybo/zybo_defconfig``.
+
+Other hardware features are not currently supported by the port.
+
+Programming and Debugging
+*************************
+
+The Zynq-7000 series SoC needs to be initialized prior to running a Zephyr application. This can be
+achieved in a number of ways (e.g. using the Xilinx First Stage Boot Loader (FSBL), the Xilinx
+Vivado generated ``ps_init.tcl`` JTAG script, Das U-Boot Secondary Program Loader (SPL), ...).
+
+The instructions here use the U-Boot SPL. For further details and instructions for using Das U-Boot
+with Xilinx Zynq-7000 series SoCs, see the following documentation:
+
+- `Das U-Boot Website`_
+- `Using Distro Boot With Xilinx U-Boot`_
+
+Building Das U-Boot
+===================
+
+Clone and build Das U-Boot for the Digilent Zybo:
+
+.. code-block:: console
+
+   git clone -b v2022.04 https://source.denx.de/u-boot/u-boot.git
+   cd u-boot
+   make distclean
+   make xilinx_zynq_virt_defconfig
+   export PATH=/path/to/zephyr-sdk/arm-zephyr-eabi/bin/:$PATH
+   export CROSS_COMPILE=arm-zephyr-eabi-
+   export DEVICE_TREE="zynq-zybo"
+   make
+
+Flashing
+========
+
+Here is an example for running the :ref:`hello_world` application via JTAG.
+
+Ensure the board is configured for JTAG boot, open a serial terminal, turn on/reset the board (press
+the ``PS-SRST`` button), and initialize the Zynq-7000 series SoC by uploading and running the U-Boot
+SPL via JTAG.
+
+Next, upload and run the Zephyr application:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: zybo
+   :goals: flash
+
+You should see the following message in the terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS vx.xx.x-xxx-gxxxxxxxxxxxx ***
+   Hello World! zybo
+
+Another option is to load and run the :ref:`hello_world` application via U-Boot. Copy
+``u-boot/spl/boot.bin``, ``u-boot/u-boot.img``, and ``zephyr/zephyr.bin`` to a FAT32 formatted
+microSD card, insert the card in the ``SD MICRO`` slot on the Zybo board, ensure the board is
+configured for ``SD`` boot, and turn on the board.
+
+Once U-boot is done initializing, load an run the Zephyr application:
+
+.. code-block:: console
+
+   Zynq> fatload mmc 0 0x0 zephyr.bin
+   817120 bytes read in 56 ms (13.9 MiB/s)
+   Zynq> go 0x0
+   ## Starting application at 0x00000000 ...
+   *** Booting Zephyr OS vx.xx.x-xxx-gxxxxxxxxxxxx ***
+   Hello World! zybo
+
+Debugging
+=========
+
+Here is an example for the :ref:`hello_world` application.
+
+Ensure the board is configured for JTAG boot, open a serial terminal, turn on/reset the board (press
+the ``PS-SRST`` button), and initialize the Zynq-7000 series SoC by uploading and running the U-Boot
+SPL via JTAG.
+
+Next, upload and debug the Zephyr application:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: zybo
+   :goals: debug
+
+Step through the application in your debugger, and you should see the following message in the
+terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***
+   Hello World! zybo
+
+.. _Digilent Zybo:
+   https://digilent.com/reference/programmable-logic/zybo/start
+
+.. _Das U-Boot Website:
+   https://www.denx.de/wiki/U-Boot
+
+.. _Using Distro Boot With Xilinx U-Boot:
+   https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/749142017/Using+Distro+Boot+With+Xilinx+U-Boot

boards/arm/zybo/support/openocd.cfg

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+source [find interface/ftdi/digilent-hs1.cfg]
+transport select jtag
+source [find target/zynq_7000.cfg]

boards/arm/zybo/zybo-pinctrl.dtsi

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+/*
+ * Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/pinctrl-zynq.h>
+
+&pinctrl0 {
+	pinctrl_uart1_default: uart1-default {
+		mux {
+			groups = "uart1_10_grp";
+			function = "uart1";
+		};
+
+		conf {
+			groups = "uart1_10_grp";
+			slew-rate = <IO_SPEED_SLOW>;
+			power-source = <IO_STANDARD_LVCMOS18>;
+		};
+
+		conf-rx {
+			pins = "MIO49";
+			bias-high-impedance;
+		};
+
+		conf-tx {
+			pins = "MIO48";
+			bias-disable;
+		};
+	};
+};

boards/arm/zybo/zybo.dts

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+/*
+ * Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <xilinx/zynq7000.dtsi>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+#include "zybo-pinctrl.dtsi"
+
+/ {
+	model = "Digilent Zybo board";
+	compatible = "digilent,zynq-zybo", "xlnx,zynq-7000";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,ocm = &ocm_high;
+	};
+
+	aliases {
+		led0 = &ld_mio;
+		sw0 = &btn4;
+		sw1 = &btn5;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <1>;
+		};
+	};
+
+	sram0: memory@0 {
+		compatible = "mmio-sram";
+		reg = <0x00000000 DT_SIZE_M(512)>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		ld_mio: led_mio {
+			gpios = <&psgpio_bank0 7 GPIO_ACTIVE_HIGH>;
+			label = "LD_MIO";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		btn4: btn4 {
+			gpios = <&psgpio_bank1 18 GPIO_ACTIVE_LOW>;
+			label = "BTN4";
+		};
+		btn5: btn5 {
+			gpios = <&psgpio_bank1 19 GPIO_ACTIVE_LOW>;
+			label = "BTN5";
+		};
+	};
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	clock-frequency = <100000000>;
+	pinctrl-0 = <&pinctrl_uart1_default>;
+	pinctrl-names = "default";
+};
+
+&psgpio {
+	status = "okay";
+};

boards/arm/zybo/zybo.yaml

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+# Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk>
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: zybo
+name: Digilent Zybo
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
+ram: 524288
+supported:
+  - gpio

boards/arm/zybo/zybo_defconfig

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+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_SERIES_XILINX_XC7ZXXX=y
+CONFIG_SOC_XILINX_XC7Z010=y
+CONFIG_BOARD_ZYBO=y
+
+# The GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=325000000
+
+CONFIG_PINCTRL=y
+CONFIG_SERIAL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y