From c86073cf6b2d7fc602a2ed1c25e6ae9a7c65be84 Mon Sep 17 00:00:00 2001 From: Ioannis Glaropoulos Date: Tue, 15 Oct 2019 19:45:33 +0200 Subject: [PATCH] arch: arm: error: fix ARMv6-M assembly for Z_ARCH_EXCEPT As we are allowed to pass any integer value as as software fatal exception reason, we need to fix the inline assembly for ARMv6-M, to accept large immediate offsets. We do this by changing the way we write the exception reason to R0. Signed-off-by: Ioannis Glaropoulos --- include/arch/arm/error.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/include/arch/arm/error.h b/include/arch/arm/error.h index 35a66eabbe8..f57597b3636 100644 --- a/include/arch/arm/error.h +++ b/include/arch/arm/error.h @@ -31,13 +31,14 @@ extern "C" { * schedule a new thread until they are unlocked which is not what we want. * Force them unlocked as well. */ -#define Z_ARCH_EXCEPT(reason_p) do { \ +#define Z_ARCH_EXCEPT(reason_p) \ +register u32_t r0 __asm__("r0") = reason_p; \ +do { \ __asm__ volatile ( \ "cpsie i\n\t" \ - "movs r0, %[reason]\n\t" \ "svc %[id]\n\t" \ : \ - : [reason] "i" (reason_p), [id] "i" (_SVC_CALL_RUNTIME_EXCEPT) \ + : "r" (r0), [id] "i" (_SVC_CALL_RUNTIME_EXCEPT) \ : "memory"); \ CODE_UNREACHABLE; \ } while (false)