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boards: renesas: Add SPI support for Renesas RA6, RA4, RA2

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- Add SPI support for ek_ra6m1, ek_ra6m2, ek_ra6m3, ek_ra6m4,
ek_ra6m5, ek_ra6e2, fpb_ra6e1, fpb_ra6e2, ek_ra4e2, ek_ra4m2,
ek_ra4m3, ek_ra4w1, ek_ra2a1

- Add SPI support doc for these board

Signed-off-by: Tri Nguyen <tri.nguyen.wj@bp.renesas.com>
Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
This commit is contained in:
Khoa Nguyen 2024-11-19 13:48:59 +07:00 • committed by Benjamin Cabé
commit c8077e3552
39 changed files with 239 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

2
boards/renesas/ek_ra2a1/doc/index.rst
View file

@ -78,6 +78,8 @@ hardware features:
+-----------+------------+-------------------------------+
| UART | on-chip | uart |
+-----------+------------+-------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------+
The default configuration can be found in
:zephyr_file:`boards/renesas/ek_ra2a1/ek_ra2a1_defconfig`

10
boards/renesas/ek_ra2a1/ek_ra2a1-pinctrl.dtsi
View file

@ -16,4 +16,14 @@
drive-strength = "medium";
};
};
spi1_default: spi1_default {
group1 {
/* MISO MOSI RSPCK SSL */
psels = <RA_PSEL(RA_PSEL_SPI, 1, 4)>,
<RA_PSEL(RA_PSEL_SPI, 1, 5)>,
<RA_PSEL(RA_PSEL_SPI, 1, 3)>,
<RA_PSEL(RA_PSEL_SPI, 1, 2)>;
};
};
};

11
boards/renesas/ek_ra2a1/ek_ra2a1.dts
View file

@ -58,3 +58,14 @@
status = "okay";
};
};
&spi1 {
pinctrl-0 = <&spi1_default>;
pinctrl-names = "default";
cs-gpios = <&ioport1 2 GPIO_ACTIVE_LOW>;
status = "okay";
};
&ioport1 {
status = "okay";
};

2
boards/renesas/ek_ra4e2/doc/index.rst
View file

@ -98,6 +98,8 @@ The below features are currently supported on Zephyr OS for EK-RA4E2 board:
+-----------+------------+----------------------+
| CLOCK | on-chip | clock control |
+-----------+------------+----------------------+
| SPI | on-chip | spi |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port.

10
boards/renesas/ek_ra4e2/ek_ra4e2-pinctrl.dtsi
View file

@ -11,4 +11,14 @@
<RA_PSEL(RA_PSEL_SCI_0, 4, 10)>;
};
};
spi0_default: spi0_default {
group1 {
/* MISO MOSI RSPCK SSL */
psels = <RA_PSEL(RA_PSEL_SPI, 2, 6)>,
<RA_PSEL(RA_PSEL_SPI, 2, 7)>,
<RA_PSEL(RA_PSEL_SPI, 3, 2)>,
<RA_PSEL(RA_PSEL_SPI, 3, 1)>;
};
};
};

6
boards/renesas/ek_ra4e2/ek_ra4e2.dts
View file

@ -76,3 +76,9 @@
&ioport2 {
status = "okay";
};
&spi0 {
pinctrl-0 = <&spi0_default>;
pinctrl-names = "default";
status = "okay";
};

2
boards/renesas/ek_ra4m2/doc/index.rst
View file

@ -98,6 +98,8 @@ The below features are currently supported on Zephyr OS for EK-RA4M2 board:
+-----------+------------+----------------------+
| CLOCK | on-chip | clock control |
+-----------+------------+----------------------+
| SPI | on-chip | spi |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port.

10
boards/renesas/ek_ra4m2/ek_ra4m2-pinctrl.dtsi
View file

@ -11,4 +11,14 @@
<RA_PSEL(RA_PSEL_SCI_0, 4, 10)>;
};
};
spi0_default: spi0_default {
group1 {
/* MISO MOSI RSPCK SSL */
psels = <RA_PSEL(RA_PSEL_SPI, 1, 10)>,
<RA_PSEL(RA_PSEL_SPI, 1, 9)>,
<RA_PSEL(RA_PSEL_SPI, 1, 11)>,
<RA_PSEL(RA_PSEL_SPI, 3, 0)>;
};
};
};

6
boards/renesas/ek_ra4m2/ek_ra4m2.dts
View file

@ -72,3 +72,9 @@
&ioport4 {
status = "okay";
};
&spi0 {
pinctrl-0 = <&spi0_default>;
pinctrl-names = "default";
status = "okay";
};

2
boards/renesas/ek_ra4m3/doc/index.rst
View file

@ -100,6 +100,8 @@ The below features are currently supported on Zephyr OS for EK-RA4M3 board:
+-----------+------------+----------------------+
| CLOCK | on-chip | clock control |
+-----------+------------+----------------------+
| SPI | on-chip | spi |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port.

10
boards/renesas/ek_ra4m3/ek_ra4m3-pinctrl.dtsi
View file

@ -11,4 +11,14 @@
<RA_PSEL(RA_PSEL_SCI_0, 4, 10)>;
};
};
spi0_default: spi0_default {
group1 {
/* MISO MOSI RSPCK SSL */
psels = <RA_PSEL(RA_PSEL_SPI, 7, 0)>,
<RA_PSEL(RA_PSEL_SPI, 7, 1)>,
<RA_PSEL(RA_PSEL_SPI, 7, 2)>,
<RA_PSEL(RA_PSEL_SPI, 7, 3)>;
};
};
};

6
boards/renesas/ek_ra4m3/ek_ra4m3.dts
View file

@ -72,3 +72,9 @@
&ioport4 {
status = "okay";
};
&spi0 {
pinctrl-0 = <&spi0_default>;
pinctrl-names = "default";
status = "okay";
};

2
boards/renesas/ek_ra4w1/doc/index.rst
View file

@ -90,6 +90,8 @@ The below features are currently supported on Zephyr OS for EK-RA4W1 board:
+-----------+------------+----------------------+
| CLOCK | on-chip | clock control |
+-----------+------------+----------------------+
| SPI | on-chip | spi |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port.

10
boards/renesas/ek_ra4w1/ek_ra4w1-pinctrl.dtsi
View file

@ -11,4 +11,14 @@
<RA_PSEL(RA_PSEL_SCI_0, 1, 0)>;
};
};
spi1_default: spi1_default {
group1 {
/* MISO MOSI RSPCK SSL */
psels = <RA_PSEL(RA_PSEL_SPI, 1, 10)>,
<RA_PSEL(RA_PSEL_SPI, 1, 9)>,
<RA_PSEL(RA_PSEL_SPI, 1, 11)>,
<RA_PSEL(RA_PSEL_SPI, 1, 12)>;
};
};
};

6
boards/renesas/ek_ra4w1/ek_ra4w1.dts
View file

@ -59,3 +59,9 @@
&ioport4 {
status = "okay";
};
&spi1 {
pinctrl-0 = <&spi1_default>;
pinctrl-names = "default";
status = "okay";
};

2
boards/renesas/ek_ra6e2/doc/index.rst
View file

@ -98,6 +98,8 @@ The below features are currently supported on Zephyr OS for EK-RA6E2 board:
+-----------+------------+----------------------+
| CLOCK | on-chip | clock control |
+-----------+------------+----------------------+
| SPI | on-chip | spi |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port.

10
boards/renesas/ek_ra6e2/ek_ra6e2-pinctrl.dtsi
View file

@ -11,4 +11,14 @@
<RA_PSEL(RA_PSEL_SCI_0, 4, 10)>;
};
};
spi0_default: spi0_default {
group1 {
/* MISO MOSI RSPCK SSL */
psels = <RA_PSEL(RA_PSEL_SPI, 1, 10)>,
<RA_PSEL(RA_PSEL_SPI, 1, 9)>,
<RA_PSEL(RA_PSEL_SPI, 1, 11)>,
<RA_PSEL(RA_PSEL_SPI, 3, 1)>;
};
};
};

6
boards/renesas/ek_ra6e2/ek_ra6e2.dts
View file

@ -56,6 +56,12 @@
status = "okay";
};
&spi0 {
pinctrl-0 = <&spi0_default>;
pinctrl-names = "default";
status = "okay";
};
&ioport2 {
status = "okay";
};

2
boards/renesas/ek_ra6m1/doc/index.rst
View file

@ -96,6 +96,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M1 board:
+-----------+------------+----------------------+
| I2C | on-chip | i2c |
+-----------+------------+----------------------+
| SPI | on-chip | spi |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port.

10
boards/renesas/ek_ra6m1/ek_ra6m1-pinctrl.dtsi
View file

@ -20,4 +20,14 @@
drive-strength = "medium";
};
};
spi0_default: spi0_default {
group1 {
/* MISO MOSI RSPCK SSL */
psels = <RA_PSEL(RA_PSEL_SPI, 4, 10)>,
<RA_PSEL(RA_PSEL_SPI, 4, 11)>,
<RA_PSEL(RA_PSEL_SPI, 4, 12)>,
<RA_PSEL(RA_PSEL_SPI, 4, 13)>;
};
};
};

6
boards/renesas/ek_ra6m1/ek_ra6m1.dts
View file

@ -55,6 +55,12 @@
pinctrl-names = "default";
};
&spi0 {
pinctrl-0 = <&spi0_default>;
pinctrl-names = "default";
status = "okay";
};
&ioport1 {
status = "okay";
};

2
boards/renesas/ek_ra6m2/doc/index.rst
View file

@ -90,6 +90,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M2 board:
+-----------+------------+----------------------+
| I2C | on-chip | i2c |
+-----------+------------+----------------------+
| SPI | on-chip | spi |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port.

10
boards/renesas/ek_ra6m2/ek_ra6m2-pinctrl.dtsi
View file

@ -20,4 +20,14 @@
drive-strength = "medium";
};
};
spi0_default: spi0_default {
group1 {
/* MISO MOSI RSPCK SSL */
psels = <RA_PSEL(RA_PSEL_SPI, 4, 10)>,
<RA_PSEL(RA_PSEL_SPI, 4, 11)>,
<RA_PSEL(RA_PSEL_SPI, 4, 12)>,
<RA_PSEL(RA_PSEL_SPI, 4, 13)>;
};
};
};

6
boards/renesas/ek_ra6m2/ek_ra6m2.dts
View file

@ -55,6 +55,12 @@
pinctrl-names = "default";
};
&spi0 {
pinctrl-0 = <&spi0_default>;
pinctrl-names = "default";
status = "okay";
};
&ioport1 {
status = "okay";
};

2
boards/renesas/ek_ra6m3/doc/index.rst
View file

@ -98,6 +98,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M3 board:
+-----------+------------+----------------------+
| I2C | on-chip | i2c |
+-----------+------------+----------------------+
| SPI | on-chip | spi |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port.

10
boards/renesas/ek_ra6m3/ek_ra6m3-pinctrl.dtsi
View file

@ -20,4 +20,14 @@
drive-strength = "medium";
};
};
spi0_default: spi0_default {
group1 {
/* MISO MOSI RSPCK SSL */
psels = <RA_PSEL(RA_PSEL_SPI, 4, 10)>,
<RA_PSEL(RA_PSEL_SPI, 4, 11)>,
<RA_PSEL(RA_PSEL_SPI, 4, 12)>,
<RA_PSEL(RA_PSEL_SPI, 4, 14)>;
};
};
};

6
boards/renesas/ek_ra6m3/ek_ra6m3.dts
View file

@ -42,6 +42,12 @@
};
};
&spi0 {
pinctrl-0 = <&spi0_default>;
pinctrl-names = "default";
status = "okay";
};
&ioport1 {
status = "okay";
};

2
boards/renesas/ek_ra6m4/doc/index.rst
View file

@ -103,6 +103,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M4 board:
+-----------+------------+----------------------+
| I2C | on-chip | i2c |
+-----------+------------+----------------------+
| SPI | on-chip | spi |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port.

10
boards/renesas/ek_ra6m4/ek_ra6m4-pinctrl.dtsi
View file

@ -20,4 +20,14 @@
drive-strength = "medium";
};
};
spi0_default: spi0_default {
group1 {
/* MISO MOSI RSPCK SSL */
psels = <RA_PSEL(RA_PSEL_SPI, 2, 2)>,
<RA_PSEL(RA_PSEL_SPI, 2, 3)>,
<RA_PSEL(RA_PSEL_SPI, 2, 4)>,
<RA_PSEL(RA_PSEL_SPI, 2, 5)>;
};
};
};

6
boards/renesas/ek_ra6m4/ek_ra6m4.dts
View file

@ -63,6 +63,12 @@
pinctrl-names = "default";
};
&spi0 {
pinctrl-0 = <&spi0_default>;
pinctrl-names = "default";
status = "okay";
};
&ioport4 {
status = "okay";
};

2
boards/renesas/ek_ra6m5/doc/index.rst
View file

@ -101,6 +101,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M5 board:
+-----------+------------+----------------------+
| I2C | on-chip | i2c |
+-----------+------------+----------------------+
| SPI | on-chip | spi |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port.

10
boards/renesas/ek_ra6m5/ek_ra6m5-pinctrl.dtsi
View file

@ -20,4 +20,14 @@
drive-strength = "medium";
};
};
spi0_default: spi0_default {
group1 {
/* MISO MOSI RSPCK SSL */
psels = <RA_PSEL(RA_PSEL_SPI, 2, 2)>,
<RA_PSEL(RA_PSEL_SPI, 2, 3)>,
<RA_PSEL(RA_PSEL_SPI, 2, 4)>,
<RA_PSEL(RA_PSEL_SPI, 2, 5)>;
};
};
};

6
boards/renesas/ek_ra6m5/ek_ra6m5.dts
View file

@ -63,6 +63,12 @@
pinctrl-names = "default";
};
&spi0 {
pinctrl-0 = <&spi0_default>;
pinctrl-names = "default";
status = "okay";
};
&ioport0 {
status = "okay";
};

2
boards/renesas/fpb_ra6e1/doc/index.rst
View file

@ -85,6 +85,8 @@ The below features are currently supported on Zephyr OS for FPB-RA6E1 board:
+-----------+------------+----------------------+
| I2C | on-chip | i2c |
+-----------+------------+----------------------+
| SPI | on-chip | spi |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port.

10
boards/renesas/fpb_ra6e1/fpb_ra6e1-pinctrl.dtsi
View file

@ -20,4 +20,14 @@
drive-strength = "medium";
};
};
spi1_default: spi1_default {
group1 {
/* MISO MOSI RSPCK SSL */
psels = <RA_PSEL(RA_PSEL_SPI, 4, 10)>,
<RA_PSEL(RA_PSEL_SPI, 4, 11)>,
<RA_PSEL(RA_PSEL_SPI, 4, 12)>,
<RA_PSEL(RA_PSEL_SPI, 4, 13)>;
};
};
};

6
boards/renesas/fpb_ra6e1/fpb_ra6e1.dts
View file

@ -59,6 +59,12 @@
pinctrl-names = "default";
};
&spi1 {
pinctrl-0 = <&spi1_default>;
pinctrl-names = "default";
status = "okay";
};
&ioport4 {
status = "okay";
};

2
boards/renesas/fpb_ra6e2/doc/index.rst
View file

@ -85,6 +85,8 @@ The below features are currently supported on Zephyr OS for FPB-RA6E2 board:
+-----------+------------+----------------------+
| UART | on-chip | serial |
+-----------+------------+----------------------+
| SPI | on-chip | spi |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port.

10
boards/renesas/fpb_ra6e2/fpb_ra6e2-pinctrl.dtsi
View file

@ -11,4 +11,14 @@
<RA_PSEL(RA_PSEL_SCI_0, 4, 10)>;
};
};
spi0_default: spi0_default {
group1 {
/* MISO MOSI RSPCK SSL */
psels = <RA_PSEL(RA_PSEL_SPI, 1, 10)>,
<RA_PSEL(RA_PSEL_SPI, 1, 9)>,
<RA_PSEL(RA_PSEL_SPI, 1, 11)>,
<RA_PSEL(RA_PSEL_SPI, 3, 1)>;
};
};
};

6
boards/renesas/fpb_ra6e2/fpb_ra6e2.dts
View file

@ -49,6 +49,12 @@
};
};
&spi0 {
pinctrl-0 = <&spi0_default>;
pinctrl-names = "default";
status = "okay";
};
&ioport2 {
status = "okay";
};