From c7ed7e492b51b4afce365290ea9db0e80f483ef9 Mon Sep 17 00:00:00 2001
From: Daniel Leung <daniel.leung@intel.com>
Date: Mon, 5 Oct 2020 10:15:00 -0700
Subject: [PATCH] xtensa: intel_s1000: enable thread local storage

Adds the bits to enable thread local storage for
intel_s1000 SoC.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
---
 soc/xtensa/intel_s1000/Kconfig.soc | 1 +
 soc/xtensa/intel_s1000/linker.ld   | 1 +
 2 files changed, 2 insertions(+)

diff --git a/soc/xtensa/intel_s1000/Kconfig.soc b/soc/xtensa/intel_s1000/Kconfig.soc
index b40a3a56f6d..4fab35bcb00 100644
--- a/soc/xtensa/intel_s1000/Kconfig.soc
+++ b/soc/xtensa/intel_s1000/Kconfig.soc
@@ -7,3 +7,4 @@ config SOC_INTEL_S1000
 	select XTENSA_HAL if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc"
 	select HAS_I2C_DW if I2C
 	select HAS_SPI_DW if SPI
+	select ARCH_HAS_THREAD_LOCAL_STORAGE
diff --git a/soc/xtensa/intel_s1000/linker.ld b/soc/xtensa/intel_s1000/linker.ld
index 9e4ac873a46..f68d98867c6 100644
--- a/soc/xtensa/intel_s1000/linker.ld
+++ b/soc/xtensa/intel_s1000/linker.ld
@@ -355,6 +355,7 @@ SECTIONS
     _etext = .;
   } >ram :ram_phdr
 #include <linker/common-rom.ld>
+#include <linker/thread-local-storage.ld>
 
   .noinit :  ALIGN(4)
   {