soc: ti: k3: add AM2434 support

Add SoC support and device trees for Texas Instruments AM2434 SoC. Both R5
and M4 cores are supported here.

Signed-off-by: Amneesh Singh <a-singh7@ti.com>

dts/arm/ti/am64x_m4.dtsi

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2024 PHYTEC Messtechnik GmbH
+ * Copyright (c) 2025 Texas Instruments Incorporated
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,9 +8,9 @@
 #include <mem.h>
 #include <freq.h>
 #include <arm/armv7-m.dtsi>
-#include <zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h>
+
-#include <zephyr/dt-bindings/gpio/gpio.h>
+#include "am64x_main.dtsi"
-#include <zephyr/dt-bindings/i2c/i2c.h>
+#include "am64x_mcu.dtsi"
 
 / {
 
@@ -29,9 +30,9 @@
 		reg = <0x0 DT_SIZE_K(192)>;		/* 192 KB of SRAM (I-Code) */
 	};
 
-	sram1: memory1@40000 {
+	sram1: memory1@30000 {
 		compatible = "mmio-sram";
-		reg = <0x40000 DT_SIZE_K(64)>;		/* 64 KB of SRAM (D-Code) */
+		reg = <0x30000 DT_SIZE_K(64)>;		/* 64 KB of SRAM (D-Code) */
 	};
 
 	sysclk: system-clock {
@@ -39,72 +40,6 @@
 		clock-frequency = <DT_FREQ_M(400)>;
 		#clock-cells = <0>;
 	};
-
-	mbox6: mailbox@29060000 {
-		compatible = "ti,omap-mailbox";
-		reg = <0x29060000 0x200>;
-		interrupts = <56 4>;
-		interrupt-parent = <&nvic>;
-		usr-id = <3>;
-		#mbox-cells = <1>;
-	};
-
-	pinctrl: pinctrl@4084000 {
-		compatible = "ti,k3-pinctrl";
-		reg = <0x04084000 0x88>;
-		status = "okay";
-	};
-
-	uart0: serial@4a00000 {
-		compatible = "ns16550";
-		reg = <0x04a00000 0x200>;
-		interrupts = <24 4>;
-		interrupt-parent = <&nvic>;
-		clock-frequency = <DT_FREQ_M(96)>;
-		current-speed = <115200>;
-		reg-shift = <2>;
-		status = "disabled";
-	};
-
-	uart1: serial@4a10000 {
-		compatible = "ns16550";
-		reg = <0x04a10000 0x200>;
-		interrupts = <25 4>;
-		interrupt-parent = <&nvic>;
-		clock-frequency = <DT_FREQ_M(96)>;
-		current-speed = <115200>;
-		reg-shift = <2>;
-		status = "disabled";
-	};
-
-	i2c0: i2c@4900000 {
-		compatible = "ti,omap-i2c";
-		reg = <0x04900000 0x100>;
-		interrupts = <17 4>;
-		interrupt-parent = <&nvic>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	i2c1: i2c@4910000 {
-		compatible = "ti,omap-i2c";
-		reg = <0x04910000 0x100>;
-		interrupts = <18 4>;
-		interrupt-parent = <&nvic>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	gpio0: gpio@4201000 {
-		compatible = "ti,davinci-gpio";
-		reg = <0x4201000 0x100>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		ngpios = <24>;
-		status = "disabled";
-	};
 };
 
 &nvic {
@@ -114,3 +49,33 @@
 &systick {
 	status = "okay";
 };
+
+&mcu_uart0 {
+	interrupts = <24 4>;
+	interrupt-parent = <&nvic>;
+};
+
+&mcu_uart1 {
+	interrupts = <25 4>;
+	interrupt-parent = <&nvic>;
+};
+
+&mcu_i2c0 {
+	interrupts = <17 4>;
+	interrupt-parent = <&nvic>;
+};
+
+&mcu_i2c1 {
+	interrupts = <18 4>;
+	interrupt-parent = <&nvic>;
+};
+
+&mbox6 {
+	interrupts = <56 4>;
+	interrupt-parent = <&nvic>;
+};
+
+&mbox7 {
+	interrupts = <57 4>;
+	interrupt-parent = <&nvic>;
+};

dts/arm/ti/am64x_main.dtsi

@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2025 Texas Instruments Incorporated
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <freq.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	pinctrl: pinctrl@f4000 {
+		compatible = "ti,k3-pinctrl";
+		reg = <0xf4000 0x2ac>;
+		status = "disabled";
+	};
+
+	timer0: timer@2400000 {
+		compatible = "ti,am654-timer";
+		reg = <0x2400000 DT_SIZE_K(1)>;
+		status = "disabled";
+	};
+
+	timer1: timer@2410000 {
+		compatible = "ti,am654-timer";
+		reg = <0x2410000 DT_SIZE_K(1)>;
+		status = "disabled";
+	};
+
+	timer2: timer@2420000 {
+		compatible = "ti,am654-timer";
+		reg = <0x2420000 DT_SIZE_K(1)>;
+		status = "disabled";
+	};
+
+	timer3: timer@2430000 {
+		compatible = "ti,am654-timer";
+		reg = <0x2430000 DT_SIZE_K(1)>;
+		status = "disabled";
+	};
+
+	timer4: timer@2440000 {
+		compatible = "ti,am654-timer";
+		reg = <0x2440000 DT_SIZE_K(1)>;
+		status = "disabled";
+	};
+
+	timer5: timer@2450000 {
+		compatible = "ti,am654-timer";
+		reg = <0x2450000 DT_SIZE_K(1)>;
+		status = "disabled";
+	};
+
+	timer6: timer@2460000 {
+		compatible = "ti,am654-timer";
+		reg = <0x2460000 DT_SIZE_K(1)>;
+		status = "disabled";
+	};
+
+	timer7: timer@2470000 {
+		compatible = "ti,am654-timer";
+		reg = <0x2470000 DT_SIZE_K(1)>;
+		status = "disabled";
+	};
+
+	timer8: timer@2480000 {
+		compatible = "ti,am654-timer";
+		reg = <0x2480000 DT_SIZE_K(1)>;
+		status = "disabled";
+	};
+
+	timer9: timer@2490000 {
+		compatible = "ti,am654-timer";
+		reg = <0x2490000 DT_SIZE_K(1)>;
+		status = "disabled";
+	};
+
+	timer10: timer@24a0000 {
+		compatible = "ti,am654-timer";
+		reg = <0x24a0000 DT_SIZE_K(1)>;
+		status = "disabled";
+	};
+
+	timer11: timer@24b0000 {
+		compatible = "ti,am654-timer";
+		reg = <0x24b0000 DT_SIZE_K(1)>;
+		status = "disabled";
+	};
+
+	uart0: uart@2800000 {
+		compatible = "ns16550";
+		reg = <0x02800000 0x200>;
+		clock-frequency = <DT_FREQ_M(48)>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	uart1: uart@2810000 {
+		compatible = "ns16550";
+		reg = <0x02810000 0x200>;
+		clock-frequency = <DT_FREQ_M(48)>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	uart2: uart@2820000 {
+		compatible = "ns16550";
+		reg = <0x02820000 0x200>;
+		clock-frequency = <DT_FREQ_M(48)>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	uart3: uart@2830000 {
+		compatible = "ns16550";
+		reg = <0x02830000 0x200>;
+		clock-frequency = <DT_FREQ_M(48)>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	uart4: uart@2840000 {
+		compatible = "ns16550";
+		reg = <0x02840000 0x200>;
+		clock-frequency = <DT_FREQ_M(48)>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	uart5: uart@2850000 {
+		compatible = "ns16550";
+		reg = <0x02850000 0x200>;
+		clock-frequency = <DT_FREQ_M(48)>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	uart6: uart@2860000 {
+		compatible = "ns16550";
+		reg = <0x02860000 0x200>;
+		clock-frequency = <DT_FREQ_M(48)>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	i2c0: i2c0@20000000 {
+		compatible = "ti,omap-i2c";
+		reg = <0x20000000 0x100>;
+		clock-frequency = <DT_FREQ_K(100)>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c1: i2c0@20010000 {
+		compatible = "ti,omap-i2c";
+		reg = <0x20010000 0x100>;
+		clock-frequency = <DT_FREQ_K(100)>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c2: i2c0@20020000 {
+		compatible = "ti,omap-i2c";
+		reg = <0x20020000 0x100>;
+		clock-frequency = <DT_FREQ_K(100)>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c3: i2c0@20030000 {
+		compatible = "ti,omap-i2c";
+		reg = <0x20030000 0x100>;
+		clock-frequency = <DT_FREQ_K(100)>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	gpio0: gpio@600000 {
+		compatible = "ti,davinci-gpio";
+		reg = <0x600000 0x100>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		status = "disabled";
+	};
+
+	gpio1: gpio@601000 {
+		compatible = "ti,davinci-gpio";
+		reg = <0x601000 0x100>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		status = "disabled";
+	};
+
+	adc0: adc@28001000 {
+		compatible = "ti,am335x-adc";
+		reg = <0x28001000 DT_SIZE_K(1)>;
+		status = "disabled";
+		#io-channel-cells = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	/* users: r5f0_0, r5f0_1, r5f1_0, r5f1_1 */
+	mbox0: mailbox@29000000 {
+		compatible = "ti,omap-mailbox";
+		reg = <0x29000000 0x200>;
+		#mbox-cells = <1>;
+		status = "disabled";
+	};
+
+	/* users: r5f0_0, r5f0_1, r5f1_0, r5f1_1 */
+	mbox1: mailbox@29010000 {
+		compatible = "ti,omap-mailbox";
+		reg = <0x29010000 0x200>;
+		#mbox-cells = <1>;
+		status = "disabled";
+	};
+
+	/* users: r5f0_0, r5f0_1, a53 */
+	mbox2: mailbox@29020000 {
+		compatible = "ti,omap-mailbox";
+		reg = <0x29020000 0x200>;
+		#mbox-cells = <1>;
+		status = "disabled";
+	};
+
+	/* users: r5f0_0, r5f0_1, a53 */
+	mbox3: mailbox@29030000 {
+		compatible = "ti,omap-mailbox";
+		reg = <0x29030000 0x200>;
+		#mbox-cells = <1>;
+		status = "disabled";
+	};
+
+	/* users: r5f1_0, r5f1_1, a53 */
+	mbox4: mailbox@29040000 {
+		compatible = "ti,omap-mailbox";
+		reg = <0x29040000 0x200>;
+		#mbox-cells = <1>;
+		status = "disabled";
+	};
+
+	/* users: r5f1_0, r5f1_1, a53 */
+	mbox5: mailbox@29050000 {
+		compatible = "ti,omap-mailbox";
+		reg = <0x29050000 0x200>;
+		#mbox-cells = <1>;
+		status = "disabled";
+	};
+
+	/* users: r5f0_0, r5f0_1, a53, m4 */
+	mbox6: mailbox@29060000 {
+		compatible = "ti,omap-mailbox";
+		reg = <0x29060000 0x200>;
+		#mbox-cells = <1>;
+		status = "disabled";
+	};
+
+	/* users: r5f1_0, r5f1_1, a53, m4 */
+	mbox7: mailbox@29070000 {
+		compatible = "ti,omap-mailbox";
+		reg = <0x29070000 0x200>;
+		#mbox-cells = <1>;
+		status = "disabled";
+	};
+};

dts/arm/ti/am64x_mcu.dtsi

@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2025 Texas Instruments Incorporated
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <freq.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	mcu_pinctrl: pinctrl@4084000 {
+		compatible = "ti,k3-pinctrl";
+		reg = <0x04084000 0x88>;
+		status = "disabled";
+	};
+
+	mcu_uart0: serial@4a00000 {
+		compatible = "ns16550";
+		reg = <0x04a00000 0x200>;
+		clock-frequency = <DT_FREQ_M(48)>;
+		current-speed = <115200>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	mcu_uart1: serial@4a10000 {
+		compatible = "ns16550";
+		reg = <0x04a10000 0x200>;
+		clock-frequency = <DT_FREQ_M(48)>;
+		current-speed = <115200>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	mcu_i2c0: i2c0@4900000 {
+		compatible = "ti,omap-i2c";
+		reg = <0x4900000 0x100>;
+		clock-frequency = <DT_FREQ_K(100)>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	mcu_i2c1: i2c0@4910000 {
+		compatible = "ti,omap-i2c";
+		reg = <0x4910000 0x100>;
+		clock-frequency = <DT_FREQ_K(100)>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	mcu_gpio0: gpio@4201000 {
+		compatible = "ti,davinci-gpio";
+		reg = <0x4201000 0x100>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <23>;
+		status = "disabled";
+	};
+};

dts/arm/ti/am64x_r5.dtsi

@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2025 Texas Instruments Incorporated
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv7-r.dtsi>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+#include <zephyr/dt-bindings/interrupt-controller/ti-vim.h>
+#include "am64x_main.dtsi"
+#include "am64x_mcu.dtsi"
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r5";
+			reg = <0>;
+			clock-frequency = <DT_FREQ_M(800)>;
+		};
+	};
+
+	atcm: memory@0 {
+		device_type = "memory";
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x0 DT_SIZE_K(32)>;
+		zephyr,memory-region = "ATCM";
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
+	};
+
+	btcm: memory@41010000 {
+		device_type = "memory";
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x41010000 DT_SIZE_K(32)>;
+		zephyr,memory-region = "BTCM";
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
+	};
+
+	sram: memory@70080000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x70080000 DT_SIZE_K(256)>;
+		zephyr,memory-region = "SRAM";
+	};
+
+	vim: interrupt-controller@2fff0000 {
+		#address-cells = <1>;
+		compatible = "ti,vim";
+		reg = <0x2fff0000 0x4000>;
+		interrupt-controller;
+		#interrupt-cells = <4>; /* {IRQ/FIQ, IRQ_NUM, IRQ_TYPE, IRQ_PRIO} */
+	};
+};
+
+&timer0 {
+	interrupts = <0 152 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&timer1 {
+	interrupts = <0 153 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&timer2 {
+	interrupts = <0 154 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&timer3 {
+	interrupts = <0 155 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&timer4 {
+	interrupts = <0 156 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&timer5 {
+	interrupts = <0 157 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&timer6 {
+	interrupts = <0 158 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&timer7 {
+	interrupts = <0 159 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&timer8 {
+	interrupts = <0 160 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&timer9 {
+	interrupts = <0 161 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&timer10 {
+	interrupts = <0 162 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&timer11 {
+	interrupts = <0 163 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&uart0 {
+	interrupts = <0 210 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&uart1 {
+	interrupts = <0 211 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&uart2 {
+	interrupts = <0 212 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&uart3 {
+	interrupts = <0 213 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&uart4 {
+	interrupts = <0 214 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&uart5 {
+	interrupts = <0 215 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&uart6 {
+	interrupts = <0 216 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&i2c0 {
+	interrupts = <0 193 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&i2c1 {
+	interrupts = <0 194 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&i2c2 {
+	interrupts = <0 195 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&i2c3 {
+	interrupts = <0 196 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&mcu_uart0 {
+	interrupts = <0 217 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&mcu_uart1 {
+	interrupts = <0 218 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&mcu_i2c0 {
+	interrupts = <0 61 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&mcu_i2c1 {
+	interrupts = <0 62 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&adc0 {
+	interrupts = <0 128 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&mbox0 {
+	interrupts = <0 96 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&mbox1 {
+	interrupts = <0 97 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&mbox2 {
+	interrupts = <0 98 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&mbox3 {
+	interrupts = <0 99 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&mbox4 {
+	interrupts = <0 98 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&mbox5 {
+	interrupts = <0 99 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&mbox6 {
+	interrupts = <0 100 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};
+
+&mbox7 {
+	interrupts = <0 100 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	interrupt-parent = <&vim>;
+};

soc/ti/k3/am6x/CMakeLists.txt

@@ -21,6 +21,7 @@ elseif(CONFIG_SOC_SERIES_AM6X_M4)
   set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/m4/linker.ld CACHE INTERNAL "")
 elseif(CONFIG_SOC_SERIES_AM6X_R5)
   zephyr_sources(r5/soc.c)
+  zephyr_sources_ifdef(CONFIG_ARM_MPU r5/arm_mpu_regions.c)
 
   zephyr_include_directories(r5)
 

soc/ti/k3/am6x/Kconfig

@@ -33,6 +33,7 @@ config SOC_SERIES_AM6X_R5
 	select SOC_EARLY_INIT_HOOK
 
 config SOC_PART_NUMBER
+	default "AM2434" if SOC_AM2434_M4 || SOC_AM2434_R5F0_0
 	default "AM6232" if SOC_AM6232_A53
 	default "AM6232" if SOC_AM6232_M4
 	default "AM6234" if SOC_AM6234_A53

soc/ti/k3/am6x/Kconfig.soc

@@ -43,6 +43,14 @@ config SOC_AM6442_M4
 	bool
 	select SOC_SERIES_AM6X_M4
 
+config SOC_AM2434_M4
+	bool
+	select SOC_SERIES_AM6X_M4
+
+config SOC_AM2434_R5F0_0
+	bool
+	select SOC_SERIES_AM6X_R5
+
 config SOC_J721E_MAIN_R5F0_0
 	bool
 	select SOC_SERIES_AM6X_R5
@@ -59,6 +67,7 @@ config SOC_SERIES
 	default "am6x" if SOC_SERIES_AM6X
 
 config SOC
+	default "am2434" if SOC_AM2434_M4 || SOC_AM2434_R5F0_0
 	default "am6232" if SOC_AM6232_M4 || SOC_AM6232_A53
 	default "am6234" if SOC_AM6234_M4 || SOC_AM6234_A53
 	default "am6442" if SOC_AM6442_M4

soc/ti/k3/am6x/common/ctrl_partitions.c

@@ -17,19 +17,27 @@
 #define CTRL_PARTITION_SIZE        (0x4000)
 #define CTRL_PARTITION(base, part) ((base) + (part) * CTRL_PARTITION_SIZE)
 
-#if defined CONFIG_SOC_AM6442_M4
+#if defined CONFIG_SOC_AM6442_M4 || defined CONFIG_SOC_AM2434_M4
 #define MCU_PADCFG_BASE (0x4080000)
 #elif defined CONFIG_SOC_AM6234_M4 | defined CONFIG_SOC_AM6232_M4
 #define WKUP_PADCFG_BASE (0x4080000)
+#elif defined CONFIG_SOC_AM2434_R5F0_0
+#define MCU_PADCFG_BASE  (0x4080000)
+#define MAIN_PADCFG_BASE (0xf0000)
 #endif
 
 static const uintptr_t ctrl_partitions[] = {
-#if defined CONFIG_SOC_AM6442_M4
+#if defined CONFIG_SOC_AM6442_M4 || defined CONFIG_SOC_AM2434_M4
 	CTRL_PARTITION(MCU_PADCFG_BASE, 0),
 	CTRL_PARTITION(MCU_PADCFG_BASE, 1),
 #elif defined CONFIG_SOC_AM6234_M4 | defined CONFIG_SOC_AM6232_M4
 	CTRL_PARTITION(WKUP_PADCFG_BASE, 0),
 	CTRL_PARTITION(WKUP_PADCFG_BASE, 1),
+#elif defined CONFIG_SOC_AM2434_R5F0_0
+	CTRL_PARTITION(MAIN_PADCFG_BASE, 0),
+	CTRL_PARTITION(MAIN_PADCFG_BASE, 1),
+	CTRL_PARTITION(MCU_PADCFG_BASE, 0),
+	CTRL_PARTITION(MCU_PADCFG_BASE, 1),
 #endif
 };
 

soc/ti/k3/am6x/r5/arm_mpu_regions.c

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2025 Texas Instruments
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/kernel.h>
+#include <zephyr/arch/arm/mpu/arm_mpu.h>
+
+/* userspace threads require RO access to .text and .rodata */
+#ifdef CONFIG_USERSPACE
+#define PERM_Msk P_RW_U_RO_Msk
+#else
+#define PERM_Msk P_RW_U_NA_Msk
+#endif
+
+static const struct arm_mpu_region mpu_regions[] = {
+#if defined CONFIG_SOC_AM2434_R5F0_0
+	MPU_REGION_ENTRY("Device", 0x0, REGION_2G, {MPU_RASR_S_Msk | NOT_EXEC | PERM_Msk}),
+#endif
+
+	MPU_REGION_ENTRY(
+		"SRAM", CONFIG_SRAM_BASE_ADDRESS, REGION_SRAM_SIZE,
+		{NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE | PERM_Msk}),
+};
+
+const struct arm_mpu_config mpu_config = {
+	.num_regions = ARRAY_SIZE(mpu_regions),
+	.mpu_regions = mpu_regions,
+};

soc/ti/k3/soc.yml

@@ -14,6 +14,10 @@ family:
     - name: am6442
       cpuclusters:
       - name: m4
+    - name: am2434
+      cpuclusters:
+      - name: m4
+      - name: r5f0_0
     - name: j721e
       cpuclusters:
       - name: main_r5f0_0