boards: espressif: esp32c6: Add LP Core board support

Add ULP Coprocessor board support for C6.
This requires a change in the board qualifier depending on the build
target.
Update esp32c6 overlay and configuration files to the proper name.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>

boards/deprecated.cmake

@@ -22,6 +22,9 @@ set(arduino_uno_r4_minima_DEPRECATED
 set(arduino_uno_r4_wifi_DEPRECATED
     arduino_uno_r4@wifi
 )
+set(esp32c6_devkitc_DEPRECATED
+    esp32c6_devkitc/esp32c6/hpcore
+)
 set(qemu_xtensa_DEPRECATED
     qemu_xtensa/dc233c
 )

boards/espressif/esp32c6_devkitc/Kconfig

@@ -3,4 +3,5 @@
 
 config HEAP_MEM_POOL_ADD_SIZE_BOARD
 	int
-	default 4096
+	default 4096 if BOARD_ESP32C6_DEVKITC_ESP32C6_HPCORE
+	default 256 if BOARD_ESP32C6_DEVKITC_ESP32C6_LPCORE

boards/espressif/esp32c6_devkitc/Kconfig.esp32c6_devkitc

@@ -5,3 +5,5 @@
 
 config BOARD_ESP32C6_DEVKITC
 	select SOC_ESP32_C6_WROOM_1U_N8
+	select SOC_ESP32C6_HPCORE if BOARD_ESP32C6_DEVKITC_ESP32C6_HPCORE
+	select SOC_ESP32C6_LPCORE if BOARD_ESP32C6_DEVKITC_ESP32C6_LPCORE

boards/espressif/esp32c6_devkitc/doc/index.rst

@@ -147,7 +147,7 @@ To build the sample application using sysbuild use the command:
 .. zephyr-app-commands::
    :tool: west
    :zephyr-app: samples/hello_world
-   :board: esp32c6_devkitc
+   :board: esp32c6_devkitc/esp32c6/hpcore
    :goals: build
    :west-args: --sysbuild
    :compact:
@@ -196,7 +196,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: esp32c6_devkitc
+   :board: esp32c6_devkitc/esp32c6/hpcore
    :goals: build
 
 The usual ``flash`` target will work with the ``esp32c6_devkitc`` board
@@ -205,7 +205,7 @@ application.
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: esp32c6_devkitc
+   :board: esp32c6_devkitc/esp32c6/hpcore
    :goals: flash
 
 Open the serial monitor using the following command:
@@ -220,7 +220,7 @@ message in the monitor:
 .. code-block:: console
 
    ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
-   Hello World! esp32c6_devkitc
+   Hello World! esp32c6_devkitc/esp32c6/hpcore
 
 Debugging
 *********
@@ -237,7 +237,7 @@ Here is an example for building the :zephyr:code-sample:`hello_world` applicatio
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: esp32c6_devkitc
+   :board: esp32c6_devkitc/esp32c6/hpcore
    :goals: build flash
    :gen-args: -DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>
 
@@ -245,9 +245,32 @@ You can debug an application in the usual way. Here is an example for the :zephy
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: esp32c6_devkitc
+   :board: esp32c6_devkitc/esp32c6/hpcore
    :goals: debug
 
+Low-Power CPU (LP CORE)
+***********************
+
+The ESP32-C6 SoC has two RISC-V cores: the High-Performance Core (HP CORE) and the Low-Power Core (LP CORE).
+The LP Core features ultra low power consumption, an interrupt controller, a debug module and a system bus
+interface for memory and peripheral access.
+
+The LP Core is in sleep mode by default. It has two application scenarios:
+
+- Power insensitive scenario: When the High-Performance CPU (HP Core) is active, the LP Core can assist the HP CPU with some speed and efficiency-insensitive controls and computations.
+- Power sensitive scenario: When the HP CPU is in the power-down state to save power, the LP Core can be woken up to handle some external wake-up events.
+
+For more information, check the datasheet at `ESP32-C6 Datasheet`_ or the technical reference
+manual at `ESP32-C6 Technical Reference Manual`_.
+
+The LP Core support is fully integrated with :ref:`sysbuild`. The user can enable the LP Core by adding
+the following configuration to the project:
+
+.. code:: cfg
+
+   CONFIG_ULP_COPROC_ENABLED=y
+
+See :zephyr:code-sample-category:`lp-core` folder as code reference.
 
 References
 **********

boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore.dts

@@ -12,7 +12,7 @@
 #include <espressif/partitions_0x0_default.dtsi>
 
 / {
-	model = "esp32c6_devkitc";
+	model = "esp32c6_devkitc HP Core";
 	compatible = "espressif,esp32c6";
 
 	chosen {

boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore.yaml

@@ -1,5 +1,5 @@
-identifier: esp32c6_devkitc
-name: ESP32-C6
+identifier: esp32c6_devkitc/esp32c6/hpcore
+name: ESP32-C6-DevKitC HP Core
 vendor: espressif
 type: mcu
 arch: riscv

boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore.dts

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/dts-v1/;
+
+#include <espressif/esp32c6/esp32c6_lpcore_wroom_n4.dtsi>
+#include <espressif/partitions_0x0_default.dtsi>
+
+/ {
+	model = "Espressif ESP32C6-DevkitC LPCORE";
+	compatible = "espressif,esp32c6";
+
+	chosen {
+		zephyr,sram = &sramlp;
+		zephyr,code-partition = &slot0_lpcore_partition;
+	};
+};

boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore.yaml

@@ -0,0 +1,16 @@
+identifier: esp32c6_devkitc/esp32c6/lpcore
+name: ESP32-C6-DevKitC LP Core
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+supported:
+  - cpu
+testing:
+  only_tags:
+    - introduction
+  ignore_tags:
+    - kernel
+    - posix
+    - chre
+vendor: espressif

boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore_defconfig

@@ -0,0 +1,15 @@
+# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+# Memory protection
+CONFIG_THREAD_STACK_INFO=n
+CONFIG_THREAD_CUSTOM_DATA=n
+
+# Boot
+CONFIG_BOOT_BANNER=n
+
+# Console
+CONFIG_PRINTK=n
+
+# Build
+CONFIG_SIZE_OPTIMIZATIONS=y

doc/releases/release-notes-4.2.rst

@@ -70,6 +70,9 @@ Deprecated APIs and options
   of a new ``arduino_uno_r4`` board with revisions (``arduino_uno_r4@minima`` and
   ``arduino_uno_r4@wifi``).
 
+* ``esp32c6_devkitc`` board target has been deprecated and renamed to
+  ``esp32c6_devkitc/esp32c6/hpcore``.
+
 New APIs and options
 ====================
 

drivers/timer/Kconfig.esp32

@@ -5,7 +5,7 @@
 
 config ESP32_SYS_TIMER
 	bool "ESP32 sys-timer support (ESP32Cx series)"
-	depends on SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
+	depends on SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || (SOC_SERIES_ESP32C6 && !SOC_ESP32C6_LPCORE)
 	default y
 	select TICKLESS_CAPABLE
 	select TIMER_HAS_64BIT_CYCLE_COUNTER

samples/cpp/hello_world/sample.yaml

@@ -22,3 +22,4 @@ tests:
       - intel_ish_5_4_1
       - intel_ish_5_6_0
       - intel_ish_5_8_0
+      - esp32c6_devkitc/esp32c6/lpcore

samples/net/wifi/shell/sample.yaml

@@ -90,7 +90,7 @@ tests:
       - esp32c3_devkitm
       - esp32s3_devkitm/esp32s3/procpu
       - esp8684_devkitm
-      - esp32c6_devkitc
+      - esp32c6_devkitc/esp32c6/hpcore
   sample.net.wifi.siwx91x_offloaded:
     extra_args:
       - CONFIG_WIFI_SILABS_SIWX91X_NET_STACK_OFFLOAD=y

samples/sysbuild/with_mcuboot/sample.yaml

@@ -13,14 +13,14 @@ tests:
       - esp32s2_devkitc
       - esp32s3_devkitm/esp32s3/procpu
       - esp32c3_devkitm
-      - esp32c6_devkitc
+      - esp32c6_devkitc/esp32c6/hpcore
     integration_platforms:
       - nrf52840dk/nrf52840
       - esp32_devkitc_wrover/esp32/procpu
       - esp32s2_devkitc
       - esp32s3_devkitm/esp32s3/procpu
       - esp32c3_devkitm
-      - esp32c6_devkitc
+      - esp32c6_devkitc/esp32c6/hpcore
     tags: mcuboot
     harness: console
     harness_config:

soc/espressif/Kconfig.ulp

@@ -5,6 +5,8 @@ menu "Ultra Low Power (ULP) Coprocessor"
 
 config ULP_COPROC_ENABLED
 	bool "Ultra Low Power (ULP) Coprocessor"
+	default y if SOC_ESP32C6_LPCORE
+	select SOC_LATE_INIT_HOOK if SOC_ESP32C6_HPCORE
 	help
 	  Enable this feature if you plan to use the ULP Coprocessor.
 	  Once this option is enabled, further ULP co-processor configuration will appear in the menu.

soc/espressif/common/CMakeLists.txt

@@ -44,6 +44,8 @@ set_property(TARGET bintools PROPERTY disassembly_flag_inline_source)
 # Select the image origin depending on the boot configuration
 if(CONFIG_SOC_ESP32_APPCPU OR CONFIG_SOC_ESP32S3_APPCPU)
   dt_nodelabel(dts_partition_path NODELABEL "slot0_appcpu_partition")
+elseif(CONFIG_SOC_ESP32C6_LPCORE)
+  dt_nodelabel(dts_partition_path NODELABEL "slot0_lpcore_partition")
 elseif(CONFIG_MCUBOOT OR CONFIG_ESP_SIMPLE_BOOT)
   dt_nodelabel(dts_partition_path NODELABEL "boot_partition")
 else()
@@ -78,6 +80,8 @@ if(CONFIG_MCUBOOT)
   set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/../${CONFIG_SOC}/mcuboot.ld CACHE INTERNAL "")
 elseif(CONFIG_SOC_ESP32_APPCPU OR CONFIG_SOC_ESP32S3_APPCPU)
   set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/../${CONFIG_SOC}/default_appcpu.ld CACHE INTERNAL "")
+elseif(CONFIG_SOC_ESP32C6_LPCORE)
+  set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/../${CONFIG_SOC}/default_lpcore.ld CACHE INTERNAL "")
 else()
   set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/../${CONFIG_SOC}/default.ld CACHE INTERNAL "")
 endif()

soc/espressif/common/Kconfig.defconfig

@@ -4,7 +4,7 @@
 if SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
 
 config GEN_ISR_TABLES
-	default y
+	default y if !SOC_ESP32C6_LPCORE
 
 config GEN_SW_ISR_TABLE
 	default y
@@ -13,7 +13,7 @@ config GEN_IRQ_VECTOR_TABLE
 	default n
 
 config DYNAMIC_INTERRUPTS
-	default y
+	default y if !SOC_ESP32C6_LPCORE
 
 config ISR_STACK_SIZE
 	default 2048

soc/espressif/esp32c6/CMakeLists.txt

@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
-zephyr_sources(
+zephyr_sources_ifdef(CONFIG_SOC_ESP32C6_HPCORE
   vectors.S
   soc_irq.S
   soc_irq.c
@@ -8,9 +8,18 @@ zephyr_sources(
   ../common/loader.c
   )
 
+zephyr_sources_ifdef(CONFIG_SOC_ESP32C6_LPCORE
+  vector_table_lpcore.S
+  vectors_lpcore.S
+  start_lpcore.S
+  soc_lpcore.c
+  )
+
 zephyr_include_directories(.)
 
+if(CONFIG_SOC_ESP32C6_HPCORE)
   zephyr_sources_ifndef(CONFIG_BOOTLOADER_MCUBOOT hw_init.c)
-
   zephyr_library_sources_ifdef(CONFIG_PM power.c)
   zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c)
+  zephyr_sources_ifdef(CONFIG_ULP_COPROC_ENABLED hpcore_init_ulp.c)
+endif()

soc/espressif/esp32c6/Kconfig

@@ -4,14 +4,15 @@
 config SOC_SERIES_ESP32C6
 	select RISCV
 	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
-	select DYNAMIC_INTERRUPTS
-	select CLOCK_CONTROL
-	select PINCTRL
+	select DYNAMIC_INTERRUPTS if SOC_ESP32C6_HPCORE
+	select CLOCK_CONTROL if SOC_ESP32C6_HPCORE
+	select PINCTRL if SOC_ESP32C6_HPCORE
 	select RISCV_ISA_RV32I
 	select RISCV_ISA_EXT_A
 	select RISCV_ISA_EXT_M
 	select RISCV_ISA_EXT_C
 	select RISCV_ISA_EXT_ZICSR
+	select RISCV_ISA_EXT_ZIFENCEI
 	select HAS_ESPRESSIF_HAL
 	select HAS_PM
 	select HAS_POWEROFF

soc/espressif/esp32c6/Kconfig.defconfig

@@ -18,3 +18,25 @@ config MAIN_STACK_SIZE
 	default 2048
 
 endif # SOC_SERIES_ESP32C6
+
+if SOC_ESP32C6_LPCORE
+
+config GEN_ISR_TABLES
+	default n
+
+config SYS_CLOCK_EXISTS
+	default n
+
+config KERNEL_MEM_POOL
+	default n
+
+config COMMON_LIBC_MALLOC_ARENA_SIZE
+	default 0
+
+config MULTITHREADING
+	default n
+
+config NUM_PREEMPT_PRIORITIES
+	default 0
+
+endif

soc/espressif/esp32c6/Kconfig.soc

@@ -17,6 +17,16 @@ config SOC_ESP32C6
 	bool
 	select SOC_SERIES_ESP32C6
 
+config SOC_ESP32C6_HPCORE
+	bool
+	help
+	  This hidden configuration defines that build is targeted for HP CORE.
+
+config SOC_ESP32C6_LPCORE
+	bool
+	help
+	  This hidden configuration defines that build is targeted for LP CORE.
+
 config SOC_SERIES
 	default "esp32c6" if SOC_SERIES_ESP32C6
 

soc/espressif/esp32c6/default.ld

@@ -66,9 +66,13 @@ MEMORY
   irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN
   drom0_0_seg(R):  org = DROM_SEG_ORG, len = DROM_SEG_LEN
 
+#if CONFIG_ULP_COPROC_ENABLED
+  lp_ram_seg(RW):    org = LPSRAM_IRAM_START + ULP_COPROC_RESERVE_MEM,
+                     len = LPSRAM_SIZE - ULP_COPROC_RESERVE_MEM - CONFIG_RESERVE_RTC_MEM
+#else
   lp_ram_seg(RW):    org = LPSRAM_IRAM_START,
                      len = 0x4000 - CONFIG_RESERVE_RTC_MEM
-
+#endif
   /* We reduced the size of lp_ram_seg by CONFIG_RESERVE_RTC_MEM value.
      It reserves the amount of LP memory that we use for this memory segment.
      This segment is intended for keeping:
@@ -186,7 +190,6 @@ SECTIONS
 #endif
 
   /* --- START OF RTC --- */
-
   .rtc.text :
   {
     . = ALIGN(4);

soc/espressif/soc.yml

@@ -25,3 +25,6 @@ family:
   - name: esp32c6
     socs:
     - name: esp32c6
+      cpuclusters:
+      - name: hpcore
+      - name: lpcore

tests/boards/espressif/rtc_clk/README.rst

@@ -14,7 +14,7 @@ Supported Boards
 ****************
 - esp32_devkitc_wrover/esp32/procpu
 - esp32c3_devkitm
-- esp32c6_devkitc
+- esp32c6_devkitc/esp32c6/hpcore
 - esp32s2_saola
 - esp32s3_devkitm/esp32s3/procpu
 

tests/boards/espressif/rtc_clk/testcase.yaml

@@ -1,19 +1,19 @@
 common:
   integration_platforms:
-    - esp32c6_devkitc
+    - esp32c6_devkitc/esp32c6/hpcore
 tests:
   boards.esp32.rtc_clk:
     platform_allow:
       - esp32_devkitc_wrover/esp32/procpu
       - esp32c3_devkitm
-      - esp32c6_devkitc
+      - esp32c6_devkitc/esp32c6/hpcore
       - esp32s2_saola
       - esp32s3_devkitm/esp32s3/procpu
   boards.esp32.rtc_clk.xtal:
     platform_allow:
       - esp32_devkitc_wrover/esp32/procpu
       - esp32c3_devkitm
-      - esp32c6_devkitc
+      - esp32c6_devkitc/esp32c6/hpcore
       - esp32s2_saola
       - esp32s3_devkitm/esp32s3/procpu
     harness_config:

tests/drivers/pwm/pwm_gpio_loopback/testcase.yaml

@@ -12,7 +12,7 @@ tests:
       - esp32_devkitc_wrover/esp32/procpu
       - esp8684_devkitm
       - esp32c3_devkitm
-      - esp32c6_devkitc
+      - esp32c6_devkitc/esp32c6/hpcore
       - esp32s2_saola
       - esp32s3_devkitm/esp32s3/procpu
 

tests/drivers/uart/uart_elementary/testcase.yaml

@@ -19,7 +19,7 @@ tests:
       - esp32_devkitc_wrover/esp32/procpu
       - esp8684_devkitm
       - esp32c3_devkitm
-      - esp32c6_devkitc
+      - esp32c6_devkitc/esp32c6/hpcore
       - esp32s2_saola
       - esp32s3_devkitm/esp32s3/procpu
     integration_platforms:

west.yml

@@ -162,7 +162,7 @@ manifest:
       groups:
         - hal
     - name: hal_espressif
-      revision: 202c59552dc98e5cd02386313e1977ecb17a131f
+      revision: 1892bfe6ffc859885bc2b0f2e06b6ad9ee436e6b
       path: modules/hal/espressif
       west-commands: west/west-commands.yml
       groups: