boards: espressif: esp32c6: Add LP Core board support
Add ULP Coprocessor board support for C6. This requires a change in the board qualifier depending on the build target. Update esp32c6 overlay and configuration files to the proper name. Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
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46 changed files with 170 additions and 33 deletions
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@ -5,6 +5,8 @@ menu "Ultra Low Power (ULP) Coprocessor"
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config ULP_COPROC_ENABLED
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bool "Ultra Low Power (ULP) Coprocessor"
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default y if SOC_ESP32C6_LPCORE
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select SOC_LATE_INIT_HOOK if SOC_ESP32C6_HPCORE
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help
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Enable this feature if you plan to use the ULP Coprocessor.
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Once this option is enabled, further ULP co-processor configuration will appear in the menu.
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@ -44,6 +44,8 @@ set_property(TARGET bintools PROPERTY disassembly_flag_inline_source)
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# Select the image origin depending on the boot configuration
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if(CONFIG_SOC_ESP32_APPCPU OR CONFIG_SOC_ESP32S3_APPCPU)
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dt_nodelabel(dts_partition_path NODELABEL "slot0_appcpu_partition")
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elseif(CONFIG_SOC_ESP32C6_LPCORE)
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dt_nodelabel(dts_partition_path NODELABEL "slot0_lpcore_partition")
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elseif(CONFIG_MCUBOOT OR CONFIG_ESP_SIMPLE_BOOT)
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dt_nodelabel(dts_partition_path NODELABEL "boot_partition")
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else()
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@ -78,6 +80,8 @@ if(CONFIG_MCUBOOT)
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set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/../${CONFIG_SOC}/mcuboot.ld CACHE INTERNAL "")
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elseif(CONFIG_SOC_ESP32_APPCPU OR CONFIG_SOC_ESP32S3_APPCPU)
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set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/../${CONFIG_SOC}/default_appcpu.ld CACHE INTERNAL "")
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elseif(CONFIG_SOC_ESP32C6_LPCORE)
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set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/../${CONFIG_SOC}/default_lpcore.ld CACHE INTERNAL "")
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else()
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set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/../${CONFIG_SOC}/default.ld CACHE INTERNAL "")
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endif()
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@ -4,7 +4,7 @@
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if SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
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config GEN_ISR_TABLES
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default y
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default y if !SOC_ESP32C6_LPCORE
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config GEN_SW_ISR_TABLE
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default y
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@ -13,7 +13,7 @@ config GEN_IRQ_VECTOR_TABLE
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default n
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config DYNAMIC_INTERRUPTS
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default y
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default y if !SOC_ESP32C6_LPCORE
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config ISR_STACK_SIZE
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default 2048
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@ -1,6 +1,6 @@
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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources(
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zephyr_sources_ifdef(CONFIG_SOC_ESP32C6_HPCORE
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vectors.S
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soc_irq.S
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soc_irq.c
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@ -8,9 +8,18 @@ zephyr_sources(
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../common/loader.c
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)
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zephyr_sources_ifdef(CONFIG_SOC_ESP32C6_LPCORE
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vector_table_lpcore.S
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vectors_lpcore.S
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start_lpcore.S
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soc_lpcore.c
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)
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zephyr_include_directories(.)
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zephyr_sources_ifndef(CONFIG_BOOTLOADER_MCUBOOT hw_init.c)
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zephyr_library_sources_ifdef(CONFIG_PM power.c)
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zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c)
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if(CONFIG_SOC_ESP32C6_HPCORE)
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zephyr_sources_ifndef(CONFIG_BOOTLOADER_MCUBOOT hw_init.c)
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zephyr_library_sources_ifdef(CONFIG_PM power.c)
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zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c)
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zephyr_sources_ifdef(CONFIG_ULP_COPROC_ENABLED hpcore_init_ulp.c)
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endif()
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@ -4,14 +4,15 @@
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config SOC_SERIES_ESP32C6
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select RISCV
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select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
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select DYNAMIC_INTERRUPTS
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select CLOCK_CONTROL
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select PINCTRL
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select DYNAMIC_INTERRUPTS if SOC_ESP32C6_HPCORE
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select CLOCK_CONTROL if SOC_ESP32C6_HPCORE
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select PINCTRL if SOC_ESP32C6_HPCORE
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select RISCV_ISA_RV32I
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select RISCV_ISA_EXT_A
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select RISCV_ISA_EXT_M
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select RISCV_ISA_EXT_C
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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select HAS_ESPRESSIF_HAL
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select HAS_PM
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select HAS_POWEROFF
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@ -18,3 +18,25 @@ config MAIN_STACK_SIZE
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default 2048
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endif # SOC_SERIES_ESP32C6
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if SOC_ESP32C6_LPCORE
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config GEN_ISR_TABLES
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default n
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config SYS_CLOCK_EXISTS
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default n
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config KERNEL_MEM_POOL
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default n
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config COMMON_LIBC_MALLOC_ARENA_SIZE
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default 0
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config MULTITHREADING
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default n
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config NUM_PREEMPT_PRIORITIES
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default 0
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endif
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@ -17,6 +17,16 @@ config SOC_ESP32C6
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bool
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select SOC_SERIES_ESP32C6
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config SOC_ESP32C6_HPCORE
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bool
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help
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This hidden configuration defines that build is targeted for HP CORE.
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config SOC_ESP32C6_LPCORE
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bool
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help
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This hidden configuration defines that build is targeted for LP CORE.
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config SOC_SERIES
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default "esp32c6" if SOC_SERIES_ESP32C6
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@ -66,9 +66,13 @@ MEMORY
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irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN
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drom0_0_seg(R): org = DROM_SEG_ORG, len = DROM_SEG_LEN
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#if CONFIG_ULP_COPROC_ENABLED
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lp_ram_seg(RW): org = LPSRAM_IRAM_START + ULP_COPROC_RESERVE_MEM,
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len = LPSRAM_SIZE - ULP_COPROC_RESERVE_MEM - CONFIG_RESERVE_RTC_MEM
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#else
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lp_ram_seg(RW): org = LPSRAM_IRAM_START,
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len = 0x4000 - CONFIG_RESERVE_RTC_MEM
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#endif
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/* We reduced the size of lp_ram_seg by CONFIG_RESERVE_RTC_MEM value.
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It reserves the amount of LP memory that we use for this memory segment.
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This segment is intended for keeping:
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@ -186,7 +190,6 @@ SECTIONS
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#endif
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/* --- START OF RTC --- */
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.rtc.text :
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{
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. = ALIGN(4);
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@ -25,3 +25,6 @@ family:
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- name: esp32c6
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socs:
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- name: esp32c6
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cpuclusters:
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- name: hpcore
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- name: lpcore
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