boards: espressif: esp32c6: Add LP Core board support

Add ULP Coprocessor board support for C6.
This requires a change in the board qualifier depending on the build
target.
Update esp32c6 overlay and configuration files to the proper name.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
This commit is contained in:
Lucas Tamborrino 2025-01-20 16:50:02 -03:00 committed by Benjamin Cabé
commit c6f84d0ba2
46 changed files with 170 additions and 33 deletions

View file

@ -5,6 +5,8 @@ menu "Ultra Low Power (ULP) Coprocessor"
config ULP_COPROC_ENABLED
bool "Ultra Low Power (ULP) Coprocessor"
default y if SOC_ESP32C6_LPCORE
select SOC_LATE_INIT_HOOK if SOC_ESP32C6_HPCORE
help
Enable this feature if you plan to use the ULP Coprocessor.
Once this option is enabled, further ULP co-processor configuration will appear in the menu.

View file

@ -44,6 +44,8 @@ set_property(TARGET bintools PROPERTY disassembly_flag_inline_source)
# Select the image origin depending on the boot configuration
if(CONFIG_SOC_ESP32_APPCPU OR CONFIG_SOC_ESP32S3_APPCPU)
dt_nodelabel(dts_partition_path NODELABEL "slot0_appcpu_partition")
elseif(CONFIG_SOC_ESP32C6_LPCORE)
dt_nodelabel(dts_partition_path NODELABEL "slot0_lpcore_partition")
elseif(CONFIG_MCUBOOT OR CONFIG_ESP_SIMPLE_BOOT)
dt_nodelabel(dts_partition_path NODELABEL "boot_partition")
else()
@ -78,6 +80,8 @@ if(CONFIG_MCUBOOT)
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/../${CONFIG_SOC}/mcuboot.ld CACHE INTERNAL "")
elseif(CONFIG_SOC_ESP32_APPCPU OR CONFIG_SOC_ESP32S3_APPCPU)
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/../${CONFIG_SOC}/default_appcpu.ld CACHE INTERNAL "")
elseif(CONFIG_SOC_ESP32C6_LPCORE)
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/../${CONFIG_SOC}/default_lpcore.ld CACHE INTERNAL "")
else()
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/../${CONFIG_SOC}/default.ld CACHE INTERNAL "")
endif()

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@ -4,7 +4,7 @@
if SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
config GEN_ISR_TABLES
default y
default y if !SOC_ESP32C6_LPCORE
config GEN_SW_ISR_TABLE
default y
@ -13,7 +13,7 @@ config GEN_IRQ_VECTOR_TABLE
default n
config DYNAMIC_INTERRUPTS
default y
default y if !SOC_ESP32C6_LPCORE
config ISR_STACK_SIZE
default 2048

View file

@ -1,6 +1,6 @@
# SPDX-License-Identifier: Apache-2.0
zephyr_sources(
zephyr_sources_ifdef(CONFIG_SOC_ESP32C6_HPCORE
vectors.S
soc_irq.S
soc_irq.c
@ -8,9 +8,18 @@ zephyr_sources(
../common/loader.c
)
zephyr_sources_ifdef(CONFIG_SOC_ESP32C6_LPCORE
vector_table_lpcore.S
vectors_lpcore.S
start_lpcore.S
soc_lpcore.c
)
zephyr_include_directories(.)
zephyr_sources_ifndef(CONFIG_BOOTLOADER_MCUBOOT hw_init.c)
zephyr_library_sources_ifdef(CONFIG_PM power.c)
zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c)
if(CONFIG_SOC_ESP32C6_HPCORE)
zephyr_sources_ifndef(CONFIG_BOOTLOADER_MCUBOOT hw_init.c)
zephyr_library_sources_ifdef(CONFIG_PM power.c)
zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c)
zephyr_sources_ifdef(CONFIG_ULP_COPROC_ENABLED hpcore_init_ulp.c)
endif()

View file

@ -4,14 +4,15 @@
config SOC_SERIES_ESP32C6
select RISCV
select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
select DYNAMIC_INTERRUPTS
select CLOCK_CONTROL
select PINCTRL
select DYNAMIC_INTERRUPTS if SOC_ESP32C6_HPCORE
select CLOCK_CONTROL if SOC_ESP32C6_HPCORE
select PINCTRL if SOC_ESP32C6_HPCORE
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_C
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
select HAS_ESPRESSIF_HAL
select HAS_PM
select HAS_POWEROFF

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@ -18,3 +18,25 @@ config MAIN_STACK_SIZE
default 2048
endif # SOC_SERIES_ESP32C6
if SOC_ESP32C6_LPCORE
config GEN_ISR_TABLES
default n
config SYS_CLOCK_EXISTS
default n
config KERNEL_MEM_POOL
default n
config COMMON_LIBC_MALLOC_ARENA_SIZE
default 0
config MULTITHREADING
default n
config NUM_PREEMPT_PRIORITIES
default 0
endif

View file

@ -17,6 +17,16 @@ config SOC_ESP32C6
bool
select SOC_SERIES_ESP32C6
config SOC_ESP32C6_HPCORE
bool
help
This hidden configuration defines that build is targeted for HP CORE.
config SOC_ESP32C6_LPCORE
bool
help
This hidden configuration defines that build is targeted for LP CORE.
config SOC_SERIES
default "esp32c6" if SOC_SERIES_ESP32C6

View file

@ -66,9 +66,13 @@ MEMORY
irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN
drom0_0_seg(R): org = DROM_SEG_ORG, len = DROM_SEG_LEN
#if CONFIG_ULP_COPROC_ENABLED
lp_ram_seg(RW): org = LPSRAM_IRAM_START + ULP_COPROC_RESERVE_MEM,
len = LPSRAM_SIZE - ULP_COPROC_RESERVE_MEM - CONFIG_RESERVE_RTC_MEM
#else
lp_ram_seg(RW): org = LPSRAM_IRAM_START,
len = 0x4000 - CONFIG_RESERVE_RTC_MEM
#endif
/* We reduced the size of lp_ram_seg by CONFIG_RESERVE_RTC_MEM value.
It reserves the amount of LP memory that we use for this memory segment.
This segment is intended for keeping:
@ -186,7 +190,6 @@ SECTIONS
#endif
/* --- START OF RTC --- */
.rtc.text :
{
. = ALIGN(4);

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@ -25,3 +25,6 @@ family:
- name: esp32c6
socs:
- name: esp32c6
cpuclusters:
- name: hpcore
- name: lpcore