From c6ebfad7a7d8f9d08fe2eac83182fab3ef45a5cc Mon Sep 17 00:00:00 2001
From: Erwan Gouriou <erwan.gouriou@linaro.org>
Date: Wed, 24 Apr 2019 14:13:27 +0200
Subject: [PATCH] include/arch/arm: linker.ld: Add shared memory sections
 definitions

STM32WB HCI driver requires definition of 2 RAM regions to support
use of 3 shared memory sections: MAPPING_TABLE, MB_MEM1 and MB_MEM2.
In linker.ld, under conditions of HCI driver to be enabled,
define SRAM1 and SRAM2 based on input defined in stm32wb linker.
Then define the 3 sections MAPPING_TABLE, MB_MEM1 and MB_MEM

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
---
 include/arch/arm/cortex_m/scripts/linker.ld | 5 ++++-
 soc/arm/st_stm32/stm32wb/CMakeLists.txt     | 5 +++++
 soc/arm/st_stm32/stm32wb/ipm.ld             | 9 +++++++++
 soc/arm/st_stm32/stm32wb/linker.ld          | 7 ++++++-
 4 files changed, 24 insertions(+), 2 deletions(-)
 create mode 100644 soc/arm/st_stm32/stm32wb/ipm.ld

diff --git a/include/arch/arm/cortex_m/scripts/linker.ld b/include/arch/arm/cortex_m/scripts/linker.ld
index 8b7861c121c..3367ad73df9 100644
--- a/include/arch/arm/cortex_m/scripts/linker.ld
+++ b/include/arch/arm/cortex_m/scripts/linker.ld
@@ -102,7 +102,10 @@ MEMORY
     CCM                   (rw) : ORIGIN = DT_CCM_BASE_ADDRESS, LENGTH = DT_CCM_SIZE * 1K
 #endif
     SRAM                  (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
-
+#ifdef CONFIG_BT_STM32_IPM
+    SRAM1                 (rw) : ORIGIN = RAM1_ADDR, LENGTH = RAM1_SIZE
+    SRAM2                 (rw) : ORIGIN = RAM2_ADDR, LENGTH = RAM2_SIZE
+#endif
     /* Used by and documented in include/linker/intlist.ld */
     IDT_LIST  (wx)      : ORIGIN = (RAM_ADDR + RAM_SIZE), LENGTH = 2K
     }
diff --git a/soc/arm/st_stm32/stm32wb/CMakeLists.txt b/soc/arm/st_stm32/stm32wb/CMakeLists.txt
index 844c5252009..0d9dec4e8f0 100644
--- a/soc/arm/st_stm32/stm32wb/CMakeLists.txt
+++ b/soc/arm/st_stm32/stm32wb/CMakeLists.txt
@@ -2,3 +2,8 @@ zephyr_include_directories(${ZEPHYR_BASE}/drivers)
 zephyr_sources(
   soc.c
   )
+
+zephyr_linker_sources_ifdef(CONFIG_BT_STM32_IPM
+  SECTIONS
+  ipm.ld
+  )
diff --git a/soc/arm/st_stm32/stm32wb/ipm.ld b/soc/arm/st_stm32/stm32wb/ipm.ld
new file mode 100644
index 00000000000..558dff3912f
--- /dev/null
+++ b/soc/arm/st_stm32/stm32wb/ipm.ld
@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2019 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+   MAPPING_TABLE (NOLOAD) : {_sMAPPING_TABLE = .; *(MAPPING_TABLE); _eMAPPING_TABLE = .; } >SRAM1
+   MB_MEM1 (NOLOAD) : { _sMB_MEM1 = .; *(MB_MEM1); _eMB_MEM1 = .; } >SRAM1
+   MB_MEM2 (NOLOAD) : { _sMB_MEM2 = .; *(MB_MEM2); _eMB_MEM2 = .; } >SRAM2
diff --git a/soc/arm/st_stm32/stm32wb/linker.ld b/soc/arm/st_stm32/stm32wb/linker.ld
index ba0abaf5051..2d5b2b61758 100644
--- a/soc/arm/st_stm32/stm32wb/linker.ld
+++ b/soc/arm/st_stm32/stm32wb/linker.ld
@@ -1,9 +1,14 @@
 /* linker.ld - Linker command/script file */
 
 /*
- * Copyright (c) 2014-2016 Wind River Systems, Inc.
+ * Copyright (c) 2019 Linaro Limited
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#define RAM1_SIZE (10 * 1K)
+#define RAM1_ADDR 0x20030000
+#define RAM2_SIZE (20 * 1K)
+#define RAM2_ADDR 0x20038000
+
 #include <arch/arm/cortex_m/scripts/linker.ld>