soc: alder_lake: Add Adler Lake SoC

Add Adler Lake SoC. The SoC is derived from Elkhart Lake SoC.

Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>

dts/bindings/cpu/intel,alder_lake.yaml

@@ -0,0 +1,8 @@
+# Copyright (c) 2023 Intel Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Intel Alder Lake CPU
+
+compatible: "intel,alder-lake"
+
+include: cpu.yaml

dts/x86/intel/alder_lake.dtsi

@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2023 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "skeleton.dtsi"
+#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/pcie/pcie.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "intel,alder_lake";
+			d-cache-line-size = <64>;
+			reg = <0>;
+		};
+
+	};
+
+	dram0: memory@0 {
+		device_type = "memory";
+		reg = <0x0 DT_DRAM_SIZE>;
+	};
+
+	intc: ioapic@fec00000  {
+		compatible = "intel,ioapic";
+		reg = <0xfec00000 0x1000>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+	};
+
+	pcie0: pcie0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "intel,pcie";
+		ranges;
+
+		smbus0: smbus0 {
+			compatible = "intel,pch-smbus";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x54a3>;
+			interrupts = <16 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+
+			status = "okay";
+		};
+
+		uart0: uart0 {
+			compatible = "ns16550";
+
+			vendor-id = <0x8086>;
+			device-id = <0x54a8>;
+
+			clock-frequency = <1843200>;
+			current-speed = <115200>;
+			reg-shift = <2>;
+
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+
+			status = "okay";
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		uart0_legacy: uart@3f8 {
+			compatible = "ns16550";
+			reg = <0x000003f8 0x100>;
+			clock-frequency = <1843200>;
+			interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
+			interrupt-parent = <&intc>;
+			reg-shift = <0>;
+			status = "okay";
+		};
+
+		hpet: hpet@fed00000 {
+			compatible = "intel,hpet";
+			reg = <0xfed00000 0x400>;
+			interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>;
+			interrupt-parent = <&intc>;
+
+			status = "okay";
+		};
+
+		counter: counter@70 {
+			compatible = "motorola,mc146818";
+			reg = <0x70 0x0D 0x71 0x0D>;
+
+			status = "okay";
+		};
+
+		tco_wdt: tco_wdt@400 {
+			compatible = "intel,tco-wdt";
+			reg = <0x0400 0x20>;
+		};
+	};
+};

soc/x86/alder_lake/CMakeLists.txt

@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
+
+zephyr_cc_option(-march=goldmont)
+
+zephyr_library_sources(cpu.c)

soc/x86/alder_lake/Kconfig.defconfig

@@ -0,0 +1,19 @@
+# Alder Lake SoC configuration options
+
+# Copyright (c) 2018-2023 Intel Corporation
+# Copyright (c) 2014-2015 Wind River Systems, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_ALDER_LAKE
+
+config SOC
+	default "alder_lake"
+
+config PCIE_MMIO_CFG
+	default y
+
+config X86_DYNAMIC_IRQ_STUBS
+	default 16
+	depends on DYNAMIC_INTERRUPTS
+
+endif # SOC_ALDER_LAKE

soc/x86/alder_lake/Kconfig.soc

@@ -0,0 +1,11 @@
+# Copyright (c) 2018-2023 Intel Corporation Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_ALDER_LAKE
+	bool "Intel Alder Lake SOC"
+	select X86
+	select CPU_ATOM
+	select PCIE
+	select PCIE_MSI
+	select DYNAMIC_INTERRUPTS
+	select X86_MMU

soc/x86/alder_lake/cpu.c

@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2023 Intel Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+
+uint8_t x86_cpu_loapics[] = { 0x00, 0x02, 0x04, 0x06 };

soc/x86/alder_lake/doc/supported_features.txt

@@ -0,0 +1,14 @@
+Supported Features
+==================
+
+In addition to the standard architecture devices (HPET, local and I/O APICs,
+etc.), Zephyr supports the following Alder Lake-specific SoC devices:
+
+* I2C
+* SMBus
+
+UART Serial Port Support
+-------------------------------------
+
+The Alder Lake UARTs are NS16550-compatible. Baud rate of
+115.2kbps is supported.

soc/x86/alder_lake/linker.ld

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2011-2014, Wind River Systems, Inc.
+ * Copyright (c) 2019-2023 Intel Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/x86/memory.ld>
+
+#ifdef CONFIG_X86_64
+#include <zephyr/arch/x86/intel64/linker.ld>
+#else
+#include <zephyr/arch/x86/ia32/linker.ld>
+#endif /* CONFIG_X86_64 */

soc/x86/alder_lake/soc.h

@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2018-2023, Intel Corporation
+ * Copyright (c) 2010-2015, Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Board configuration macros for the Alder Lake SoC
+ *
+ * This header file is used to specify and describe soc-level aspects for
+ * the 'Alder Lake' SoC.
+ */
+
+#ifndef __SOC_H_
+#define __SOC_H_
+
+#include <zephyr/sys/util.h>
+
+#ifndef _ASMLANGUAGE
+#include <zephyr/device.h>
+#include <zephyr/random/rand32.h>
+#endif
+
+#ifdef CONFIG_GPIO_INTEL
+#include "soc_gpio.h"
+#endif
+
+#if DT_ON_BUS(DT_CHOSEN(zephyr_console), pcie)
+#include <zephyr/drivers/pcie/pcie.h>
+#define X86_SOC_EARLY_SERIAL_PCIDEV PCIE_BDF(0, 0x19, 2) /* uart2 */
+#else
+#define X86_SOC_EARLY_SERIAL_MMIO8_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_console))
+#endif
+
+#endif /* __SOC_H_ */

soc/x86/alder_lake/soc_gpio.h

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2021-2023, Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief GPIO macros for the Alder Lake SoC
+ *
+ * This header file is used to specify the GPIO macros for
+ * the Alder Lake SoC.
+ */
+
+#ifndef __SOC_GPIO_H_
+#define __SOC_GPIO_H_
+
+#define GPIO_INTEL_NR_SUBDEVS		15
+
+#define REG_PAD_OWNER_BASE              0x0020
+#define REG_GPI_INT_STS_BASE            0x0100
+#define PAD_CFG0_PMODE_MASK             (0x0F << 10)
+
+#define REG_PAD_BASE_ADDR		0x000C
+#define REG_GPI_INT_EN_BASE		0x0120
+#define REG_PAD_HOST_SW_OWNER		0x0B0
+#define PAD_BASE_ADDR_MASK              0xfff
+
+#define GPIO_REG_BASE(reg_base) \
+	(reg_base & ~PAD_BASE_ADDR_MASK)
+
+#define GPIO_PAD_BASE(reg_base) \
+	(reg_base & PAD_BASE_ADDR_MASK)
+
+#define GPIO_PAD_OWNERSHIP(raw_pin, pin_offset)					\
+	(pin_offset % 8) ?							\
+		REG_PAD_OWNER_BASE +						\
+			 ((((pin_offset / 8) + 1) + (raw_pin / 8)) * 0x4) :	\
+		REG_PAD_OWNER_BASE +						\
+			 (((pin_offset / 8) + (raw_pin / 8)) * 0x4);		\
+
+#define GPIO_OWNERSHIP_BIT(raw_pin) ((raw_pin % 8) * 4)
+
+#define GPIO_RAW_PIN(pin, pin_offset) pin
+
+#define GPIO_INTERRUPT_BASE(cfg) \
+	(cfg->group_index * 0x4)
+
+#define GPIO_BASE(cfg) \
+	(cfg->group_index * 0x4)
+
+#define PIN_OFFSET 0x10
+
+#endif /* __SOC_GPIO_H_ */