drivers: dai: intel: ssp: add blob 1.5 support
Add support for newer data blob version 1.5. Refactor the code to re-use the common register setting. Clock setting will be handled differently with legacy and version 1.5 blob. Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
This commit is contained in:
Jaska Uimonen
Anas Nashif
parent
3b7f9c320d
commit
c64f91de1a
2 changed files with 95 additions and 34 deletions
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@ -188,6 +188,12 @@ struct dai_intel_ipc4_ssp_mclk_config {
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uint32_t mdivr;
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} __packed;
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struct dai_intel_ipc4_ssp_mclk_config_2 {
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uint32_t mdivctlr;
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uint32_t mdivrcnt;
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uint32_t mdivr[];
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} __packed;
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struct dai_intel_ipc4_ssp_driver_config {
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struct dai_intel_ipc4_ssp_config i2s_config;
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struct dai_intel_ipc4_ssp_mclk_config mclk_config;
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@ -252,4 +258,21 @@ struct dai_intel_ipc4_ssp_configuration_blob {
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union dai_intel_ipc4_ssp_dma_control i2s_dma_control[0];
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} __packed;
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#define SSP_BLOB_VER_1_5 0xee000105
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struct dai_intel_ipc4_ssp_configuration_blob_ver_1_5 {
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union dai_intel_ipc4_gateway_attributes gw_attr;
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uint32_t version;
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uint32_t size;
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/* TDM time slot mappings */
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uint32_t tdm_ts_group[DAI_INTEL_I2S_TDM_MAX_SLOT_MAP_COUNT];
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/* i2s port configuration */
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struct dai_intel_ipc4_ssp_config i2s_ssp_config;
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/* clock configuration parameters */
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struct dai_intel_ipc4_ssp_mclk_config_2 i2s_mclk_control;
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} __packed;
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#endif
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@ -1533,46 +1533,64 @@ out:
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return ret;
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}
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static int dai_ssp_set_config_blob(struct dai_intel_ssp *dp, const struct dai_config *cfg,
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const void *spec_config)
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static int dai_ssp_set_clock_control_ver_1_5(struct dai_intel_ssp *dp,
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const struct dai_intel_ipc4_ssp_mclk_config_2 *cc)
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{
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/* currently we only support 1 divider */
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if (cc->mdivrcnt != 1) {
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LOG_ERR("%s bad clock divider count %u", __func__,
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cc->mdivrcnt);
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return -EINVAL;
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}
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/* ssp blob is set by pcm_hw_params for ipc4 stream, so enable
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* mclk and bclk at this time.
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*/
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dai_ssp_mn_set_mclk_blob(dp, cc->mdivctlr, cc->mdivr[0]);
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return 0;
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}
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static int dai_ssp_set_clock_control_ver_1(struct dai_intel_ssp *dp,
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const struct dai_intel_ipc4_ssp_mclk_config *cc)
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{
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/* ssp blob is set by pcm_hw_params for ipc4 stream, so enable
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* mclk and bclk at this time.
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*/
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dai_ssp_mn_set_mclk_blob(dp, cc->mdivc, cc->mdivr);
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return 0;
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}
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static void dai_ssp_set_reg_config(struct dai_intel_ssp *dp, const struct dai_config *cfg,
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const struct dai_intel_ipc4_ssp_config *regs)
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{
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const struct dai_intel_ipc4_ssp_configuration_blob *blob = spec_config;
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struct dai_intel_ssp_pdata *ssp = dai_get_drvdata(dp);
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uint32_t ssc0, sstsa, ssrsa;
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/* set config only once for playback or capture */
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if (ssp->state[DAI_DIR_PLAYBACK] > DAI_STATE_READY ||
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ssp->state[DAI_DIR_CAPTURE] > DAI_STATE_READY)
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return 0;
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ssc0 = blob->i2s_driver_config.i2s_config.ssc0;
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sstsa = blob->i2s_driver_config.i2s_config.sstsa;
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ssrsa = blob->i2s_driver_config.i2s_config.ssrsa;
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ssc0 = regs->ssc0;
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sstsa = regs->sstsa;
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ssrsa = regs->ssrsa;
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sys_write32(ssc0, dai_base(dp) + SSCR0);
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sys_write32(blob->i2s_driver_config.i2s_config.ssc2 & ~SSCR2_SFRMEN,
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dai_base(dp) + SSCR2); /* hardware specific flow */
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sys_write32(blob->i2s_driver_config.i2s_config.ssc1, dai_base(dp) + SSCR1);
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sys_write32(blob->i2s_driver_config.i2s_config.ssc2 | SSCR2_SFRMEN,
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dai_base(dp) + SSCR2); /* hardware specific flow */
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sys_write32(blob->i2s_driver_config.i2s_config.ssc2, dai_base(dp) + SSCR2);
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sys_write32(blob->i2s_driver_config.i2s_config.ssc3, dai_base(dp) + SSCR3);
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sys_write32(blob->i2s_driver_config.i2s_config.sspsp, dai_base(dp) + SSPSP);
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sys_write32(blob->i2s_driver_config.i2s_config.sspsp2, dai_base(dp) + SSPSP2);
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sys_write32(blob->i2s_driver_config.i2s_config.ssioc, dai_base(dp) + SSIOC);
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sys_write32(blob->i2s_driver_config.i2s_config.sscto, dai_base(dp) + SSTO);
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sys_write32(regs->ssc2 & ~SSCR2_SFRMEN, dai_base(dp) + SSCR2); /* hardware specific flow */
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sys_write32(regs->ssc1, dai_base(dp) + SSCR1);
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sys_write32(regs->ssc2 | SSCR2_SFRMEN, dai_base(dp) + SSCR2); /* hardware specific flow */
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sys_write32(regs->ssc2, dai_base(dp) + SSCR2);
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sys_write32(regs->ssc3, dai_base(dp) + SSCR3);
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sys_write32(regs->sspsp, dai_base(dp) + SSPSP);
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sys_write32(regs->sspsp2, dai_base(dp) + SSPSP2);
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sys_write32(regs->ssioc, dai_base(dp) + SSIOC);
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sys_write32(regs->sscto, dai_base(dp) + SSTO);
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sys_write32(sstsa, dai_base(dp) + SSTSA);
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sys_write32(ssrsa, dai_base(dp) + SSRSA);
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LOG_INF("%s sscr0 = 0x%08x, sscr1 = 0x%08x, ssto = 0x%08x, sspsp = 0x%0x", __func__,
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ssc0, blob->i2s_driver_config.i2s_config.ssc1,
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blob->i2s_driver_config.i2s_config.sscto,
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blob->i2s_driver_config.i2s_config.sspsp);
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ssc0, regs->ssc1, regs->sscto, regs->sspsp);
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LOG_INF("%s sscr2 = 0x%08x, sspsp2 = 0x%08x, sscr3 = 0x%08x", __func__,
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blob->i2s_driver_config.i2s_config.ssc2, blob->i2s_driver_config.i2s_config.sspsp2,
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blob->i2s_driver_config.i2s_config.ssc3);
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regs->ssc2, regs->sspsp2, regs->ssc3);
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LOG_INF("%s ssioc = 0x%08x, ssrsa = 0x%08x, sstsa = 0x%08x", __func__,
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blob->i2s_driver_config.i2s_config.ssioc, ssrsa, sstsa);
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regs->ssioc, ssrsa, sstsa);
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ssp->params.sample_valid_bits = SSCR0_DSIZE_GET(ssc0);
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if (ssc0 & SSCR0_EDSS) {
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@ -1586,14 +1604,34 @@ static int dai_ssp_set_config_blob(struct dai_intel_ssp *dp, const struct dai_co
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ssp->state[DAI_DIR_PLAYBACK] = DAI_STATE_PRE_RUNNING;
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ssp->state[DAI_DIR_CAPTURE] = DAI_STATE_PRE_RUNNING;
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}
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static int dai_ssp_set_config_blob(struct dai_intel_ssp *dp, const struct dai_config *cfg,
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const void *spec_config)
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{
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const struct dai_intel_ipc4_ssp_configuration_blob_ver_1_5 *blob15 = spec_config;
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const struct dai_intel_ipc4_ssp_configuration_blob *blob = spec_config;
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struct dai_intel_ssp_pdata *ssp = dai_get_drvdata(dp);
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int err;
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/* set config only once for playback or capture */
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if (ssp->state[DAI_DIR_PLAYBACK] > DAI_STATE_READY ||
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ssp->state[DAI_DIR_CAPTURE] > DAI_STATE_READY)
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return 0;
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if (blob15->version == SSP_BLOB_VER_1_5) {
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dai_ssp_set_reg_config(dp, cfg, &blob15->i2s_ssp_config);
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err = dai_ssp_set_clock_control_ver_1_5(dp, &blob15->i2s_mclk_control);
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if (err)
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return err;
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} else {
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dai_ssp_set_reg_config(dp, cfg, &blob->i2s_driver_config.i2s_config);
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err = dai_ssp_set_clock_control_ver_1(dp, &blob->i2s_driver_config.mclk_config);
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if (err)
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return err;
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}
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/* ssp blob is set by pcm_hw_params for ipc4 stream, so enable
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* mclk and bclk at this time.
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*/
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dai_ssp_mn_set_mclk_blob(dp, blob->i2s_driver_config.mclk_config.mdivc,
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blob->i2s_driver_config.mclk_config.mdivr);
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ssp->clk_active |= SSP_CLK_MCLK_ES_REQ;
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/* enable TRSE/RSRE before SSE */
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dai_ssp_update_bits(dp, SSCR1, SSCR1_TSRE | SSCR1_RSRE, SSCR1_TSRE | SSCR1_RSRE);
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