arch: arm: Refactor and cleanup nRF52 series arch code

In preparation for the upcoming nRF52840 support, this patch refactors
the nRF52 series support code to allow for future members of the IC
family to be added, while keeping everything that is common together.

JIRA: ZEP-1418

Change-Id: I4200064ca888d72ba0b8629ce94e4ea6384099ad
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>

arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.nrf52832

@@ -28,5 +28,9 @@ config SRAM_SIZE
 config FLASH_SIZE
 	default 512
 
+config NUM_IRQS
+	int
+	default 39
+
 endif # SOC_NRF52832
 

arch/arm/soc/nordic_nrf5/nrf52/Kconfig.defconfig.series

@@ -35,10 +35,6 @@ config SRAM_BASE_ADDRESS
 config FLASH_BASE_ADDRESS
 	default 0x00000000
 
-config NUM_IRQS
-	int
-	default 39
-
 config NUM_IRQ_PRIO_BITS
 	int
 	default 3

arch/arm/soc/nordic_nrf5/nrf52/Kconfig.series

@@ -19,6 +19,7 @@ config  SOC_SERIES_NRF52X
 	bool "Nordic Semiconductor nRF52 series MCU"
 	select CPU_CORTEX_M
 	select CPU_CORTEX_M4
+	select CPU_HAS_FPU
 	select SOC_FAMILY_NRF5
 	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
 	select XIP

arch/arm/soc/nordic_nrf5/nrf52/Kconfig.soc

@@ -21,6 +21,5 @@ depends on SOC_SERIES_NRF52X
 
 config SOC_NRF52832
 	bool "NRF52832"
-	select CPU_HAS_FPU
 
 endchoice

arch/arm/soc/nordic_nrf5/nrf52/Makefile

@@ -1,7 +1,7 @@
 ZEPHYRINCLUDE += -I$(srctree)/arch/arm/soc/nordic_nrf5/include
 
-ifdef CONFIG_SOC_SERIES_NRF52X
+ifdef CONFIG_SOC_NRF52832
-soc-cflags += -DNRF52
+soc-cflags += -DNRF52832_XXAA
 endif
 
 obj-y += soc.o

arch/arm/soc/nordic_nrf5/nrf52/soc.c

@@ -38,36 +38,48 @@ extern void _NmiInit(void);
 
 #define __SYSTEM_CLOCK_64M (64000000UL)
 
-static bool ftpan_32(void);
+#ifdef CONFIG_SOC_NRF52832
-static bool ftpan_37(void);
+static bool ftpan_32(void)
-static bool ftpan_36(void);
-
-uint32_t SystemCoreClock __used = __SYSTEM_CLOCK_64M;
-
-static void clock_init(void)
 {
-	SystemCoreClock = __SYSTEM_CLOCK_64M;
+	if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
+		(((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
+		if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
+			(((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
+			return true;
+		}
+	}
+
+	return false;
 }
 
-static int nordicsemi_nrf52_init(struct device *arg)
+static bool ftpan_37(void)
 {
-	uint32_t key;
+	if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
+		(((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
+		if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
+			(((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
+			return true;
+		}
+	}
 
-	ARG_UNUSED(arg);
+	return false;
+}
 
-	/* Note:
+static bool ftpan_36(void)
-	* Magic numbers below are obtained by reading the registers
+{
-	* when the SoC was running the SAM-BA bootloader
+	if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
-	* (with reserved bits set to 0).
+		(((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
-	*/
+		if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
+			(((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
+			return true;
+		}
+	}
 
-	key = irq_lock();
+	return false;
-
+}
-	/* Setup the vector table offset register (VTOR),
-	* which is located at the beginning of flash area.
-	*/
-	_scs_relocate_vector_table((void *)CONFIG_FLASH_BASE_ADDRESS);
 
+static void nordicsemi_nrf52832_init(void)
+{
 	/* Workaround for FTPAN-32 "DIF: Debug session automatically
 	* enables TracePort pins" found at Product Anomaly document
 	* for your device located at https://www.nordicsemi.com/
@@ -94,18 +106,15 @@ static int nordicsemi_nrf52_init(struct device *arg)
 	}
 
 	/* Enable the FPU if the compiler used floating point unit
-	* instructions. __FPU_USED is a MACRO defined by the
+	* instructions. Since the FPU consumes energy, remember to
-	* compiler. Since the FPU consumes energy, remember to
 	* disable FPU use in the compiler if floating point unit
 	* operations are not used in your code.
 	*/
-	#if (__FPU_USED == 1)
+#if defined(CONFIG_FLOAT)
-
 	SCB->CPACR |= (3UL << 20) | (3UL << 22);
 	__DSB();
 	__ISB();
-
+#endif
-	#endif
 
 	/* Configure NFCT pins as GPIOs if NFCT is not to be used in
 	* your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
@@ -113,8 +122,7 @@ static int nordicsemi_nrf52_init(struct device *arg)
 	* will be reserved for NFC and will not be available as
 	* normal GPIOs.
 	*/
-	#if defined(CONFIG_NFCT_PINS_AS_GPIOS)
+#if defined(CONFIG_NFCT_PINS_AS_GPIOS)
-
 	if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) ==
 	    (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)) {
 
@@ -132,8 +140,7 @@ static int nordicsemi_nrf52_init(struct device *arg)
 		}
 		NVIC_SystemReset();
 	}
-
+#endif
-	#endif
 
 	/* Configure GPIO pads as pPin Reset pin if Pin Reset
 	* capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
@@ -141,7 +148,7 @@ static int nordicsemi_nrf52_init(struct device *arg)
 	* Product Specification to see which one) will then be
 	* reserved for PinReset and not available as normal GPIO.
 	*/
-	#if defined(CONFIG_GPIO_AS_PINRESET)
+#if defined(CONFIG_GPIO_AS_PINRESET)
 	if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) !=
 	     (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
 	    ((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) !=
@@ -165,30 +172,55 @@ static int nordicsemi_nrf52_init(struct device *arg)
 		}
 		NVIC_SystemReset();
 	}
-	#endif
+#endif
 
 	/* Enable SWO trace functionality. If ENABLE_SWO is not
 	* defined, SWO pin will be used as GPIO (see Product
 	* Specification to see which one).
 	*/
-	#if defined(ENABLE_SWO)
+#if defined(ENABLE_SWO)
-
 	CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
 	NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial <<
 				  CLOCK_TRACECONFIG_TRACEMUX_Pos;
-	#endif
+#endif
 
 	/* Enable Trace functionality. If ENABLE_TRACE is not
 	* defined, TRACE pins will be used as GPIOs (see Product
 	* Specification to see which ones).
 	*/
-	#if defined(ENABLE_TRACE)
+#if defined(ENABLE_TRACE)
 	CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
 	NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel <<
 				  CLOCK_TRACECONFIG_TRACEMUX_Pos;
-	#endif
+#endif
+}
+#endif /* CONFIG_SOC_NRF52832 */
 
-	/* Clear all faults */
+uint32_t SystemCoreClock __used = __SYSTEM_CLOCK_64M;
+
+static void clock_init(void)
+{
+	SystemCoreClock = __SYSTEM_CLOCK_64M;
+}
+
+static int nordicsemi_nrf52_init(struct device *arg)
+{
+	uint32_t key;
+
+	ARG_UNUSED(arg);
+
+	key = irq_lock();
+
+	/* Setup the vector table offset register (VTOR),
+	 * which is located at the beginning of flash area.
+	 */
+	_scs_relocate_vector_table((void *)CONFIG_FLASH_BASE_ADDRESS);
+
+#ifdef CONFIG_SOC_NRF52832
+	nordicsemi_nrf52832_init();
+#endif
+
+	/* Reset all faults */
 	_ScbMemFaultAllFaultsReset();
 	_ScbBusFaultAllFaultsReset();
 	_ScbUsageFaultAllFaultsReset();
@@ -208,43 +240,4 @@ static int nordicsemi_nrf52_init(struct device *arg)
 	return 0;
 }
 
-static bool ftpan_32(void)
-{
-	if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
-	    (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
-		if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
-		    (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
-			return true;
-		}
-	}
-
-	return false;
-}
-
-static bool ftpan_37(void)
-{
-	if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
-	    (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
-		if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
-		    (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
-			return true;
-		}
-	}
-
-	return false;
-}
-
-static bool ftpan_36(void)
-{
-	if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
-	    (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
-		if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
-		    (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
-			return true;
-		}
-	}
-
-	return false;
-}
-
 SYS_INIT(nordicsemi_nrf52_init, PRE_KERNEL_1, 0);