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board/nsim: Refactor device tree description

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Instead of blind copy of nsim_em.dts re-structure this way:
 * nsim.dtsi     - Top-level "board" description re-usable for
 |                 all nSIM-based "boards".
 |
 |                 Even though it's not needed right now but it
 |                 allows to add other ARC core families in the future.
 |
 \_ nsim_em.dtsi - Common definitions for boards with ARC EM cores
    |
    \_ Real boards with ARC EM cores
      |
      \ nsim_em.dts
      \ nsim_sem.dts
      \ nsim_em_mpu_stack_guard.dts
      \ nsim_sem_mpu_stack_guard.dts

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This commit is contained in:
Alexey Brodkin 2019-06-04 13:25:44 +03:00 • committed by Anas Nashif
commit c5663caf77
6 changed files with 96 additions and 49 deletions
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46
boards/arc/nsim/nsim.dtsi Normal file
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@ -0,0 +1,46 @@
/*
* Copyright (c) 2018, 2019, Synopsys, Inc. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include "skeleton.dtsi"
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
intc: arcv2-intc {
compatible = "snps,arcv2-intc";
interrupt-controller;
#interrupt-cells = <2>;
};
};
iccm0: iccm@0 {
device_type = "memory";
compatible = "arc,iccm";
reg = <0x0 0x80000>;
};
dccm0: dccm@80000000 {
device_type = "memory";
compatible = "arc,dccm";
reg = <0x80000000 0x80000>;
};
uart0: uart@f0000000 {
compatible = "snps,nsim-uart";
reg = <0xf0000000 0x100>;
label = "UART_0";
};
chosen {
zephyr,sram = &dccm0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
};
};

48
boards/arc/nsim/nsim_em.dts
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@ -1,56 +1,14 @@
/* /*
* Copyright (c) 2018, Synopsys, Inc. All rights reserved. * Copyright (c) 2018, 2019, Synopsys, Inc. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
/dts-v1/; /dts-v1/;
#include "skeleton.dtsi" #include "nsim_em.dtsi"
/ { / {
model = "snps,nsim_em";
model = "nsim_em";
compatible = "snps,nsim_em"; compatible = "snps,nsim_em";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,arcem";
reg = <1>;
};
intc: arcv2-intc {
compatible = "snps,arcv2-intc";
interrupt-controller;
#interrupt-cells = <2>;
};
};
iccm0: iccm@0 {
device_type = "memory";
compatible = "arc,iccm";
reg = <0x0 0x80000>;
};
dccm0: dccm@80000000 {
device_type = "memory";
compatible = "arc,dccm";
reg = <0x80000000 0x80000>;
};
uart0: uart@f0000000 {
compatible = "snps,nsim-uart";
reg = <0xf0000000 0x100>;
label = "UART_0";
};
chosen {
zephyr,sram = &dccm0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
};
}; };

22
boards/arc/nsim/nsim_em.dtsi Normal file
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/*
* Copyright (c) 2019, Synopsys, Inc. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include "nsim.dtsi"
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,arcem";
reg = <0>;
};
};
};

9
boards/arc/nsim/nsim_em_mpu_stack_guard.dts
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@ -4,4 +4,11 @@
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
#include "nsim_em.dts" /dts-v1/;
#include "nsim_em.dtsi"
/ {
model = "snps,nsim_em_mpu_stack_guard";
compatible = "snps,nsim_em_mpu_stack_guard";
};

11
boards/arc/nsim/nsim_sem.dts
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@ -1,7 +1,14 @@
/* /*
* Copyright (c) 2018, Synopsys, Inc. All rights reserved. * Copyright (c) 2018, 2019, Synopsys, Inc. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
#include "nsim_em.dts" /dts-v1/;
#include "nsim_em.dtsi"
/ {
model = "snps,nsim_sem";
compatible = "snps,nsim_sem";
};

9
boards/arc/nsim/nsim_sem_mpu_stack_guard.dts
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@ -4,4 +4,11 @@
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
#include "nsim_em.dts" /dts-v1/;
#include "nsim_em.dtsi"
/ {
model = "snps,nsim_sem_mpu_stack_guard";
compatible = "snps,nsim_sem_mpu_stack_guard.dts";
};